Influence of a PCB Layout Design on the Efficiency of Heat Dissipation and Mutual Thermal Couplings between Transistors

Abstract

This article presents the results of the investigations concerning the influence of the printed circuit board (PCB) layout design on self and transfer transient thermal impedances characterizing thermal phenomena occurring in the network containing two power MOSFETs. The tested devices have the case D²PAK and are soldered to the PCB using the surface mount technology (SMT). The measurement method is described. The tested transistors are presented with the used PCBs on which they are mounted. The obtained measurement results of the mentioned thermal parameters of the tested transistors operating on all the tested PCBs are shown and discussed. The influence of a cooling area of the tested PCBs on the parameters describing self and transfer transient thermal impedances is analyzed.

1. Introduction

Power transistors are important components of electronic and power circuits [1,2]. During the operation of these semiconductor devices, thermal phenomena, such as self-heating and thermal couplings, occur inside them [3,4,5,6]. These phenomena cause an increase in the junction temperature of these transistors [3,4,7,8,9,10], worsening their parameters and reliability [11,12,13]. Therefore, designers of electronic devices containing transistors apply solutions that allow the efficient dissipation of the heat generated inside these semiconductor devices to the ambient. Examples of such solutions are passive and active cooling systems described in the papers [14].

The authors of the papers [14] proved experimentally that improvement in cooling efficiency can be achieved, among others, using heatsinks and fans. In turn, the paper [15] analyzes fluid cooling systems, which can be much more effective than free convection cooling systems. In the paper [16], it is proved that by enhancing a cooling system, cooling efficiency can be improved so efficiently that the allowable power dissipated inside the cooled device can increase even 40 times. Due to a lack of moving parts, the lifetime of free convection cooling systems is much longer. In such systems, the improvement of heat transfer is achieved by enhancing the area in which the convection occurs [17]. The problem of the improving cooling efficiency of such devices as power LEDs is considered in the papers [18,19,20,21]. One of the discussed methods is the use of the metal core PCB [18].

The application note [22] analyzes the thermal performance of CoolSiC MOSFETs in TO-263 packages and soldered on the printed circuit boards (PCB) of a different number of layers. The test results show that a 4-layer board has a better cooling effect than a 2-layer board. It was found that 0.4 mm thermal vias under and around the soldering pad led to lower temperature changes. The soldering mask around the pad increases the total thermal resistance R_thja by about 4 K/W. Moreover, a heat sink improves thermal performance when the total drain copper area is limited to 2.7 times the copper area under the pad. It was also shown that a copper heat sink is a better choice than an aluminium heat sink. Excellent heat performance can be obtained even without a heat sink when the via matrix size is large.

In the paper [23], the results of the analysis of the influence of a number of thermal vias on the value of the thermal resistance of a substrate are presented. The analysis was performed using the finite element method (FEM) and two analytic methods—a 1-dimensional heat flow model and a circular fin model. The authors also calculated the values of the analysis error of both the analytic methods in comparison with the results obtained with the FEM method.

In the paper [24], general considerations and practical hints related to the application of thermal vias for cooling SMD devices are presented. The important role of filling the thermal vias with thermoconducting material (e.g., copper) in order to achieve the maximum heat transfer efficiency was pointed out. It was also noted that in some applications, the role of traces in the overall thermal balance can be important. The authors enlisted potential problems resulting from the application of thermal vias without a fill, such as solderwicking, air and moisture entrapment, and associated lower long-term reliability.

The paper [25] analyzes the thermal relationship between the SMD packages via design on the PCB level and the achievable thermal resistance. The goal of the investigations was to show the best combination to keep the packages as cool as possible while also considering the cost. The reason for optimal thermal management is that, as a rule of thumb, a 10 K rise in temperature doubles the failure rate. In the analysis, the influence of solder voids on thermal parameters of selected SMD package type ThinPAK was included.

In the paper [26], the PCB-Investigator Physics software for thermal analysis of PCB designs is described. Based on an example of the selected PCB, the influence of a number of thermal vias on the temperature of a device being a source of heat soldered onto this PCB was discussed. It was proved that increasing the number of thermal vias above a certain value has no justification because it does not cause a further visible increase in heat transfer from the cooled device.

In the paper [27], the possibilities of using Al-SiC material as a substrate of the PCBs used, e.g., for printed electronics, are presented.

The paper [28] shows the results of thermal investigations with different CoolMOS chips in the D²PAK-7 package placed on a high-voltage Insulated Metal Substrate (IMS). Such transistors are used for automotive applications in electric vehicles, such as on-board chargers and on-board DC-DC converters. The final data indicates that the IMS is an excellent choice for high-power applications since the thermal resistance from the heat source towards the heat sink (the liquid cooling system) is very low in comparison with other substrates (such as FR4).

The paper [29] compares the thermal performance between the FR-4 (NEMA grade designation for the glass-reinforced epoxy laminate material) and the IMS PCB in a three-phase GaN inverter for motor drives and helps engineers make an informed choice on the most suitable PCB design for a given application. The cited paper shows that the FR-4 PCB has a 45% higher value of thermal resistance compared with the IMS PCB. The main difference is in the choice of the TIM that was mandated due to the lower mechanical strength of the thin FR-4 PCB. A more optimal FR-4 PCB-based solution might be a 1.6-mm PCB with a phase-change TIM to enable a lower value of thermal resistance for the FR-4 PCB, which may have thermal resistance only 15–20% higher than the IMS PCB. The selection of suitable PCB thickness should be made to optimize between the required mechanical strength and the RVIAS in the FR-4 PCBs.

Phase-change TIMs provide superior thermal performance compared with adhesive TIMs, and the PCB designer should ensure sufficient clamping downforce using a suitable mounting mechanism to enable the use of a phase-change TIM with the FR-4 PCBs—the use of the adhesive TIM can be a major roadblock to achieving necessary thermal performance. The IMS PCBs can also work with thermal grease, which has better thermal performance than even a phase-change TIM. The IMS PCBs come at a higher cost but provide a significant advantage over the FR-4 PCBs in the high power, high-density applications with forced-air or liquid cooling or in applications with high ambient temperature requirements and small temperature margins.

As is visible from the presented literature review, there is a lack of papers in which the problem of the influence of the design of the used PCB on the parameters characterizing both self-heating and mutual thermal couplings is considered. Therefore, the aim of this article is to investigate the thermal properties of power MOSFETs mounted on PCBs of the same dimensions and with a different design of the layout.

In this paper, the results of the experimental investigations illustrating the influence of the PCB layout design on the thermal parameters of SMD power transistors soldered onto a common PCB are presented. Both the parameters characterizing self-heating and mutual thermal couplings are considered. The measurements were performed using the indirect electrical method. Both free-air convection cooling and forced convection two-phase fluid cooling were considered. The results of the measurements are presented and discussed. It is pointed out in which cases the influence of mutual thermal couplings between transistors can be neglected during the estimation of the junction temperature of these transistors. We also discussed the influence of the area of the copper layer and the number of metal vias connecting both sides of the tested PCB on the values of self and mutual thermal resistances of the tested devices.

Section 2 presents a manner of describing the thermal parameters of the transistors. Section 3 presents the method used for the measurements. Section 4 presents the tested devices and the layout of PCBs. The results of the measurements are presented and discussed in Section 5.

2. Description of Thermal Properties of Transistors

A parameter characterizing the cooling efficiency of a semiconductor device is its transient thermal impedance Z_th(t) [30,31]. This parameter can be used to calculate an increase in the junction temperature of transistor T_j caused by self-heating phenomena. In practical applications, there is usually more than one transistor placed on a common PCB or mounted onto a common heat sink. In such a case, mutual thermal couplings occur between the transistors. These thermal couplings are characterized by transient thermal impedance Z_thm(t).

Applying the classical thermal model [32] for a circuit comprising two transistors, the dependence of the waveform of the junction temperature T_j1(t) of transistor T₁ on the power dissipated in this transistor p_T1(t) and the power p_T2(t) dissipated in the second transistor placed onto the same substrate can be given in the form

$${\mathrm{T}}_{\mathrm{j}1}\left(\mathrm{t}\right)={\mathrm{T}}_{\mathrm{a}}+\underset{0}{\overset{\mathrm{t}}{\int }}{\mathrm{Z}}_{\mathrm{th}}^{\prime }(\mathrm{t}-\mathrm{v})·{\mathrm{p}}_{\mathrm{T}1}\left(\mathrm{v}\right)\mathrm{dv}+\underset{0}{\overset{\mathrm{t}}{\int }}{\mathrm{Z}}_{\mathrm{thm}}^{\prime }(\mathrm{t}-\mathrm{v})·{\mathrm{p}}_{\mathrm{T}2}\left(\mathrm{v}\right)\mathrm{dv}$$

(1)

where T_a denotes the ambient temperature, Z’_th(t)—time differentiation of transient thermal impedance Z_th(t), whereas Z’_thm(t)—time differentiation of transfer transient thermal impedance Z_thm(t).

Waveforms of Z_th(t) and Z_thm(t) typically are given by the formula [30,33,34]

$${\mathrm{Z}}_{\mathrm{t}\mathrm{h}}\left(\mathrm{t}\right)={\mathrm{R}}_{\mathrm{t}\mathrm{h}}·\left(1-{\displaystyle \sum _{\mathrm{i}=1}^{\mathrm{N}}{\mathrm{a}}_{\mathrm{i}}·\exp \left(-\frac{\mathrm{t}}{{\mathrm{\tau }}_{\mathrm{t}\mathrm{h}\mathrm{i}}}\right)}\right)$$

(2)

where R_th is thermal resistance, a_i is the weighting factor related to the thermal time constant τ_thi, and N is the number of thermal time constants.

The correct calculation of the value of the junction temperature of the transistors placed on the same substrate while the waveforms of the power dissipated in these transistors are different requires the knowledge of waveforms of Z_th(t) and Z_thm(t). In order to achieve the lowest value of the junction temperature of a transistor, the lowest values of these parameters are desired.

In the case of SMD devices, special fields of metallization, typically connected with a soldering pad of the device intended for spreading and dissipating the heat generated inside these devices, are used [35]. These fields of metallization are called thermal pads. Thermal pads can be placed on the mounting side of a PCB but also on the other side and in internal layers in the case of multi-layer PCBs. In order to further improve heat spreading and dissipation, thermal pads placed in different layers of a PCB are typically connected with metalized wall drills, i.e., so-called thermal vias. In order to achieve the best heat transfer between the layers, thermal vias can be additionally filled in with thermos-conducting material, e.g., copper. In the paper [34], it is proved that the application of such a thermal pad allows reducing the thermal resistance of a semiconductor device even by 20%. This means that thermal pads are important parts of a PCB layout.

3. Measurement Method

The results of the investigations described in the paper refer to two power MOS transistors in D²PAK packages soldered to a common substrate, through which they are thermally coupled. Transistor M_A is an active transistor, i.e., there is power dissipated in it, causing an increase in its junction temperature related to self-heating. Transistor M_P is a passive transistor. Its junction temperature goes up only as a result of heat conduction from transistor M_A through the common substrate, i.e., thermal coupling.

The schematic diagram of the measurement setup used during the investigations is presented in Figure 1. Thermal parameters of the investigated transistors Z_th(t) Z_thw(t), R_th, and R_thw are calculated using the indirect method based on the dependence of one of the electric parameters of a transistor on temperature. It is a so-called thermal parameter (TSP).

In a circuit shown in Figure 1, the thermal parameter of the M_A transistor is the gate-source voltage V_GS, and in the case of the M_P transistor, it is the voltage on the reverse-polarized antiparallel diode V_F. The circuit allows recording a cooling curve, i.e., time changes of the selected TSP (TSP(t)) during the device cooling.

The use of the selected measurement method requires, in the first place, the measurements of the dependence of TSP on temperature, i.e., the so-called thermometric characteristic in a proper polarization circuit of the transistor. The polarization circuit differs depending on the selected thermal parameter. In Figure 1, polarization circuits of transistors M_A and M_P are marked with yellow color. Transistor M_A is polarized to operate in saturation, while transistor M_P—in the diode configuration. Polarization circuits ensure the flow of measurement currents I_MA and I_MP. Their values are selected in such a way that they do not cause self-heating of the transistors.

In order to perform measurements of the thermometric characteristics, the investigated transistors are placed inside a thermostatic chamber with the internal temperature, which can be set in a broad range, e.g., 20–150 °C. Next, the measurements of the values of TSP at different temperatures take place. The correct implementation of the method requires that during the measurement of TSP, the junction temperature T_j of the transistor should be equal to the setting of the chamber temperature T_k.

The next stage of the measurements takes place outside the thermostatic chamber in the following steps:

(a)

Heating the active transistor M_A and the passive transistor M_P up to achieve thermally stable conditions at a specified level of the power dissipated in the transistor M_A. Transistor M_A is polarized using voltage sources V_D vs. V_M. Switch S₁ is in position 1. When heating, power p(t) is dissipated in transistor M_A.

(b)

Cooling the active transistor M_A and the transistor M_P and recording time changes of the values of their TSPs in a range of time from t₀ = 0 to t. Cooling begins at the moment of a change of switch S₁ from position 1 to 2. The moment of a change of switch S₁ position corresponds to time t₀ when recording the values of TSP of both the transistors connected with a drop of their junction temperature starts. When cooling, transistor M_A is polarized from voltage sources V_D and V_M. Only the current I_MA of the value at which the thermometric characteristic was measured flows through both the transistors when cooling.

Thermal parameters of transistors M_A and M_P are calculated based on the measured characteristics TSP(T_a) and TSP(t) in a way described below. The thermal parameter of transistor M_A is the gate-source voltage V_GS, and transistor M_P—is the voltage across the antiparallel diode V_F.

After the measurements of the thermometric characteristics of both the transistors, functions approximating them are determined. Based on the results shown in the paper [14], a linear approximation of the dependence T_a(V_F) with the coefficients a₁ and a₀ as well as a quadratic approximation of the dependence T_a(V_GS) with the coefficients b₂, b_1, and b₀ were chosen.

Waveforms Z_th(t) and Z_thm(t) are calculated based on the waveforms of voltages V_GS(t) and V_F(t) from the following formulas.

$${\mathrm{Z}}_{\mathrm{t}\mathrm{h}}\left(\mathrm{t}\right)=\frac{{\mathrm{T}}_{\mathrm{j}}\left(\mathrm{t}=0\right)-{\mathrm{T}}_{\mathrm{j}}\left(\mathrm{t}\right)}{{\mathrm{V}}_{\mathrm{D}\mathrm{S}1}·{\mathrm{I}}_1}$$

(3)

$${\mathrm{Z}}_{\mathrm{t}\mathrm{h}\mathrm{m}}\left(\mathrm{t}\right)=\frac{{\mathrm{a}}_1·\left({\mathrm{V}}_{\mathrm{F}}\left(\mathrm{t}=0\right)+{\mathrm{V}}_{\mathrm{F}}\left(\mathrm{t}\right)\right)}{{\mathrm{V}}_{\mathrm{D}\mathrm{S}1}·{\mathrm{I}}_1}$$

(4)

where temperature T_j is calculated from the formula

$${\mathrm{T}}_{\mathrm{j}}\left(\mathrm{t}\right)={\mathrm{b}}_2·{\left({\mathrm{V}}_{\mathrm{G}\mathrm{S}}\left(\mathrm{t}\right)\right)}^2+{\mathrm{b}}_1·{\mathrm{V}}_{\mathrm{G}\mathrm{S}}\left(\mathrm{t}\right)+{\mathrm{b}}_0$$

(5)

4. Tested PCBs

In order to investigate the efficiency of the heat transfer from transistor M_A and the thermal coupling between transistor M_A and M_P, nine two-sided printed boards were designed and manufactured. SMD power MOS-FET transistors FDB52N20 were selected for investigations. They are characterized by the following parameters [36]: v_DSmax = 200 V, i_Dmax = 52 A, R_DS(on)max = 49 mΩ. The manufacturer states in the datasheet also the values of the thermal parameters. The thermal resistance junction-case R_thj-c is less than 0.35 K/W. The maximum value of the thermal resistance junction-ambient R_thj-a = 62.5 K/W in the case of soldering the transistor to a standard pad, and R_thj-a = 40 K/W in the case when the transistor is soldered to a pad of an area increased to 6.45 cm² (1 in²).

The view of the investigated PCBs is shown in Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9 and Figure 10. All the PCBs are made of epoxy resin laminate reinforced with fiberglass (FR-4) and have the dimensions 30.48 mm × 40.64 mm. The thickness of the PCBs is 1.55 mm, and the thickness of metallization is 35 µm (2 oz copper). The boards are covered with an anti-soldering mask. Soldering pads are covered with a layer of LF HASL (Lead-Free Hot Air Solder Level). On all the boards, there are two soldering pads dedicated to power MOSFET transistors in D²PAK packages. The dimensions of the soldering pads are 10.16 mm × 10.16 mm, and the surface area is 103.22 mm².

The reference design is board B1. Only the standard soldering pads for the transistors are located on it. On the remaining eight boards, the layout solutions used to improve the thermal properties of the board were added. On the B2 board, an additional field of metallization of the dimensions 17.78 mm × 20.32 mm (361.23 mm²) was added in the bottom layer. On boards B3 and B4, thermal vias of a diameter of 0.35 mm were added. On both boards, all the vias are located within the outline of the transistors soldering pads. There are 25 thermal vias under every transistor on board B3 and 49 vias on board B4. On board B5, the diameter of the vias was modified to 0.6 mm. On board B6, an additional field of metallization was added on the top layer of the board. The dimensions of this field are 16.51 mm × 17.78 mm (293.55 mm²). There are 75 thermal vias of a 0.35 mm diameter. These vias are located outside the outline of the soldering pads of the transistors. Boards B7, B8, and B9 have the same metallization area on both sides as board B6. However, there are 49 thermal vias of 0.6 mm diameter located within the outline of the soldering pad of each transistor.

Additionally, on the top layer of boards, B7, B8, and B9 soldering pads for two types of heatsinks dedicated to D²PAK packages are located. On board B8, the metallization field in the bottom layer was left without the soldering mask.

The heatsinks used in the study are presented in Figure 11. The heatsink shown in Figure 11a produced by Fisher Elektronik [37] was soldered to boards B7 and B8. It is a heatsink made of a copper plate of a thickness of 0.6 mm, stamped, folded, and plated. In turn, in Figure 11b, the heatsink produced by Ohmite [38] and soldered to board B9 is shown. This heatsink is made of extruded and black anodized aluminium.

The view of board B1 with the transistors soldered is presented in Figure 12.

The distance between the packages of the transistors is 10 mm. The heatsinks were soldered only on the side of an active transistor.

5. Results

Using the measurement method described in Section 2, the measurements of self and mutual transient thermal impedances of the transistors soldered onto the boards characterized in Section 3 were carried out.

In Figure 13, the waveforms of self-transient thermal impedance Z_th(t) of the active transistors on all the investigated boards (B1–B9) are shown. The measurements were taken at the power dissipated in the investigated transistors equal to 2 W. During the measurements, the boards were placed in a lateral orientation facing the transistors.

As it can be noticed, a change in the layout design causes significant changes in Z_th(t) waveforms. The most efficient cooling was achieved with the transistors placed on board B9, and the least efficient with the transistors placed on board B1. For example, the values of Z_th(t) obtained in the steady state are in a range from 28 K/W to 56 K/W, so they differ from each other even twice. The settling time of the measured waveforms is several hundred seconds.

In Figure 14, the waveforms of mutual transient thermal impedance Z_thm(t) of the passive transistors on all the investigated boards (B1–B9) are presented.

It can be noticed that the weakest thermal coupling (the lowest value of the transient thermal impedance) is observed for the B1 board and the strongest—for the B6 board. The waveforms of Z_thm(t) start to grow for most boards after 20 s and for board B1—after 70 s. Comparing the measurement results of Z_th(t) and Z_thm(t), it is visible that the values of these parameters differ between each other even 10 times. That means that an increase in the junction temperature of the transistors is determined mostly by self-heating.

Figure 15 and Figure 16 show the measured values of R_th and R_thm for the tested PCBs.

Figure 15 shows that the difference between the thermal resistance values obtained for the tested cooling systems exceeds even 45%. In the case of the transistors operating without heat sinks, it is possible to reduce the thermal resistance of the transistor, compared with the system marked as B1, by up to 28%. Adding a copper field on the other side of the PCB (B2 PCB) lowers thermal resistance by 15%. The additional area of the cooper improves the efficiency of heat convection and makes it possible to reduce the value of thermal resistance. The introduction of thermal vias further improves the cooling efficiency of the transistor. The use of 75 vias outside the outline of the transistor’s solder pad (B6 board) was most beneficial. Such vias improve the heat transfer between both sides of the PCB, and therefore, the value of thermal resistance decreases. The number of vias and their diameter have no significant effect on the R_th value. The differences in the R_th values for PCBs B3, B4, B5, and B6 do not exceed 4%.

The efficiency of heat dissipation can be further increased by using the soldered heat sinks. The use of a copper wound heat-sink (B7 board) resulted in a 40% reduction in thermal resistance. The thermal resistance of the transistor on the B8 board, obtained using the same heat sink but without the soldering mask on the underside of the thermal pad, is slightly higher than the value obtained for the B7 board. This difference may be due to the accuracy of the measurements. The lowest value of thermal resistance R_th was obtained for the B9 board with a hot extruded heat sink. In this case, the value of this parameter was reduced by nearly 48% compared with the B1 board. The lower value of thermal resistance for the B9 board in comparison with the B7 board is a result of different values of the total surface of the heat-sinks. The heat-sink used in the B9 board has a much bigger surface than the heat-sink used in the B7 board. An increase in this area causes an increase in the efficiency of heat convection.

On the basis of the obtained results of measurements, the following analytical dependence of thermal resistance R_th on the area of the copper layer S and on the number of thermal vias n can be formulated.

$${\mathrm{R}}_{\mathrm{t}\mathrm{h}}={\mathrm{R}}_{\mathrm{t}\mathrm{h}0}+{\mathrm{R}}_{\mathrm{t}\mathrm{h}1}·\exp \left(-\mathrm{a}·\mathrm{S}\right)+{\mathrm{R}}_{\mathrm{t}\mathrm{h}2}·\exp \left(-\mathrm{b}·\mathrm{n}\right)$$

(6)

where R_th0, R_th1, R_th2, a and b are the model parameters.

The values of the transfer thermal resistance R_thm shown in Figure 16 are several times lower than the R_th values shown in Figure 15. The lowest R_thm values were obtained for the B1 board, which corresponds to the highest R_th value. Increasing the surface of the copper and introducing vias increases the R_thm value. Adding a heat-sink does not significantly affect the values of this parameter. An increase in the copper surface area on the printed circuit board causes an increase in the efficiency of the heat transfer between the transistors, which is manifested by an increase in R_thm.

On the basis of the obtained measurement results, the following empirical formula describing the dependence of R_thm on the parameters characterizing the layout of the PCB can be used:

$${\mathrm{R}}_{\mathrm{t}\mathrm{h}\mathrm{m}}={\mathrm{R}}_{\mathrm{t}\mathrm{h}\mathrm{m}0}·\left[1-{\mathrm{R}}_{\mathrm{t}\mathrm{h}\mathrm{m}1}·\exp \left(-{\mathrm{a}}_{\mathrm{m}}·\mathrm{S}\right)+{\mathrm{R}}_{\mathrm{t}\mathrm{h}\mathrm{m}2}·\exp \left(-{\mathrm{b}}_{\mathrm{m}}·\mathrm{n}\right)\right]$$

(7)

where R_thm0, R_thm1, R_thm2, a_m and b_m are the model parameters.

The measurements, the results of which are shown in Figure 15 and Figure 16, were carried out with the power dissipation in the tested transistors equal to 2 W. As is known, e.g., from the papers [14,16,17], the efficiency of heat dissipation from electronic components changes with a change in the temperature of these components or the power dissipated in them. Such dependences of R_th(p) and R_thm(p) for the fixed layout of the PCB can be described using the following formulas.

$${\mathrm{R}}_{\mathrm{t}\mathrm{h}}={\mathrm{R}}_{\mathrm{t}\mathrm{h}\min }+{\mathrm{R}}_{\mathrm{t}\mathrm{h}\mathrm{a}\mathrm{m}\mathrm{p}}·\exp \left(-\frac{\mathrm{p}}{{\mathrm{p}}_1}\right)$$

(8)

$${\mathrm{R}}_{\mathrm{t}\mathrm{h}}\mathrm{m}={\mathrm{R}}_{\mathrm{t}\mathrm{h}\mathrm{m}\min }+{\mathrm{R}}_{\mathrm{t}\mathrm{h}\mathrm{m}\mathrm{a}\mathrm{m}\mathrm{p}}·\exp \left(-\frac{\mathrm{p}}{{\mathrm{p}}_2}\right)$$

(9)

where R_thmin, R_thamp, R_thmmin, R_thmamp, p_1, and p₂ are the model parameters.

Figure 17 shows the measured dependences of R_th and R_thm on the power p dissipated in the active transistor (M_A) for the B1 board and Figure 18—for the B9 board. In these figures, points denote the results of the measurements, whereas lines—the results of the calculations performed using the Formulas (8) and (9). Blue is for R_th, and red is for R_thm.

As it can be noticed, in both the considered cases, the dependences of R_th(p) and R_thm(p) are monotonically decreasing functions. In the analyzed range of changes in the power, both the values of thermal resistance and mutual thermal resistance drop by about 10%. The observed character of the presented dependences shows that convection is the dominant mechanism in the process of heat dissipation from the transistors soldered to the tested boards.

Waveforms of Z_th(t) and Z_thm(t) are commonly approximated using the Formula (2). The dynamics of cooling are characterized, among the others, by the spectrum of the thermal time constants [39] appearing in the Formula (2). Such a spectrum for the waveforms of Z_th(t) from Figure 13 is presented in Figure 19, and for the waveforms of Z_th(t) from Figure 14—in Figure 20. In these figures the colors of lines correspond to particular boards denoted as B1–B9. The values of the spectral lines were estimated with the use of the algorithm from the paper [32].

In Figure 19, it can be noticed that for every board, there are time constants related to thermal capacitances and thermal resistances of the components of the heat flow path. The shortest of these thermal constants has a value of 1 ms and is related to the thermal properties of the semiconductor structure. The next thermal constant of the value of several tenths of the second is related to the thermal properties of the transistor package. The thermal time constants of the value of several seconds characterize the heat dissipation from the transistor leads and their soldering pads. The longest thermal time constants of the value of tens and hundreds of seconds characterize the heat dissipation from each of the sides of the PCB. In the considered conditions, the thermal properties of the PCB have a decisive impact on the overall ability of the considered boards to dissipate the heat generated in the transistors.

In the case shown in Figure 20, it is apparent that there are only 1–2 thermal time constants in the Z_thm(t) waveform. They are related primarily to the thermal parameters of the PCB, which makes the flow of the heat between the active and the passive transistor possible, as well as the dissipation of this heat to the ambient. The dominant thermal constant describing Z_thm(t) has the value of several hundred seconds.

The measurement results presented in Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, Figure 19 and Figure 20 were obtained in the conditions of natural convection. In the further part of the section, the results of the measurements acquired for two selected boards fixed to the heat exchanger of a cooling system Arctic [40] are presented. The measurements were carried out for boards B1 and B5 attached to the cooling system in a way shown in Figure 21.

In Figure 22, the waveforms of Z_th(t) and Z_thm(t) measured for the tested boards attached to the considered cooling system at the power dissipated in the active transistors equal to 2 W and 5 W are shown.

As can be noticed, the application of the cooling system Arctic allowed a significant reduction of the values of both the measured parameters in relation to the case of free convection. For board B1, the considered cooling system allows as much as a threefold (to 17 K/W) reduction of the Z_th(t) value. In turn, in the case of board B5 (R_th = 3 K/W), thanks to the application of thermal vias and the thermal pad on the bottom side of the board, a drop in the Z_th(t) value is thirteen-fold. The waveforms of Z_th(t) stabilize after several tens of seconds, which is much faster than in the case of cooling in the natural convection conditions. It is worth noticing that the effective transfer of the heat generated in the transistor on the top of the board to its bottom side is more important in the active cooling system than in the passive cooling system. This is a result of the more effective heat removal from the bottom side of the board.

The mutual transient thermal impedance Z_thm(t) of both boards is almost equal to zero. It results from the high efficiency of the heat transfer from the active transistor and maintaining practically constant temperature of the board. In such a situation, mutual thermal couplings between the transistors placed on the common board may be neglected.

Figure 23 illustrates the spectrum of the thermal time constants of waveforms Z_th(t) shown in Figure 22. (red corresponds to B1 board, blue—to B5 board)

For both the investigated boards, the thermal time constants of the value from single milliseconds to tens of seconds are present. For board B5, where the cooling pad is located on both sides of the board, the dominant thermal constant has even a ten times lower value. It means that the thermally stable state is achieved much faster.

6. Conclusions

In the paper, the results of the investigations illustrating the influence of the layout design of a PCB on the values of self and mutual transient thermal impedance of SMD power transistors are presented. The measurements were carried out using the indirect electrical method.

Based on the measurements, it was concluded that the layout design of a PCB significantly influences the values of the parameters characterizing the heat flow between the transistors placed on a common board and the ambient as well as between these transistors. For each layout design considered in the investigations, the measured values of thermal resistance were much lower than the value of the thermal resistance specified by its manufacturer for the case of the transistor without a cooling system.

It was shown that by changing the layout of the PCB only, it is possible to reduce the value of thermal resistance even by 34%. Additionally, the use of a soldered heat-sink makes it possible to reduce this parameter by an additional 20%. All the methods used for improving the efficiency of heat removal are based on increasing the area of metal from which the convection occurs. Additionally, thermal vias improve the efficiency of heat conduction between both sides of the PCB. An empirical dependence describing the influence of the dimensions and the number of the PCB layout components on R_th and R_thm was also proposed.

It was noticed that the mutual thermal resistance between the transistors increases when the thermal resistance of the active transistor decreases. It results from the fact that the heat flow through the thermal pads on the board causes better heat spreading and a reduction of the inequality of the temperature distribution on the board, as well as allowing a bigger area of the board to take part in the heat convection.

In the case of placing the investigated boards on the heat exchanger of the cooling system with forced convection, it was observed that a more considerable improvement of the cooling efficiency is achieved in the case when thermal pads and thermal vias are employed. In such a case, even a thirteen-fold reduction of the thermal resistance value can be achieved. The use of the considered cooling system also allows a significant reduction of the junction temperature stabilization time. At the same time, mutual thermal couplings become negligible because mutual thermal resistance is almost zero.

The presented investigation results can be useful for the designers of electronic circuits constructing devices assembled in the SMT process. Taking into consideration the presented results will enable optimization of a cooling system of such circuits, in particular semiconductor power devices. The optimization of the PCB layout is the most beneficial when the PCB cooperates with an effective active cooling system.