55 nm CMOS Mixed-Signal Neuromorphic Circuits for Constructing Energy-Efficient Reconfigurable SNNs

Abstract

The development of brain-inspired spiking neural networks (SNNs) has great potential for neuromorphic edge computing applications, while challenges remain in optimizing power-efficiency and silicon utilization. Neurons, synapses and spike-based learning algorithms form the fundamental information processing mechanism of SNNs. In an effort to achieve compact and biologically plausible SNNs while restricting power consumption, we propose a set of new neuromorphic building circuits, including an analog Leaky Integrate-and-Fire (LIF) neuron circuit, configurable synapse circuits and Spike Driven Synaptic Plasticity (SDSP) learning algorithm circuits. Specifically, we explore methods to minimize large leakage current and device mismatch effects, and optimize the design of these neuromorphic circuits to enable low-power operation. A reconfigurable mixed-signal SNN is proposed based on the building circuits, allowing flexible configuration of synapse weights and attributes, resulting in enhanced SNN functionality and reduced unnecessary power consumption. This SNN chip is fabricated using 55 nm CMOS technology, and test results indicate that the proposed circuits have the ability to closely mimic the behaviors of LIF neurons, synapses and SDSP mechanisms. By configuring synaptic arrays, we established varied connections between neurons in the SNN and demonstrated that this SNN chip can implement Pavlov’s dog associative learning and binary classification tasks, while dissipating less energy per spike of the order of Pico Joules per spike at a firing rate ranging from 30 Hz to 1 kHz. The proposed circuits can be used as building blocks for constructing large-scale SNNs in neuromorphic processors.

1. Introduction

Recently mimicking the human brain, neuromorphic hardware that processes information and performs a multitude of functions with low power consumption (~20 mW) and high parallel computing efficiency has emerged, with an increasing interest in its use in edge cloud computing for various applications such as environmental or health monitoring, as well as wearable devices [1,2,3]. Several neuromorphic chips based on spiking neural networks (SNNs) have been developed for Artificial Intelligence (AI) applications [4,5,6,7]. Unlike traditional artificial neural network (ANN) architectures, SNNs closely resemble real biological neural networks by using spike trains as signals for neuromorphic computation. In SNNs, information transmission is encoded based on the temporal relationship between spikes, which greatly improves parallel computing efficiency.

Brain-inspired SNNs are considered to have great potential to support low-power neural computing tasks [8,9,10]. In particular, SNNs have been demonstrated to be an effective algorithmic foundation for efficient processing of temporal signals [11,12]. The complex dynamical properties of these networks play a crucial role in reducing the memory resources necessary for processing, recognizing and classifying extended sequences of temporal data [13,14,15]. Figure 1a depicts a typical SNN comprising neuromorphic unit circuits for pattern recognition. Each input pattern pixel is represented as a random distribution spike train with its frequency proportional to the corresponding pixel value sent to the input layer neurons of the network. Pixel information is encoded by input layer neurons and is transmitted to the output layer composed of Leaky Integrate-and-Fire (LIF) neurons via synapses. As shown at the top of Figure 1b, an LIF neuron performs leaky integration of incoming spikes through input synapses, gradually accumulating them over time and firing spikes only when its membrane voltage reaches the threshold voltage V_TH, where V_TH denotes the threshold at which the LIF neuron reaches a firing spike. After spiking, the membrane potential of the LIF neuron resets to its resting state. The intelligent source of SNNs is that each synaptic weight can be modified through learning algorithms. Spike Driven Synaptic Plasticity (SDSP) is a biologically plausible learning rule optimized from the well- known Hebbian algorithm mechanism [16]. The weight pull-up process, complying with SDSP regulations, is illustrated in Figure 1b below. Under the control of UP or DN digital signals, the weight undergoes changes until a predetermined voltage threshold (V_thw) is reached, triggering a rapid transition to a stable value. The change in synaptic weight between previous and subsequent moments is indicated as ∆W. Specifically, UP and DN signals are generated by monitoring the firing frequency of postsynaptic neurons and the stimulation time of presynaptic neurons.

Thus, in SNNs’ architecture, signal processing occurs through the following three mechanisms: LIF neurons, synapses and SDSP learning algorithms. Since signal transmission relies on bio-electric impulses and voltage signals, it is presumed that analog/digital circuits are efficient means of implementing neuromorphic circuits [17,18]. Several mixed-signal SNNs have been proposed that include neurons, synapses and spike-based learning algorithms [19,20,21]. However, these circuits have complex structures and high-power consumption in these works. Therefore, designing compact and low-power neuromorphic circuits is crucial for implementing large-scale spiking neural networks. The transistor ratio is crucial for compact and energy-efficient neuromorphic circuits design. The mathematical models of LIF neurons, synapses, and the SDSP learning algorithm dictate the circuit structure and design goals. To balance the charging and discharging speed of the membrane capacitor and minimize leakage current in the design of LIF neuron circuits, it is necessary to increase the transistor ratio of the critical charging branch. The positive feedback charging branch of LIF neurons usually maintains a transistor ratio of more than 6:1, even in larger transistor sizes [19,21]. To meet the mathematical model’s requirements for LIF neurons with exponential dynamic characteristics, all transistors in DPI circuits used to collect synaptic current pulses must maintain the same proportion [18,19,20]. In the design of synaptic circuits, to ensure the adjustability and matching of synaptic time constants, increasing the ratio of transistors controlling synaptic time constants is needed to ensure a wide dynamic synaptic time constant [20,21]. For the design of the SDSP learning algorithm circuit, the transistor ratio of the amplifier needs to be adjusted based on the specific comparison threshold to achieve a more accurate gain.

In this paper, we present a set of mixed-signal neuromorphic circuits that were designed to implement energy-efficient and space-efficient SNNs using 55 nm CMOS technology. In Section 2, we discuss the design strategy for a low-energy analog LIF neuron circuit and illustrate the biophysical complexity of its neural dynamics. A configurable synapse circuit coupled with an optimal SDSP learning algorithm circuit to modify weights is designed. Specifically, the SDSP circuit is capable of precisely regulating synaptic weights to binary states of either 0 or 1 using a bi-stable transconductance amplifier. Moreover, we construct a reconfigurable mixed-signal SNN utilizing the proposed circuits, which allows initial synaptic weights and synaptic attributes to be configured using basic digital circuits. Section 3 shows the test results of the SNN chip fabricated using the 55 nm CMOS process and concludes this summary in Section 4.

2. Proposed Neuromorphic Circuits and SNN Implementation

In this section, we propose the design of an analog LIF neuron circuit, synaptic circuits and SDSP learning algorithm circuits. We analyze and formulate the advantages of these design methods, and demonstrate biologically plausible dynamic behaviors of these circuits. To build a reconfigurable mixed-signal SNN using these neuromorphic circuits, we employ asynchronous digital circuits to assign routing for synaptic arrays.

2.1. Analog LIF Neuron

The LIF neuron model has gained popularity as it is thought to capture many properties of biological neurons, while requiring fewer and less complex differential equations compared to more complex conductance-based models such as Mihalas–Niebur and Izhikevich [22,23]. LIF neurons’ computational efficiency and compact size make them valuable choices for constructing large-scale neuromorphic processors [24,25]. However, previously, LIF neurons required a significant amount of bias voltages or currents to configure circuit properties and resulted in large footprints and high energy consumption. The voltage amplifier and the tau-cell LIF neurons presented in [24,25] are considered to be efficient embodiments of biological neurons; however, their power consumption may not be as low as possible. The differential pair integrator (DPI) and low-pass filter (LPF) LIF neurons are not regarded as compact cases in previous studies [26,27]. Time-domain LIF neuron circuits feature intricate structures, including the integration of digital logic circuits that serve as spike generators [28,29]. This increases the circuit area cost and design complexity, while also resulting in higher dynamic circuit power consumption.

We propose an analog LIF neuron circuit. The purpose of proposing this neuron is to provide a low energy and compact structure utilizing highly efficient analog circuits. Figure 2 shows the neuron circuit structure. To ensure biologically plausible dynamics of neurons and synapses in SNN hardware design [30], a DPI circuit was used as an input current integrator to the neuron. Specifically, the DPI circuit avoids transistors with bulk source connections and is unaffected by any mismatches between its current sources, resulting in a smaller silicon area and lower power consumption. Therefore, it provides a compact and low-power solution. Unlike LIF neuron circuits that use transconductance amplifiers that are sensitive to supply variations [31,32], our design employs a current-based positive feedback amplifier to control spike generation. This helps to limit the input voltage swing and reduce sensitivity to supply variations, while also decreasing dynamic power consumption of the neuron circuit.

As seen, the neuron comprises an input DPI circuit (M_L1–3) used as an LPF, which models the leakage conductance of the neuron; a Na+ block (M_N1–7) models the neuron’s Sodium (Na+) activation and inactivation channels and includes an amplifier that generates spike events with positive feedback based on current; a K+ block forms two first-order low-pass filters to model the effect of potassium conductance, resets the neuron and implements a refractory period functionality (M_K1–4); a AHP module (M_A1–2) in K+ models the Calcium-dependent after-hyperpolarization Potassium currents observed in neurons, producing the spike-frequency adaptation mechanism. The above simplest highly efficient analog circuitry approaches lead to a low-energy biologically plausible neuron.

The DPI circuit functions as a low-pass filter, generating exponential dynamics in response to input currents that integrate into the membrane capacitance C_mem. The filter gain can be adjusted by V_thr. Transistor M_L3 acts as a fixed leakage transconductance for this neuron that satisfies biologically plausible time constants, and leakage current I_leak can be controlled by bias voltage V_leak. Integrating more input current into C_mem leads to an increase in membrane voltage V_mem. The V_mem rises to a certain threshold; the current-based amplifier (M_N1–3) is activated and generates a positive feedback current I_pf to rapidly charge the C_mem. The voltage at node V_o1 then decreases significantly and a pulse is generated by the inverter M_N4–6. With each spike, the capacitor C_ref is charged step by step through the transistor M_K3 and the membrane voltage V_mem is reset to the resting potential as long as the voltage V_u is high enough to turn on transistor M_K1–2. This effectively establishes the refractory period function of the neuron. Moreover, the leakage current I_ref is progressively decreased as the capacitor C_ref is charged, resulting in a longer refractory period and a lower firing frequency. The bias voltage V_ref is also used to adjust the duration of the refractory period. However, the capacitor C_ref is slowly discharged through the leakage path M_A1–2 (representing the calcium transconductance after-hyperpolarization current I_adp [21]), ultimately maintaining a stable value for the current I_ref, which also keeps the voltage V_u at a dynamically stable value. Consequently, the firing frequency of the neuron reaches a stable point and has a lower value than its initial frequency. This process effectively implements the frequency adaptation mechanism. Based on the above analysis, it is evident that the circuit operates by consuming power only during spike generation, minimizing power loss during idle periods.

The computational mode of the LIF neuron is derived from the adaptive neuron described in [33] as two coupled differential equations that follow.

$$C\frac{dV}{dt}=-G_{lk}(V-R_L)+G_{lk}{\mathrm{\Delta }}_T\cdot e^{\frac{V-V_{TH}}{{\mathrm{\Delta }}_T}}-h+I$$

(1)

$${\tau }_h\frac{dh}{dt}=w(V-G_{lk})-h$$

(2)

where C is the membrane capacitance, V is the membrane potential, G_lk is the leakage conductance, R_L is the resting potential, I is the input current (i.e., synaptic current) and h is the after-hyperpolarization adaptation current. The term ∆_T represents the threshold slope factor, V_TH represents the activate threshold potential of the neuron, w is the adaptation threshold and τ_h is the adaptation time constant.

The current of the charge–discharge branch of the membrane capacitance serves as the control variable of the neuron circuit. Hence, the currents I_mem and I_ahp correspond to the V and h variables of the computational model described in Equations (1) and (2), respectively. By applying Kirchhoff’s current law on the membrane potential node V_mem, the circuit’s behavior can be determined as

$$C_{mem}\frac{d}{dt}{V}_{mem}=I_{M_{L2}}-I_{leak}-I_{ahp}+I_{pf}$$

(3)

The gain of the DPI circuit can be adjusted precisely with the bias voltage V_thr. Adopting the trans-linear principle to the DPI circuit, as referenced in [30], we employ uniform transistor parameters and use ultra-low leakage currents where I_leak ≪ I_in, and the circuit’s dynamics can be expressed as

$$C_{mem}\frac{d}{dt}{I}_{mem}=-I_{leak}{I}_{mem}+\frac{I_{mem}{I}_{pf}}{I_{leak}}+I_{leak}(I_{in}-I_{ahp})$$

(4)

$$\frac{C_{adp}}{I_{adp}}\frac{d}{dt}{I}_{ahp}=I_{ahp}-I_{adp}$$

(5)

where $I_{mem}{I}_{pf}/I_{leak}$ is a positive feedback current contributed by the DPI block and the Na+ block, which can be approximated as an exponential function of I_mem; I_adp is the slow variable as the adaptation coefficient responsible for spike-frequency adaptation mechanisms. Therefore, the circuit depicted in Figure 2 and described by Equations (4) and (5) represents a generalized conductance-based LIF neuron model, which takes the form of an adaptive exponential LIF neuron model, as detailed in [33].

2.2. Configurable Synapse and SDSP Learning Algorithm

The synaptic transmission converts presynaptic voltage pulse signals into postsynaptic currents that are injected into the target neuron’s membrane with a strength governed by synaptic weight. Synaptic weight translates fast presynaptic pulses into long-lasting postsynaptic currents with intricate temporal dynamics, while theoretically simplifying this process with linear exponential temporal characteristics [34]. In Very Large-Scale Integration (VLSI) SNN architectures, a single postsynaptic neuron circuit integrates currents from multiple synapses. The postsynaptic neuron performs a weighted sum of input signals, resulting in postsynaptic potentials that rise with stronger excitatory synapse activity and fall with stronger inhibitory activity. As such, one of the primary requisites for synaptic circuits is compactness to ensure maximum integration of synapses on the chip, using minimal silicon area. However, implementing synaptic integrator circuits with linear response characteristics and time constants comparable to the time constant of the neuron’s membrane potential may demand significant silicon real estate. Therefore, designing compact linear synaptic circuits that model the functional properties of biological synapses remains a challenging task that continues to be actively pursued.

Various synaptic circuit designs have been proposed, with different trade-offs between functionality, complexity of temporal dynamics and circuit/layout size [34,35,36]. Some proposed circuits utilize floating-gate devices or limit the dynamic range of the signal to mimic the biophysical characteristics of synaptic channels [37,38]. Here we propose synaptic circuit features with a wide and linear exponential dynamic range. Figure 3 illustrates a schematic of the synaptic circuit. To meet SNN requirements with a compact design, excitatory and inhibitory synapses are integrated together. This design provides attribute configuration as a novel feature for synaptic circuits and has a smaller circuit area compared to the State-of-the-Art designs that use oscillator-based transconductance synaptic circuits [39].

The excitatory (M_6–7) and inhibitory (M_9–10) synapses are voltage-controlled current sources that are activated by a presynaptic pulse (Pre_spk) and weight (V_w). The attributes of the synapses can be configured according to actual needs through the digital signal Conf to control transistors M₅ and M₈. Transistor M₁ acts as a constant current source to the linearly charged capacitor C_syn, while M₆ generates an excitatory current exponentially dependent on the V_syn node and M₇ adjusts the magnitude of the excitatory current via bias voltage V_exc. Transistors M_9–10 generate inhibitory synaptic exponential current to discharge neurons’ membrane potentials. Taking the excitatory synapse as an example, based on the linear transmission principle, the synapse obeys the following dynamics:

$$\frac{C_{syn}}{I_{\tau }}\frac{d{I}_{syn}}{dt}+I_{syn}=\frac{I_w}{I_{\tau }}$$

(6)

where I_syn is the synapse output current; I_τ and I_w is a current set by V_τ and V_w, respectively. The synapse time constant can be controlled by capacitor C_syn and current I_τ. To increase the time constant of the circuit, it is necessary to increase the size of capacitors or decrease the I_τ current. To avoid the large area requirements brought about by increasing capacitor sizes in the 55 nm technology, we adjust the W/L ratio of M₁ to achieve an optimal exponential current time constant for LIF neurons.

A primary feature of biological synapses is their ability to display various forms of plasticity. Plasticity mechanisms induce enduring modifications in the synaptic efficiency of single synapses, enabling the storage and learning of input stimulus statistics. Plasticity mechanisms that increase synaptic weights are termed as long-term potentiation (LTP) mechanisms, while those that decrease synaptic weights are termed as long-term depression (LTD) mechanisms [40]. To realize the mechanism of synaptic plasticity, many spike-based models of synaptic plasticity learning algorithms are proposed, such as Spike-Timing Dependent Plasticity (STDP), Spike-Driven Synaptic Plasticity (SDSP), etc. Several STDP models have been proposed in computational neuroscience for classifying spatio-temporal spike patterns [41,42]. However, emerging evidence indicates that spike-timing-based learning algorithms alone are insufficient to explain all the phenomena observed in neurophysiological experiments [43]. These algorithms also exhibit poor memory retention performance and necessitate supplementary mechanisms to grasp spike-time correlations and input pattern mean firing rates [44]. For these reasons, we opted for implementing the spike-driven synaptic plasticity mechanism proposed by [16], as it has demonstrated the ability to mimic various biological phenomena and exhibits performance features that match those of the latest machine learning techniques [16,41,42]. This algorithm updates synaptic weights not only based on spike-timing, but also considers the timing of presynaptic spikes, the current state of membrane potential of the post-synaptic neuron and its recent spiking history behavior. The schematic of the proposed revised analog/digital SDSP learning algorithm circuits is shown in Figure 4. Figure 4a is a component of the SDSP circuit used to update weights through control signals received from the submodule, as depicted in Figure 4b.

In Figure 4a, M_H1–H6 comprise a spike-triggered weight update block. When spikes from presynaptic neurons are received, it increases or decreases synaptic weight V_w depending on the digital signals UP and DN generated downstream by the postsynaptic neuron. Up and down jumps height of weight can be adjusted by changing the V_u and V_d signals. A bi-stability weight refresh circuit comprised of M_B1–B11 is a wide-range positive-feedback transconductance amplifier with a low slew rate that continuously compares the V_w node with the threshold voltage V_thw. If V_w > V_thw, the amplifier slowly drives the V_w node toward the positive rail; otherwise, it actively drives it toward the ground. The drift rates to high and low states can be tuned with bias voltage W_U and W_D, respectively. The bi-stable property effectively implements the LIP and LTD mechanisms’ process for weight updates and eliminates the problematic requirement of storing precise analog variables for synapses at long time scales. In addition, the INIT block M_W1–4 can be used to set the initial state of the synapse weight: when the write (PW) signal stays high, the weight V_w is shorted to V_dd or toward the ground according to bit b2.

Figure 4b shows the postsynaptic learning control circuits of the SDSP learning algorithm for evaluating weight updates and “stop-learning” conditions. The spikes from the postsynaptic neuron are integrated by M_C1–C3 into the capacitor C_Ca, generating a voltage V_Ca that reflects postsynaptic calcium concentration and serves as an indicator of recent spiking activity of the neuron, and compares this voltage V_Ca to three threshold voltages K_up, K_mid and K_dw. In parallel, the membrane potential V_mem(t_post) of the neuron is compared to a set threshold θ_mem using a voltage comparator. The comparison results determine UP and DN, such that synapse weights are adjusted whenever a presynaptic spike Pre_spk reaches the weight update module shown in Figure 4a.

The weight update and stop-learning rule can be governed by the following equations, assuming the arrival of each presynaptic spike:

$$\left\{\begin{array}{l}{V}_w=V_w+\mathrm{\Delta }{w}^{+}\mathrm{if}{V}_{mem}(t_{post})>{\theta }_{mem}\mathrm{and}{K}_{dw}<V_{Ca}<K_{up}\\ V_w=V_w-\mathrm{\Delta }{w}^{-}\mathrm{if}{V}_{mem}(t_{post})<{\theta }_{mem}\mathrm{and}{K}_{dw}<V_{Ca}<K_{mid}\end{array}\right.$$

(7)

where the factor ∆w⁺ and ∆w⁻ determine the amplitude of the weight V_w increases and decreases; V_mem(t_post) represents the membrane potential of the postsynaptic neuron when have presynaptic spike arrives; θ_mem is a set thresholds for determining whether the weight should be adjusted up or down; and the thresholds K_up, K_mid and K_dw determine the conditions under which weights can be increased, decreased, or not updated. If none of the above equation conditions are met, ∆w⁺ and ∆w⁻ are nullified by setting UP to V_dd and DN to 0. This stop-learning mechanism significantly enhances the system’s ability to generalize by preventing overfitting once the input pattern has been learned [16,19,21].

Alongside the immediate weight updates, the weight V_w is continuously drawn toward one of two stable states as mentioned in Figure 4a, determined by if it is below or above a predetermined threshold V_thw as follows:

$$\left\{\begin{array}{l}\frac{d}{dt}{V}_w=\mathrm{\Delta }{J}^{+}\mathrm{if}{V}_w>V_{thw}\mathrm{and}{V}_w<W_{max}\\ \frac{d}{dt}{V}_w=\mathrm{\Delta }{J}^{-}\mathrm{if}{V}_w<V_{thw}\mathrm{and}{V}_w<W_{min}\end{array}\right.$$

(8)

where ∆J⁺ and ∆J⁻ represent the weight drive rates towards its upper and lower bounds, respectively, while W_max and W_min represent the upper (i.e., V_dd) and lower bound (i.e., ground), respectively.

As already mentioned, the synapse can be configured with specific characteristics using basic digital circuit combinations. The schematic of the synapse configuration element is shown in Figure 5.

It consists of a signal flip-flop to store the configuration bit b1, a three-state buffer for reading out the synaptic state and four logic gates for combining the incoming digital signals. The signals X_conf and Y_conf are derived from a horizontal and vertical configuration decoder, respectively, to select the synapse that needs to be configured. Bit b1 can be used to configure the synapse contact as either excitatory or inhibitory by setting the value of the digital line Conf. Setting Conf to 0 enables the excitatory branch, while setting it to 1 enables the inhibitory branch of the synapse depicted in Figure 3. CLK clock signal is essential to ensure reliable data transmission of bit b1 and it also plays a crucial role in generating write signals PW and nPW to activate the INIT circuit that sets the initial state of the synapse according to bit b2 (see Figure 4a). In an SNN, the two bits b1 and b2, along with CLK signals, can be broadcasted to all synapses, and the selection lines X_conf and Y_conf enable one synapse at a time. The three-state buffer’s input is connected to the V_w_state line and drives a digital output pin to readout the real-time digital state of synapse weights, which is beneficial for monitoring the status of SNNs during training. The configurability of the synapse is an innovative feature for constructing reconfigurable SNNs.

2.3. Reconfigurable SNN Implementation

Once the basic neuromorphic unit circuits including the compact energy-efficient neuron were built, we configure exponential feature synapse and highly biomimetic SDSP with the stop-learning function. We constructed a reconfigurable mixed-signal SNN based on these neuromorphic unit circuits. The structural diagram of the SNN is shown in Figure 6a. It comprises four presynaptic neurons as the input layer, two postsynaptic neurons as the output layer and two teacher neurons as the supervisory signals for weight updates. Each neuron in the input layer has a synapse to receive and transmit external stimulus signals. The presynaptic and postsynaptic neurons are fully connected by eight synapses, including eight SDSP weight learning algorithm circuits. In addition, the output layer of the SNN employs a Winner Take All (WTA) connection rule to create competitive interactions among the output neurons, where neurons with first firings suppress all other neurons to win the competition. Competition renders the output of a single neuron reliant on the collective activity of all neurons in the SNN, rather than just its own input. The synapse matrix can be flexibly configured through configurable elements, and each synapse weight is routed to the weight output bus via a three-state gate to read the SNN’s real-time digital weight status updates.

The SNN is fabricated using the 55 nm CMOS process; the chip micrograph is shown in Figure 6b. The chip has an area of 0.9 × 1.1 mm², with each neuron occupying 264 µm² and the learning control circuits occupying 300 µm². The synapse and weight updating circuits are integrated and cover an area of 514 µm². The chip also includes two 2–4 decoders and other digital logic gate circuits as peripheral signal transmission interfaces.

3. Chip Measurement Results

The chip measurement setup is shown in Figure 6c. The measurement system consists of a Xilinx Artix-7 AX7035 FPGA board that receives command packets via a USB interface and a PCB test substrate with the chip installed onto it via LQFP sockets. The core circuit of this chip operates at a power supply of 1.2 V, while the PAD requires a power supply of 1.8 V. The LIF neurons, plastic synapses and SDSP learning algorithm circuits in the SNN are controlled by externally biased voltage signals. Input and teacher neurons receive external digital spike sequences as stimulation signals, transmitted via plastic synapses to stimulate the output neurons for results. The configuration unit and peripheral communication module receive external digital signals to configure the network. SNN’s output signals consist of four analog and five digital signals. All analog bias voltages in the test are generated with resistive dividers, and all digital input stimulus signals are produced with the FPGA and loaded into the chip. The digital signal outputs are acquired utilizing the FPGA’s Integrated Logic Analyzer (ILA core) and observed as a waveform on the Vivado GUI through a downloader that implements JTAG interface to the USB interface data conversion, while the analog signal outputs are captured using a digital oscilloscope with a sampling rate of 5 GHz.

3.1. LIF Neuron Behavior Testing

To show the dynamic behaviors of neurons through the combination of synaptic circuits, we stimulate a chosen neuron in the SNN through excitatory synapses, while sweeping different bias parameters for the neuron. Figure 7 shows the test results of the neuronal refractory period and the frequency adaptation mechanism.

At the top of Figure 8, the membrane potential (V_mem) variation of the neuron during stimulation of an excitatory synapse with a presynaptic input spike train average frequency of 500 Hz is shown. Adjusting the bias voltage V_ref in the K+ block of Figure 2 can achieve different refractory periods. Larger voltage V_ref results in a longer refractory period for the neuron. Due to the voltage V_u remaining at a sufficiently high level, there is enough leakage current I_ahp to discharge the neuronal membrane potential to its resting state without being affected by input stimulation. Modifying the refractory period of neurons allows for wide-ranging frequency modulation and shows great potential for larger spiking neural network systems [18,19,20,21]. The bottom of Figure 8 shows the spike-frequency adaptation behavior obtained by appropriately tuning the voltage parameters in the AHP block of Figure 2, while stimulating the neuron by a synapse applies a constant step voltage and is shown as the pink trace at the bottom. As seen, the neuron is initially firing at a high rate and gradually reaches stability at a lower rate compared to the initial firing. This adaptive frequency process reduces the firing rate to conserve energy for neurons.

The variation in input intensity impacts neuronal firing rates. We recorded the firing response of a neuron to varying intensities of an input excitation, ranging from 50 Hz to 2 kHz, as depicted in Figure 8. For weaker stimuli, such as below 100 Hz, it is difficult for neurons to generate responses due to the inability to reach the firing threshold. This is a manifestation of the intrinsically conditioned response of the neuron. As the intensity of the input stimuli increases, the firing rate of the neuron gradually increases and then reaches saturation at approximately 1 kHz. As a result, the proposed neuron exhibits a wide firing output (ranging from about 30 Hz to 1 kHz), ensuring its compatibility with large-scale SNNs such as [14,18,19,20,21] those that share similar firing rates. The proposed neuron operating at the 30 Hz–1 kHz frequency range is sufficient for real-time SNN applications for natural signals such as speech, human characteristics, biological signals, and various environmental signals that typically have time constants ranging from milliseconds to seconds in SNN processing [19,20,21].

3.2. SDSP Learning Algorithm Testing

In this section, we present the SNN measurements that implement the SDSP learning mechanism described in Section 2.2. We choose a presynaptic and postsynaptic neuron, along with their connecting synapses and SDSP circuits, as a complete signal flow. We generate Poisson-based spike trains for presynaptic input stimulation, while the postsynaptic neuron is driven by a teacher neuron acting as a teacher signal in a supervised learning condition. The teacher neuron is stimulated by Poisson-based spike trains generated with FPGA. The Poisson nature of the spike trains used in this way is essential for implementing stochastic learning by providing the necessary variability [45, 46].

Figure 9 shows the experimental results of stochastic learning that highlight the operational features of both synapse and neuron learning circuits. The bottom trace represents presynaptic input spikes (500 Hz Poisson spike trains); the second trace from the bottom represents bi-stable weight updates (node V_w in Figure 4a); the third trace represents the membrane potential of the postsynaptic neuron; and the upper two traces represent digital control signals (UP and DN) that determine whether to increase, decrease or maintain V_w at its current value. Weight updates occur when the arrival of presynaptic spikes and the calcium concentration of the postsynaptic neuron is within the appropriate range, as discussed in Section 2.3 on postsynaptic learning control circuits. Based on the calcium concentration signal, the digital UP (active low) and DN (active high) signals turn on or off to enable the weight update mechanism. The weight is adjusted to increase or decrease depending on the postsynaptic membrane potential relative to the membrane threshold (refer to highlighted weight updates at t = 1.74 s and t = 1.97 s). The weight is slowly driven toward the low or high stable states, determined by whether it falls below or above the weight threshold V_thw.

3.3. Pavlov Associative Learning Experiment and Binary Classification Task Testing

The above experiments demonstrate the biological similarities between the behaviors of the neuron and the properties of the SDSP learning circuits implemented in the SNN chip. To validate the applicability of this reconfigurable SNN in specific tasks, we conducted both associative learning experiments and classification task experiments, respectively. In the associative learning experiment (known as Pavlov’s dog [47]), we select two input layer neurons for the sensory decision and one output layer neuron for the association decision. The results of the associative learning experiment are shown in Figure 10.

As seen, the time from 0 to 0.6 s represents the initial configuration period of the network prior to experimentation. X0 and X1 are outputs from the row decoder that select the desired synapses in the network as configurations, while CLK, b1 and b2 are configuration signals used to set the attribute and initial weights of the selected synapses (see Section 2.3 for details). Here, the chosen synapses were configured as excitatory through b1. The initial weight of the synapse connected to sensory neuron 2 was set to high by b2 at 0.1–0.3 s, while the synapse connected to sensory neuron 3 was set to low by b2 at 0.3–0.5 s. For sensory neurons 2 and 3, there is the same input stimulus as for the Poisson spike trains at 300 Hz. Before learning, the “salivation” neuron only responded to stimuli from the “Sight of Food” neuron 2. By co-stimulating “Sight of Food” neuron 2 and “Sound of Bell” neuron 3, the synapse between neuron 3 and the decision neuron was potentiated with the SDSP learning algorithm. After learning, when the stimulus from the “Sound of Bell” neuron 3 was used alone, the “salivation” neuron was excited and responded to neuron 3, thus establishing an association between the conditioned (“Sight of Food” neuron 2) and unconditioned (“Sound of bell” neuron 3) stimuli. The weight variation of associative learning was monitored in real-time and recorded as the W_State signal.

Associative learning is crucial in understanding how the brain connects events and for enhancing the effectiveness of neural networks in certain tasks. The successful implementation of associative learning highlights the SNN chip’s proficiency in performing intricate learning tasks. Figure 11 shows the results of a binary classification task experiment.

In this classification experiment, two patterns (pattern 1 and pattern 2) consisting of distinct pixels are loaded onto the network, where black pixels represent the stimulation from a 200 Hz Poisson spike train, while white pixels represent no stimulation. Input layers of neurons 1 and 3 correlate to pixels 1 and 3, while neurons 2 and 4 correlate to pixels 2 and 4. Output layer neurons 1 and 2 represent the spike outputs of patterns 1 and 2, respectively. During the initial configuration period of 0–0.9 s the synapse connecting the input neuron 1 and output neuron 2 is configured as inhibitory with b1 at 0.2–0.3 s; similarly, the synapse connecting input neuron 4 and output neuron 1 is configured as inhibitory with b1 at 0.7–0.8 s, while all other synapses are configured as excitatory with b1 (high level); the initial weights of all synapses is set to 0 via b2.

Firstly, pattern 1 is inputted to the network and the output neuron 1 has no response. With the guidance of teacher neuron 1 (a 300 Hz Poisson spike train) and co-stimulation of pattern 1, connections are established between input neurons 1 and 3 with output neuron 1, resulting in a response to pattern 1. This also means that the weights V_w11 and V_w13 (see Figure 6a) are updated from low to high with the SDSP learning algorithm, as can be seen from the weight output signal W_State at 2.0–2.1 s for V_w11 and 2.4–2.5 s for V_w13. Establishing a connection between pattern 2 and output neuron 2 follows the same process as pattern 1. The weights V_w22 and V_w24 (see Figure 6a) are updated from low to high with the SDSP learning algorithm, as can be seen from the weight output signal W_State at 2.3–2.4 s for V_w22 and 2.7–2.8 s for V_w24. After establishing connections between two patterns and output neurons, when the stimulus from pattern 1 was used alone, output neuron 1 was excited and responded to pattern 1. Conversely, while the stimulus from pattern 2 was used alone, output neuron 2 was excited and responded to pattern 2, and the binary classification task was effectively performed using the SNN chip. Integrating multiple SNN chips together enables networks to handle complex application tasks, as demonstrated in previous studies [20,21,48,49,50].

In this design, the indicator for evaluating the classification accuracy of SNNs in binary classification tasks is the change in synaptic weight after SNN training. After training with the standard binary task, the weight distribution of the 4 × 2 synaptic arrays in SNNs is as follows: the synaptic weights between the pre- and post-neurons corresponding to black pixels are at a high level, while the synaptic weights between the pre- and post-neurons corresponding to white pixels are at a low level. To evaluate the classification accuracy of SNNs in binary classification tasks, we applied varying degrees of noise to two patterns (i.e., white pixels were subjected to lower frequency Poisson spike trains, ranging from 10 Hz to 50 Hz), and the two patterns were divided into 5 groups for a 10-training epoch. After each epoch, the weight changes of 4 × 2 synaptic arrays in the network are counted and compared with the standard synaptic weights. After training, the accuracy of the binary classification network can be evaluated by determining the proportion of synaptic weights in the network that are the same as the standard synaptic weights. Figure 12 presents the binary classification accuracy versus training epoch statistics for the SNN, comparing simulation and testing results.

During the initial stage (1–4), the SNN began to learn the two noise patterns, resulting in a relatively low accuracy due to the significant difference between the trained weights and standard weights. In the middle stage (4–8), as the SNN continues to associate and learn, the network gradually adjusts the weight matrix toward the standard weight via inhibitory synapses, leading to an increase in accuracy. In the later stage (8–10), the SNN further learns to associate the two noise patterns and inhibits most of the synaptic weight differences caused by the noise signals, resulting in a stabilized accuracy. Through testing, the SNN achieves an accuracy of approximately 91.4% in recognizing the two noise patterns, while the simulation accuracy reaches 92.8%. However, a possible reason for the deviation between the testing and simulation accuracy could be the weighting testing error caused by the noise and leakage current in the testing substrate.

3.4. Energy per Spike

To evaluate the energy efficiency of the SNN, the energy consumption per spike is a critical figure of merit (FoM) [21,24]. In the binary classification experiment, we measure the firing frequency of single neurons and calculate the energy per spike relative to the firing rate. The energy per spike equals

$$\frac{Energy}{Freq\cdot Time}=\frac{P_{ave}\cdot Time}{Freq\cdot Time}=\frac{P_{ave}}{Freq}$$

(9)

where Energy is the product of average power consumption (P_ave) and excitation time (Time) that is represented as (P_ave·Time), and Freq is the spiking frequency. Figure 13 illustrates that the energy per spike declines from hundreds of pJ for lower frequencies to tens of pJ for higher frequencies (as reference at 92.6 pJ@300 Hz). This occurs as inverters operate at higher levels of gain in the lower frequency range, owing this to a slower charging of the membrane voltage V_mem input when compared to higher frequency operation.

Table 1. Features of proposed circuits in comparison with other works.

Work	[48]	[52]	[51]	This Work
Technology	180 nm CMOS	55 nm CMOS	28 nm CMOS	55 nm CMOS
Supply voltage	1.8 V	1 V	0.7–1.0 V	1.2 V
Area of neuron	1188 μm2	482 μm2	64.6 μm2	264 μm2
Area of synapse	128.4 μm2	-	13 μm2	54 μm2
Frequency	30 Hz–1 kHz	-	10 Hz–350 Hz	30 Hz–1 kHz
Energy per spike	883 pJ@30 Hz	1.099 nJ@10 Hz	2.3 nJ@10 Hz 30 nJ@350 Hz	18.4 pJ@30 Hz 483 pJ@1 kHz

compares the features of our designed circuit with other configurable circuits applied to neuromorphic systems [48,51] and circuits with the same process [52]. Compared to a 180 nm circuit design [48], our design exhibits superior energy efficiency with 483 pJ@30 Hz (refer to Figure 13) than the reference design 883 pJ@30 Hz, while also occupying a smaller circuit area. Moreover, the circuits used in [52] and our work have the same process, and it can be noted that our design offers significant advantages in both the area and power consumption. Compared to a more advanced 28 nm switched capacitor design [51], our design has a power efficiency that is approximately lower than two orders of magnitude. However, to achieve more complex biomimetic dynamic behaviors, our design requires a larger capacitance and transistor size, resulting in a larger circuit area relative to [51].

4. Conclusions

In this paper, we present a set of digital/analog neuromorphic circuits and implement a reconfigurable mixed-signal SNN fabricated with 55 nm technology. By measuring this SNN chip, the analog neuron can achieve stable refractory period adjustable behavior and a spike-frequency adaptive mechanism, and exhibits a wide firing rate ranging from about 30 Hz to 1 kHz. Synapses are equipped with digital configurable elements that enable excitation and inhibition configuration, as well as initial weights settings. The SDSP learning algorithm circuits employ a transconductance amplifier to achieve a stable binary weight output. We perform Pavlov’s dog association learning experiment and binary classification tasks by configuring synaptic arrays of the SNN chip. Compared to other configurable neuromorphic circuit designs with a mixed-signal, our proposed designs are more cost-effective and energy-efficient. Therefore, the proposed circuits can be used as building blocks for constructing large-scale SNNs in neuromorphic processors to efficiently handle complex application tasks.