A Wideband and Low Reference Spur PLL with Clock Feedthrough Suppressed and Low Current Mismatch Charge Pump and Symmetrical CML Divider

Abstract

This paper presents the design and performance analysis of a wideband charge-pump phase-locked loop (CPPLL) characterized by low reference spur and low phase noise. The proposed CPPLL, operating as a wideband phase-locked loop (PLL) with a reference frequency of 100 MHz, achieves a wide tuning range of 40% from 2.0 GHz to 3.0 GHz. A clock feedthrough suppressed charge pump with additional bias current branches is used to reduce the PLL’s loop reference spur. The 4-stage current mode logic (CML) divide-by-2/3 circuit is utilized in the frequency divider to achieve high-speed frequency division. The circuit of an AND gate and latch in the 2/3 divider adopts a full differential symmetric structure to minimize the phase error of high-frequency differential signals. The voltage-controlled oscillator (VCO) is designed to provide a wide tuning range while optimizing the trade-off between the phase noise and power consumption. The fabricated PLL is implemented using a 0.13 µm CMOS process. Experimental measurements reveal a reference spur of −74.39 dBc at an oscillation frequency of 2.4 GHz. Moreover, the CPPLL achieves phase noise of −102.55 dBc/Hz@100 kHz and −127.15 dBc/Hz@1 MHz, while consuming 33.6 mW under a 1.2 V supply voltage. The integrated root-mean-square (rms) jitter, measured from 10 kHz to 10 MHz, is 340.99 fs, and the figure-of-merit (FoM) is −234.08 dB at a carrier frequency of 2.4 GHz, highlighting the potential of the proposed PLL for integrated circuit applications.

1. Introduction

The phase-locked loop (PLL) is a ubiquitous component in wireless communication systems. It is responsible for generating the desired frequency signal for frequency down-conversion and up-conversion. With the increasing demand for high-speed and wideband communication systems, the design of PLLs with improved performance metrics has become crucial.

The performance concerning the reference spur is crucial for PLLs, as an inadequate reference spur can result in significant inter-channel crosstalk. Previous research in the field has primarily focused on enhancing various aspects of PLL performance, including phase noise, spur suppression, settling time, and tuning range [1,2].

In essence, the reference spur is caused by the non-idealities of the charge pump circuit as well as the phase and frequency detector (PFD) circuit. Ideally, in the locked state, the static phase error between the input reference clock and the output signal of the divider should be zero because of the infinite DC loop gain [3,4,5,6,7].

However, to maintain a constant control voltage, the static phase error is not zero due to the presence of non-idealities. These non-idealities are primarily introduced by the charge pump, which includes factors such as current mismatch, current leakage, switching time error between PMOS and NMOS transistors, and so on.

When the non-idealities are converted to the current mismatch in the charge pump [8], the current mismatch can result in ripples in the tuning voltage of the voltage-controlled oscillator (VCO). Consequently, the modulated oscillation frequency of the VCO degrades the spectral quality of the output signal [9,10,11,12]. In order to improve the signal quality, various techniques have been proposed to directly improve the current matching of the charge pump [13] or apply analog [14,15] or digital [16,17,18,19] calibration to achieve it.

In addition to the charge pump, the frequency divider plays a vital role in achieving high-speed frequency division while maintaining signal integrity. While various techniques have been introduced to improve the tank-based injection-locked type, the current mode logic (CML) type is widely recognized for its superior division bandwidth [20,21,22,23,24,25,26].

In this paper, we present a detailed design of a wideband PLL featuring low reference spur and low phase noise. The proposed wideband PLL is implemented using a 130 nm CMOS process. The structure of the paper is organized as follows: In Section 2, the PLL architecture and its constituent modules are discussed. Section 3 introduces the design of the clock feedthrough suppressed charge pump with additional bias current branches, the VCO with a wide tuning range, and the symmetrical CML divider, respectively. Section 4 presents the experimental results obtained from the proposed PLL. Finally, Section 5 concludes the paper by summarizing the key results and implications of the research.

2. PLL Architecture

Figure 1 illustrates the block diagram of the proposed wide-tuning PLL. It comprises essential components, such as a phase and frequency detector (PFD), a charge pump, a third-order loop filter, a VCO, and a divider.

The charge pump in the PLL is crucial to achieve low current mismatch. By minimizing the discrepancies between current sources, the low current mismatch charge pump effectively reduces random phase modulation, thereby enhancing the overall phase noise performance of the PLL.

To improve the charging and discharging speed, the charge pump utilizes a source-switched structure. Furthermore, to reduce the current mismatch in the charge pump, we employ a source-switched charge pump with additional bias current branches. These branches finely adjust the charging and discharging transistor currents, compensating for process, voltage, and temperature (PVT) variations. In addition, a rail-to-rail operational trans-conductance amplifier (OTA) is employed to enhance the accuracy of the current replication. This design choice ensures improved current replication accuracy, resulting in low output voltage ripple and enhanced phase noise performance.

The VCO is designed to provide a wide frequency tuning range while optimizing the trade-off between phase noise and power consumption. By employing tail resistors, the VCO allows for fine adjustment of the phase noise characteristics, ensuring optimal performance across the desired frequency range. The VCO is specifically designed to oscillate within the frequency range of 1.9 GHz to 3.1 GHz. It is composed of a pair of cross-coupled NMOS transistors and an LC tank. To accommodate variations in PVT, a 7-bit switched capacitor array (SCA) is employed, ensuring that the frequency tuning range meets the design specifications.

To achieve the desired frequency tuning range of 2 to 3 GHz with a reference frequency of 100 MHz, a significant frequency division ratio of approximately 30 is required. To meet this requirement, a 4-stage divide-by-2/3 circuit is employed to achieve high-speed frequency division and maintain signal integrity. The proposed divider is specifically designed to provide a frequency division ratio ranging from 16 to 31, effectively fulfilling the specified criteria. The divide-by-2/3 circuit employs CML AND gates and latches to enhance the high-frequency operation speed.

The open-loop transfer function of a conventional charge pump PLL is expressed as follows:

$$H_o\left(s\right)=\frac{I_{CP}{K}_{VCO}}{2\pi Ns}{Z}_{LF}\left(s\right)$$

(1)

where I${}_{CP}$ represents the current value when the charge pump is charged or discharged, K${}_{VCO}$ is the tuning gain of the VCO, N is the frequency division ratio, and Z${}_{LF}$(s) represents the characteristic impedance of the loop filter.

A PFD, a charge pump, and a divider are the main contributors to the in-band noise of a PLL. The noise transfer function of the PFD and the charge pump can be expressed as follows:

$$H_i\left(s\right)=\frac{N{H}_o\left(s\right)}{1+H_o\left(s\right)}·\frac{2\pi }{I_{CP}}.$$

(2)

In order to reduce the contribution of the PFD and the charge pump to the output noise of the PLL, it is necessary to increase the output current of the charge pump appropriately.

Additionally, the noise transfer function of the reference clock and the divider can be represented as follows:

$$H_d\left(s\right)=\frac{N{H}_o\left(s\right)}{1+H_o\left(s\right)}.$$

(3)

According to Formula (3), for the constant noise of the reference clock and the divider, its contribution to the output noise of the PLL is basically constant when the frequency division ratio is determined.

The VCO plays a significant role in the out-of-band noise of the PLL. The noise transfer function of the VCO is expressed as follows:

$$H_n\left(s\right)=\frac{1}{1+H_o\left(s\right)}.$$

(4)

The phase noise spectrum (S${}_{\Phi }$) of the VCO is proportional to the square of K${}_{VCO}$. It can be mathematically represented as follows:

$$S_{\Phi }\propto \frac{1}{Q_{tank}^2}{\left(\frac{K_{VCO}}{2\Delta \omega }\right)}^2.$$

(5)

where Q${}_{tank}$ is the quality factor of the VCO’s LC tank. In order to achieve low phase noise in the VCO, it is essential to ensure that the K${}_{VCO}$ is not excessively large.

Referring to Formulas (1) and (4), if K${}_{VCO}$ is certain, I${}_{CP}$ needs to be large in order to minimize the contribution of the VCO noise to the output noise of the PLL. This is similar to the case of the charge pump, where increasing I${}_{CP}$ helps reduce the impact of the charge pump noise on the output of the PLL.

3. Circuit Design

3.1. Clock Feedthrough Suppressed and Low Current Mismatch Charge Pump

The charge pump is a critical component in the proposed PLL design. It is responsible for generating the required voltage levels to control the loop dynamics. But in fact, there are many non-ideal factors in charge pumps, among which, current mismatch, clock feedthrough, charge sharing, and charge injection lead to non-idealities of the reference spur of PLL.

Among them, the clock feedthrough is caused by the gate–drain capacitor of the switched transistor, which leads to the high-frequency components being fed to the loop filter through this parasitic capacitor, thus leading to the deterioration of the PLL’s reference spurs. In order to reduce the influence of the clock feedthrough, it is a better choice to adopt the source-switched charge pump.

To mitigate the impact of the clock feedthrough, utilizing the conventional source-switched charge pump is proved to be a favorable option, as illustrated in Figure 2a. The source-switched charge pump can reduce the output voltage ripple compared to other charge pump architectures. By dynamically switching between current sources, it effectively mitigates the impact of switching transients and ripple noise. As a result, the output voltage exhibits improved smoothness and stability. In Figure 2a, MP${}_2$ and MN${}_2$ operate as current sources, and MP${}_1$ and MN${}_1$ operate as switches. Additionally, the switched transistors placed close to the power and ground improve the charging and discharging speed.

Indeed, along with its advantages, the source-switched structure also leads to negative effects resulting from the current mismatch. Their saturation currents in accordance with the channel length modulation effect can be expressed as

$$I_{UP}=\frac{1}{2}{\mu }_p{C}_{ox}{\left(\frac{W}{L}\right)}_{P2}{(V_P-V_{GP}-V_{tp})}^2(1+{\lambda }_p|V_{OUT}-V_P\left|\right)$$

(6)

$$I_{DN}=\frac{1}{2}{\mu }_n{C}_{ox}{\left(\frac{W}{L}\right)}_{N2}{(V_{GN}-V_N-V_{tn})}^2(1+{\lambda }_n|V_{OUT}-V_N\left|\right).$$

(7)

The clock signals are fed to the nodes V${}_P$ and V${}_N$ through $C_{gd,p1}$ and $C_{gd,n1}$, which are the gate–drain capacitors of MP${}_1$ and MN${}_1$, respectively, so that the node voltages of V${}_P$ and V${}_N$ change. When the voltages of nodes V${}_P$ and V${}_N$ change, I${}_{UP}$ and I${}_{DN}$ will change, which will lead to non-ideal factors. Assuming the equivalent capacitors of nodes V${}_P$ and V${}_N$ to the ground are represented as $C_P$ and $C_N$, respectively, we note that the voltage variation at node V${}_P$ due to clock feedthrough is given by V${}_{DD}$$C_{gd,p1}$/($C_{gd,p1}$ + $C_P$).

In order to reduce the influence of the clock feedthrough on nodes V${}_P$ and V${}_N$, MP${}_1$ and MN${}_1$ are replaced by transmission gates, and MOS transistors with a filtering function are added at V${}_P$ and V${}_N$ to further reduce the influence of non-ideal factors, as shown in Figure 2b. The differential signals UP and $\overline{UP}$, as well as DN and $\overline{DN}$, undergo cancellation of the feedthrough signals upon passing through the transmission gates. Since $C_{gd,p1}$ and $C_{gs,n5}$ are generally not equal, a net amount of change appears at V${}_P$ given by V${}_{DD}$ ($C_{gd,p1}$ − $C_{gs,n5}$)/($C_{gd,p1}$ + $C_{gs,n5}$ + $C_P$). Moreover, due to the low-voltage operation of the charge pump, the transmission gate dimensions are increased to mitigate voltage drops. This enlargement of transmission gate dimensions, however, leads to larger parasitic capacitances within the transmission gates, facilitating favorable clock feedthrough conditions. Hence, it becomes imperative to further suppress the clock feedthrough at nodes V${}_P$ and V${}_N$. To address this challenge while considering design simplification, we adopted the utilization of NMOS transistors, MF${}_1$ and MF${}_2$, as a filtering mechanism. NMOS transistors were introduced at nodes V${}_P$ and V${}_N$, as depicted in Figure 2b, exploiting their inherent parasitic capacitances ($C_{gs}$ and $C_{gd}$) to facilitate the filtering process. It is noteworthy that the introduction of the filtering NMOS transistors is specific to the source-switched charge pump.

Figure 3 illustrates the impact of filtering NMOS transistors of different dimensions on the filtering effectiveness at the V${}_P$ node. It is evident that, in the absence of filtering NMOS transistors, the voltage variation at node V${}_P$ due to clock feedthrough with the transmission gate is less affected by clock feedthrough than without the transmission gate. Upon the integration of filtering NMOS transistors, an increase in the size of the filtering NMOS transistors MF${}_1$ results in a more pronounced attenuation of feedthrough. However, with the increase in the capacitance of the filtering NMOS, the charging and discharging speeds of the current slows down, which leads to the unequal current copied by the current mirror and the current mismatch. Optimal results are achieved when the area of the filtering NMOS transistor is compromised with the filtering effect. Specifically, as can be seen from Figure 3, when the area of the filtering NMOS transistor is twice that of MP${}_1$, the trade-off between the charging and discharging speeds of the current and the filtering effect is good for achieving the desired feedthrough suppression. Another function of the filtering NMOS transistor is to reduce the voltage transients at the source terminal during feedthrough, as well as to mitigate the potential impact of signal coupling onto the gate terminal of the current mirror.

The current mismatch is one of the key factors contributing to the reference spur in the PLL. The amount of the reference spur is approximately calculated as [27]

$$P_{spur}\left(dBc\right)=20log(\frac{\Delta \varphi }{\sqrt{2}}·\frac{N·BW}{f_{ref}})-20log\left(\frac{f_{ref}}{f_p}\right)$$

(8)

where N is the frequency division ratio, BW is the PLL bandwidth, and f${}_p$ is the frequency of the pole in the loop filter. $\Delta \varphi$ refers to the phase error. The major phase error contributors are the leakage currents, the current mismatch of the charge pump, and the switching time mismatch between the up and down current pulses. The analytic expression of the phase error is

$$\Delta \varphi =\Delta {\varphi }_{leakage}+\Delta {\varphi }_{current}+\Delta {\varphi }_{time}=2\pi ·(\frac{I_{leakage}}{I_{CP}}+\frac{\Delta I}{I_{CP}}·\frac{T_{switch}}{T_{ref}}+\frac{\Delta T·T_{switch}}{T_{ref}^2})$$

(9)

where I${}_{leakage}$ is the leakage current, I${}_{CP}$ is the current of the charge pump, T${}_{switch}$ is the frequency of reference clock, and $\Delta$T, $\Delta$I are the time and current mismatch, respectively.

Formulaes (8) and (9) show that the reference spur P${}_{spur}$ is positively correlated with the current mismatch $\Delta$I of the charge pump, which means that the reference spur can be scaled down by decreasing the current mismatch of the charge pump.

In order to effectively constrain the current mismatch within a limited range, additional bias current branches, namely I${}_{N,offset}$ and I${}_{P,offset}$, introduced parallel to P${}_1$ and N${}_1$ in the charge pump to finely adjust the currents of both the pump-up and pump-down current mirrors. Figure 4 illustrates the proposed circuit configuration for the charge pump.

Due to the presence of the operational transconductance amplifier (OTA), the voltage at V${}_{OUT}$ is equivalent to the voltage at V${}_D$. However, the existence of the transmission gates prevents the source voltages of P${}_1$/P${}_2$ and N${}_1$/N${}_2$, which act as current mirrors, from being exactly equal. According to Formulae (6) and (7), a mismatch in currents occurs between the transistors P${}_1$ and N${}_1$. Additionally, process deviations in MOS transistors contribute to pump-up and pump-down current mismatch.

To further mitigate the impact of the current mismatch-induced reference spur, the current compensation branches are introduced into the circuit, as depicted in Figure 4. When the switches are connected to the ground or the power supply, the compensation branches remain closed and do not participate in current compensation. However, when the switches are connected to the gate terminals of the parallel MOS transistors, the compensation branches become active, aiding in current compensation. Notably, the compensation branches’ minimum compensating current should not be excessively large, thus a minimum current of 2 µA is set with 4-bit compensation current branches.

Figure 5 illustrates the current mismatch effect under different process corners and temperatures. As observed from the graph, compensating through the bypass branch effectively limits the mismatch to below 0.1% across various process corners.

After designing the charge pump, it is necessary to conduct a linearity simulation for the cascade of the PFD and the charge pump. By changing the time error $\Delta$T between the rising edge of the reference clock and the rising edge of the output of the loop feedback clock, the average output current of the charge pump can be viewed, as shown in Figure 6. As can be seen from the figure, when the time error $\Delta$T is greater than zero, the average output current of the charge pump is positive, indicating that it is in a charging state at this time. When the time error $\Delta$T is less than zero, the average output current of the charge pump is negative, indicating that it is in a discharging state at this time. However, with the increase of the time error $\Delta$T, the average output current of the charge pump increases. When $\Delta$T exceeds an integer multiple of the period of the reference clock, the average output current of the charge pump will change approximately periodically. When the rising edge of the reference clock coincides with the rising edge of the loop feedback clock, that is, $\Delta$T is zero, the average output current of the charge pump is the mismatch current. After the charge pump is compensated, the average output current drops from 1.76 µA to 0.71 µA, which shows that the current mismatch between the charging current and the discharging current is 0.71 µA when the PLL is locked.

3.2. Wide-Tuning Range VCO

Figure 7 illustrates the schematic of a cross-coupled LC-VCO. The proposed VCO employs a differential topology consisting of NMOS transistors, which generate negative resistance to compensate for losses in the LC tank. To achieve current control, resistor-switched is utilized instead of a current mirror, as it contributes less flicker noise.

The current of the proposed VCO can be adjusted within a range of 0.5 mA to 15.5 mA, with a step size of 0.5 mA, utilizing a 6-bit resistor bank. For frequency tuning, the VCO incorporates a 7-bit binary-weighted metal–insulator–metal (MIM) capacitor bank for coarse tuning and varactors for fine-tuning. The designed VCO offers a tuning range from 1.9 GHz to 3.1 GHz. To characterize the VCO’s performance, an average gain (K${}_{VCO}$) of 50 MHz/V is targeted, ensuring suitable frequency modulation capabilities.

3.3. Symmetrical CML Divider

CML dividers utilize differential voltage signaling, which offers several advantages. Firstly, differential signaling helps in rejecting noise, leading to improved signal integrity. Additionally, the differential nature of CML circuits enables seamless integration with other differential circuits present in the system, promoting compatibility and ease of design.

Moreover, CML dividers are capable of operating at high frequencies, making them suitable for applications that require the rapid division of clock signals or frequency synthesis. This attribute enhances their versatility and applicability in various systems.

The total frequency division ratio achieved by the cascade of multi-stage divide-by-2/3 circuits is calculated as 2${}^N$ to 2${}^{N+1}-1$, where ’N’ represents the number of stages.

Figure 8 presents the block diagram of the proposed frequency divider utilized in this design. The frequency divider employs a four-stage cascade structure of divide-by-2/3 circuits, enabling a frequency division ratio ranging from 16 to 31. To further enhance the performance of the frequency divider, retiming technology is implemented.

The divide-by-2/3 circuit is depicted in Figure 9, and the circuit of the CML latch is depicted in Figure 10a. Due to the differential input and output nature of the CML divider, there exists a heightened requirement for circuit symmetry. In Figure 9, with the exception of the input terminals of AND2 and Latch2, which accommodate control signal B, the input terminals of the remaining AND gates and latches are driven by clock signals. In cases where input signals are not propelled by buffer elements, the conventional topology illustrated in Figure 10b may result in disparate differential input impedances within the AND gate. This incongruence in impedance is undesirable within a fully differential structure.

In response to this concern, an improved topology, as depicted in Figure 10c, has been devised. In this enhanced configuration, input signals A and B exhibit symmetric conditions, thus facilitating a more symmetrical design for the entire 2/3 divider. This symmetric arrangement is conducive to a more balanced design of the overall 2/3 divider, which is especially advantageous within the context of the CML divider’s imperative for heightened circuit symmetry.

CML circuits offer speed advantages due to two key properties. Firstly, they employ moderate voltage swings, which helps in achieving faster operation. Secondly, only NMOS devices are used in the data and clock paths, further enhancing the speed performance.

The output swing of the latch can be adjusted by varying the resistance value of R${}_D$, allowing for control of the static output bias voltage. This adjustment helps optimize the performance and characteristics of the CML latch circuit.

If the transistors switch completely, the single-ended output voltage swing of Output Q and Output $\overline{Q}$ can be expressed as

$$V_{pp}=I_{SS}{R}_D$$

(10)

where V${}_{pp}$ is the maximum single-ended output voltage swing of Output Q and Output $\overline{Q}$. I${}_{SS}$ is the average tail current and R${}_D$ is the load resistance.

The output common mode (CM) level of Output Q and Output $\overline{Q}$ is given by:

$$V_{CM}=V_{DD}-\left(I_{SS}{R}_D\right)/2.$$

(11)

To increase the maximum operating frequency of the divider, the current of the CML latch can be increased, but this may result in a reduction in the output swing and the driving ability of the latch becomes weak.

4. Measurement Results

The designed PLL is fabricated in a 130 nm CMOS technology process. The control code voltages, the frequency tuning voltage, and the DC supply are wire-bonded to a printed circuit board (PCB). The chip micrograph of the fabricated PLL is shown in Figure 11.

A PXA signal analyzer (Agilent N9030A, Agilent Technologies, Santa Clara, CA, USA) is used to measure the proposed PLL. During the test, the operating current of the VCO is set to 11.5 mA, and the branch current of the charge pump is set to 2 mA. At these settings, Figure 12 and Figure 13 show the output spectrum and the phase noise of the proposed PLL at a carrier frequency of 2.4 GHz, respectively. The reference spur of the PLL is −74.39 dBc below the carrier as shown in Figure 12. The measured phase noise of the PLL is −102.55 dBc/Hz@100kHz and −127.15 dBc/Hz@1MHz as displayed in Figure 13. The total power consumption of the proposed PLL is 33.6 mW from a 1.2 V supply. Among the components, the charge pump consumes 5.5 mA, the VCO core draws 11.4 mA from a 1.2 V supply voltage, and the divider dissipates 12.8 mA. In terms of jitter performance, the measured rms jitter integrated from 10 kHz to 10 MHz at a carrier frequency of 2.4 GHz is 340.99 fs. Additionally, the figure-of-merit (FoM) at the same carrier frequency is −234.08 dB.

Table 1. Performance comparison with the state of the pulished PLLs.

Reference		This Work	ISSCC’19 [28]	ISSCC’15 [29]	ISSCC’14 [30]	JSSC’13 [31]	JSSC’12 [32]
Technology (nm)		130	10	45	40	65	130
Supply (V)		1.2	0.9	1	N/A	1.2	N/A
Oscillator Topology		LC	Ring	Ring	LC	LC	LC
Reference freq. (MHz)		100	100	22.6	26	40	60
Output freq. (GHz)		2.4	3.2	2.4	3.883	3.61	2.438
/freq. Range (GHz)		/(2.0–3.0)	/(0.5–5.0)	/(2.0–3.0)	/(3.276–3.883)	/(3.0–4.0)	/ N/A
Tuning Range (%)		40	164	40	17	28.6	N/A
Phase Noise (dBc/Hz)	@100 kHz	−102.55	N/A	−109.18	−105.49	−103.62	−102.27
	@1 MHz	−127.15	N/A	−113.78	−123.06	−103.79	−99.63
RMS jitter (fs)		340.99	1870	970	300	972.9	1092.6
		(10 k–10 M)	(100 k–100 M)	(1 k–200 M)	(1 k–10 M)	(3 k–30 M)	(10 k–10 M)
FoM (dB) *		−234.08	−233	−234.1	−242	−235.1	−229.41
Reference Spur (dBc)		−74.39	−57	−65	N/A	−71	−54.7

*: FoM = 20log(J${}_{rms}$/1 s) + 10log(P${}_{DC}$/1 mW).

summarizes a comprehensive comparison of the performance between the proposed PLL and other PLLs reported in previous studies. The phase noise performance of the proposed PLL stands out significantly in comparison to the reported PLLs. In addition, the proposed wideband PLL achieves a tuning range of 40%, which is only narrower than that of [28]. The FoM of the proposed PLL is comparable to that of other works. However, it is worth noting that their reference spur is worse than the proposed PLL’s reference spur of −74.39 dBc.

5. Conclusions

We presented a comprehensive design of a wideband PLL with low reference spur and low phase noise. The charge pump employs a source-switched charge pump with additional bias current branches to minimize current mismatch, resulting in improved phase noise performance. The utilization of the 4-stage CML divide-by-2/3 circuit in the frequency divider enables high-speed frequency division without the limitations of narrowband resonator structures. The VCO design, incorporating a wide tuning range and adjustable tail resistor, optimizes the trade-off between phase noise and power consumption. The measured results demonstrate a frequency tuning range from 2.0 GHz to 3.0 GHz, with a remarkable tuning range of 40%. Notably, the PLL exhibits a reference spur of −74.39 dBc and a FoM of −234.08 dB at a carrier frequency of 2.4 GHz. The achieved performance levels and the significant advancements in phase noise and reference spur make the proposed wideband PLL a promising solution for high-speed wireless communication systems. The low phase noise and low reference spur characteristics enable stable and accurate frequency synthesis, contributing to improved data transmission and reception in future wireless communication applications.