SHDL—A Hardware Description Language and Open-Source Web Tool for Online Digital Systems Design Teaching

Abstract

Hardware description languages and tools require a considerable amount of teaching activities in a digital systems design course, which is difficult to accommodate in a limited time frame, and to use for e-learning. This paper presents our user-friendly and open-source web-based digital design tool, SHDL, which is used to describe and simulate hardware components and translate them into a standard language. SHDL is a teaching language and tool for digital design, which aims to improve the teaching and learning experience in digital systems design courses. The use and evaluation of the proposed online teaching model for the Digital Electronic Systems Design (DESD) course, using the SHDL tool for e-learning during the COVID-19 phase, is presented. Using the SHDL language and web tool, we have created many examples of digital circuits that prepare students to explore their own designs. The example components can also be used as digital system modules, leading to better modularity of the final project. The use of SHDL in the DESD course has shown that the proposed language leads to fewer syntax, simulation and synthesis errors in the designed circuits. The evaluation results show that at the end of the laboratory exercises, there was no longer a difference in knowledge between the students without prior VHDL experience and the other students. The results encourage us to continue using SHDL, and to complement the traditional DESD teaching methods with e-learning.

1. Introduction

Technological advances in digital electronic systems have influenced education in digital system design. Low-level schematic design is inefficient for today’s complex circuits, and is being replaced by hardware description language (HDL) coding [1,2]. The standard languages—VHDL, Verilog, and SystemVerilog—describe circuits at several levels of abstraction: structural; data flow; register transfer (RTL); and behavioral. In digital circuit education, we start at the lower levels, which are closely related to basic logic theory, and continue to the higher levels, for efficient design. Digital systems design courses focus on designing architectures and describing digital components using HDL. There are several higher-level digital design languages [3], but the standard languages remain, and provide a solid foundation for undergraduate education [4].

Digital systems design exercises evolve from fully guided to largely autonomous [5]. Students practice the digital design process, which consists of component description, simulation, synthesis, and implementation on programmable devices. The overall learning outcome of the digital systems design course is the student’s ability to design digital hardware that executes specific algorithms. During the hands-on laboratory exercises with a standard VHDL model, students frequently ask questions about deviations from expectations when compiling or simulating the VHDL model, problems with the synthesis tool, and unexpected circuit behavior during final testing. Students find the learning outcome difficult to achieve; therefore, it requires an active learning approach [6]. Digital system projects are used for hands-on laboratory and online digital design courses [7].

Learning to describe digital circuits is more difficult than learning computer programming, because of the syntax and semantic rules of the design language, the understanding of synthesis requirements, and the lack of pedagogical design tools [8]. A code describing circuit components working in parallel follows different semantic rules to those of a typical programming code. Designing digital circuits requires knowledge of how logic and registers work, and of language syntax and design tools. HDL is used to simulate digital circuits, and only a subset of the language is suitable for circuit synthesis.

To improve the teaching and learning experience in digital design, we recently developed the pedagogical Small Hardware Description Language (SHDL) and a free web tool [9]. The proposed language has simple syntax, which includes only synthesizable constructs used in educational circuits. Figure 1 shows the basic synthesizable HDL modeling components. A digital circuit model describes the name of the circuit, a set of signal declarations, and an architecture specification block with a set of statements. There are three types of statements that support different modeling styles and levels of abstraction:

• instance—an instantiation of a circuit component;
• assignment—describes combinational data flow;
• sequential block (e.g., conditional assignments) for algorithmic behavioral specification.

Figure 1. Components of a circuit model in a hardware description language.

Figure 1. Components of a circuit model in a hardware description language.

The standard HDL syntax and modeling rules are difficult for inexperienced designers. Circuit models are verified on a simulator, which requires tool-specific simulation settings or, preferably, an HDL simulation test bench. The test bench is a structural HDL model with instructions that describe the timing of the input signals: these additional syntax rules are required even for verification of simple models. Our tool includes a circuit simulator, enables an easy simulation setup, and generates readable VHDL and simulation code to be used in the digital design flow. With the SHDL, we can cover the expected digital modelling topics in the limited time frame of a typical digital systems design course.

After the initial SHDL application for teaching purposes [9], we improved the syntax of the language, to render it closer to the standard VHDL language, and we extended the functionality of the tool, for better simulation support and online model management.

The proposed SHDL used in the Digital Electronic Systems Design (DESD) course helps in learning the modeling concepts for digital systems. Students who are not familiar with the standard VHDL [10] can take advantage of the initial knowledge difference, and keep up with the lab assignments on digital systems. The SHDL web tool fits seamlessly into the existing design process. The web tool also enables the implementation of online teaching/learning, which was specifically applicable during the COVID-19 lockout.

The predominant teaching method in engineering education is the traditional teaching method: frontal, face-to-face lectures followed by practical work. It is characterised by classroom implementation with time and space constraints, using traditional methods (lecturer-centred) and traditional resources, such as textbooks, discussions, and chalkboards [11]. Technological development has induced a demand to exceed these time/space constraints. With the accelerated development of technology and the internet, teaching materials have moved online. E-learning is any learning that involves technology as a learning aid: it can be done both in the classroom and with teacher and learners separated [12]. E-learning is predominantly called online learning, and is defined as a learning experience using different devices with internet access. Students can be anywhere (locally independent), and can learn and collaborate with instructors and other students [13]. The challenges for successful implementation of e-learning systems are to provide adequate system, service and content quality, technological infrastructure, awareness, management support, security support, and training [14].

The contributions of this paper are:

• presentation of the improved SHDL syntax and SHDL web tool;
• introduction of an online teaching model for the DESD course, using the SHDL tool;
• evaluation of the SHDL web tool, in relation to the knowledge output of the online teaching model;
• discussion of the online teaching model and learning experience.

To facilitate the reading of this paper, an overview of the existing languages and tools is given in Section 2. Section 3 describes the proposed SHDL and our open-source SHDL web tool. Section 4 presents our teaching model and its implementation in the DESD course. Section 5 presents the methods for assessing students’ knowledge. The assessment of students’ online learning with SHDL is described in Section 6, and the results are discussed in Section 7. Finally, Section 8 summarizes our experience with the proposed tool, and discusses opportunities for further development and pedagogical use.

2. Hardware Description Learning Tools

Existing Digital Design Languages and Tools

Digital logic simulators allow experiments with digital circuits to be conducted on a computer. Logic simulators are widely used for teaching digital circuits at lower levels of abstraction. A survey of simulators for use in education can be found in [15], and the incorporation of simulation tools into digital logic instruction is described in [16]. Several tools have been developed to create a virtual logic design laboratory [17]. A web-based platform for visualizing and animating digital logic is described in [18]. While these tools are excellent for introducing digital design, the digital systems course requires modeling tools at higher levels of abstraction for rapid design and prototyping.

Fast digital design is supported by several commercial development tools. Matlab [19] and LabVIEW [20] are used for design and analysis in laboratory practice, due to their powerful graphical user interface. They are particularly suitable for signal processing applications [21], but their models are too far removed from basic logic principles, and their commercial nature limits their usability in education.

Standard hardware description languages enable basic logic, RTL, and high-level behavioral modeling. There are several commercial and open-source digital simulators for standard HDLs. HDL simulation and synthesis tools are bundled in programmable device manufacturer software [22], designed for trained design engineers. The open-source VHDL simulator, GHDL [23], is a command line tool that requires additional software to display simulation waveforms. Researchers have developed a lightweight design environment [24] and a distributed online VHDL compiler and simulator [25]. EDA Playground [26] provides a web tool for testing various digital development tools and languages: the tools require both an HDL model and a testbench for simulation.

An extensive overview of tools languages targeting higher abstraction levels is given in [3]. High-level languages, such as Bluespec [27], Chisel [28], OpenCL [29], HML [30] and synthesis tools [31] aim to increase design efficiency, especially in the development of hardware algorithm accelerators; however, to effectively use the high-level tools, a good understanding of RTL circuit models is required. RTL languages and models provide the developer with full control over the hardware structure, and enable the optimization of the gate-level technology.

Simplified hardware description languages and associated tools have been pro-posed, to facilitate learning of HDL design methodology. A plain, simple HDL with web tool [8] introduces hardware modelling in a C-like syntax, to help students with the unfamiliar HDL syntax and programming paradigm. The Finite State Machine modeling language and tools [32] enable rapid prototyping for a particular type of digital circuit. Compact HDL [33] presents a simplified version of VHDL and Java tools for automatic translation to VHDL.

In the past, we used a subset of VHDL for the exercises and projects in the DESD course. Due to the complex syntax, we were only able to cover very simple circuits comprehensively, or to rely on pre-built IP modules. Recently, we proposed a language, SHDL, based on a small subset of VHDL-like structures and a web-based tool [9] tailored to the needs of HDL design in education. The tool is freely available and open source, to allow for future extensions. By introducing the language with simple syntax rules, students can benefit from more effective learning.

The aim of this paper was to explain the introduction of SHDL in the digital systems design course. The use and evaluation of the SHDL web tool for e-learning is presented herein.

3. Proposed Methodology

To facilitate learning HDL, we developed a language with a small set of syntax rules, called SHDL, and a tool that provides an intuitive simulation setup [9]. SHDL is seamlessly embedded into the existing digital systems design flow as a front-end modeling tool that produces standard HDL output (Figure 2). The components of the digital system architecture are designed and simulated as VHDL or SHDL models. The translated VHDL is used for synthesis, implementation and verification with back-end Field-Programmable Gate Array (FPGA) tools. SHDL can be introduced into the digital systems design course with only minor additions to the course material, and students can choose their preferred design language.

3.1. Small Hardware Description Language

The proposed small hardware description language is not a full-featured HDL, but serves as a teaching language with a minimal set of modeling constructs. Our initial specification of SHDL included syntax rules from the C and VHDL languages, introducing a mixture of VHDL operators and conditional and block statements from C with curly braces. To help students acquire VHDL syntax, the new version of SHDL now includes VHDL-like conditional statements and block start and end indicators.

VHDL has a detailed model specification consisting of the declaration of the circuit interface in the entity statement and the function in the architecture statement. The interface in SHDL is specified by declaring input and output signals. The specification of the circuit entity name is optional, as a default name from the tool settings can be used for a small test circuit. The block start and block end indicators are also optional, and are only required for structural models with multiple circuit entities.

An SHDL model is described in the Backus–Naur form, as follows:

circuit :== [‘entity’ name] {declarations}       [‘begin’] block [‘end’] declarations :== declaration {[;] declaration} declaration :== name_list ‘:’ [mode] type [= value] mode   :== ‘in’ | ‘out’ name_list :== identifier {, identifier} block   :== statement {[;] statement} statement :== assign | cond_as | if_stat | instance

Circuit signal declarations and modeling statements are separated by optional semicolons. Signal declarations are used to define the internal signal or port mode and the data type of the signals. External ports are defined using the reserved words ‘in’ or ‘out’. A basic data type is a combination of a letter u (unsigned) or s (signed), and the number of bits. An initial value can be specified for the internal signals. Example for the declaration of ports and signals:

a,b: in u1 /* 1-bit input ports       */ c : out u4 /* 4-bit unsigned output port  */ d : s8  /* 8-bit signed internal signal  */ q : u2 = 1 /* 2-bit signal with initial value 1 */

Digital components designed for implementation in programmable logic devices have mainly unidirectional ports needed for internally connected components. Bidirectional external ports can be handled by device-specific components, so we do not consider bidirectional signals in the simplified language.

An array data type is used for modeling memory structures. Arrays are limited to internal signals, and have a certain number of elements. A 256 × 8 bit memory signal is declared as a data type: 256u8. The basic data types are sufficient for creating HDL circuit models, but we have also added symbolic enumeration types for high-level description of state machines. The symbolic values are specified when declaring the signal, for example:

state: (idle, run, stop);

The data flow model consists of a series of assignment statements. Combinational logic is denoted in assignment statements by the = operator. The assignment operator <= is used for sequential logic where assignments are executed on the rising edge of the system clock. In addition to simple assignment expressions, SHDL also supports conditional ‘when–else’ assignments for modeling digital multiplexers and comparators.

assign  :== identifier as_op expression as_op  :== ‘=‘ | ‘<=‘ cond_as :== identifier as_op expression ‘when’ condition ‘else’ expression

Assignment statements define logical, arithmetic and binary expressions for the target signal. The expressions contain synthesizable numeric vector operators from VHDL, in the following order of precedence:

• parenthesis: (, )
• vector slicing: name(index), name(high downto low)
• unary: -, not
• multiply: *
• arithmetic: +,− and concatenate: &
• relational: =, /=, >, >=, <, <=
• logic: and , or, xor, nand, nor

The SHDL parser accepts constant values in various formats: VHDL-like bit values and bit strings, as well as numbers in decimal, hexadecimal or binary form. VHDL again requires matching data types in expressions and assignments, using explicit type conversion functions: exceptions are some overloaded operators—for example, addition of numeric vectors and integers. These requirements are difficult for an inexperienced developer. In the proposed language, we omit all matching requirements, to simplify the creation of digital models. The data type is matched to the values during the evaluation of the expression, and is finally converted to the target type of the assignment.

Behavioral circuit description is based on conditional statements. The syntax of the conditional statements follows the VHDL if–then format with simplified end:

if_stat :== ‘if’ condition ‘then’ block      {‘elsif’ condition ‘then’ block}      [‘else’ block]      ‘end’

Conditional statements are allowed in VHDL only in sequential blocks, such as process blocks. The order of conditionally executed statements is important in sequential blocks when the statements assign values to the same signal. The order of the statements assigning different signals can be arbitrary, as with concurrent statements in the data flow description. Multiple processing blocks are typically found in VHDL models, due to the separation between sequential logic with registers and combinational logic. The proposed language handles the separation with various assignment operators, and does not require declaration of specific blocks for conditional statements.

The structural design is supported by an instance statement. The instance of the contained SHDL model is specified with an identifier (entity name of the model) and the list of signals associated with the instance port.

instance  :== identifier ‘(‘ name_list ‘)’

3.2. SHDL Compared to VHDL

Table 1. Standard VHDL and proposed SHDL comparison.

Parameter	VHDL’93	SHDL 3
Abstraction	structural, RTL, behavioral	structural, RTL, behavioral
Conciseness	verbose syntax, 97 reserved words	concise syntax 17 reserved words
Modeling ability	combinational logic, synchronous (multiple clock), multilevel (tristate) logic	combinational logic synchronous (single clock) binary logic
Data type	Scalar: enumeration; integer; float; and physical. Composite: array; record access; file.	single bit, unsigned, signed, enumeration, integer one-dimensional array
Type conversion	explicit conv. functions, library overloading	implicit
Modeling hierarchy	component, process, package, function, procedure	component
Generic models	generic parameters	not available

compares the current version of the proposed SHDL language with the standard VHDL’93. Both languages cover the same abstraction levels. The language syntax is concise in SHDL, with a few reserved words compared to the verbose syntax of VHDL. VHDL is capable of modelling a wide range of synchronous and multilevel logic circuits, while SHDL is limited to single-clock synchronous and binary logic levels.

In VHDL, there are a variety of data types used for simulation and building complex models. Another drawback is that even the basic data types (enumerated binary, signed and unsigned vectors) are defined in libraries that must be included in the model. SHDL contains only important data types for synthesizable circuit models. Type conversion in SHDL is implicit, while conversion functions are required in VHDL. In some cases, conversion is not necessary, due to the overloading operators in libraries, which is another source of error for inexperienced developers.

VHDL provides many constructs for building large hierarchical and generic models. SHDL is intended for small models, and only component instantiations are used for hierarchical design.

3.3. Open-Source SHDL Web-Based Tool

We developed the SHDL learning tool as an open-source web application based on a set of JavaScript modules [34]. The tool is available online at: http://lniv.fe.uni-lj.si/shdl/ (accessed on 10 January 2023). The web tool includes:

• the SHDL code editor with syntax coloring;
• code parser and circuit analysis;
• circuit model simulator, waveform viewer, board simulator;
• generator for readable VHDL code with test bench;
• PHP extension for saving models to a server, and support for teachers.

The main module is the SHDL code parser, which builds internal circuit model objects. The model parser stops in case of a rule violation, and outputs an error log. The visit of the model objects is used for semantic checking, resource analysis and tagging of the objects. The tagged model is finally converted into a nicely formatted VHDL model.

The tool’s web page consists of three sections: design input with setup, simulation and output data. Setup sets the parameters for the code parser and generator, as well as the report and simulation settings. The code generator settings define the syntax of VHDL 2008 or VHDL’93, with additional experimental Verilog support. The code editor is based on CodeMirror, which provides coloring of VHDL syntax. Figure 3 shows the user interface of the SHDL tool, with an example of a 3-bit counter. A circuit description begins by specifying the circuit name, and defining signals in the signal table (Figure 3a): this step is optional, and is used to automatically prepare the initial SHDL code with entity statements and signal declarations. After the SHDL model description and parsing (Parse button), the signal table is used to define the signals displayed in the simulation waveform.

By switching to the Analysis tab in the second web page section, the results of code parsing, and statistics about the operations and resources visited (Figure 3b), can be seen. In the latest version of the tool, we have added the visualization of the data flow in the circuit model, and the estimation of the circuit area.

The lower part of the web page is used for the online SHDL simulator (Figure 3c). A discrete event simulator reads the user-set input signal values, and performs a repeated model evaluation and waveform update. The simulator outputs a graphical waveform, and generates a VHDL test bench for use with external tools.

The simulator supports integer, binary, and analog waveform, and displays symbolic enumerated values. When upgrading the SHDL tool to be used for e-learning, an interactive simulation with graphical virtual board was added. The virtual board presented in Figure 4 shows some typical interfaces which can be found on programmable boards: input keys; rotary encoder; output LEDs; two seven-segment displays; and one LED matrix display.

The virtual board helps students visualize the operation of the digital circuit model. The SHDL ports are connected to the board using predefined port names; by clicking the start button, the simulation runs in interactive mode. Circuit signals are displayed on the waveform with slow, medium, or fast update, and on the virtual board at the same time. Clicking on the rotary encoder buttons injects a sequence of signal transitions to the appropriate circuit input port. The virtual board functionality is described in a separate JavaScript library board, which can be upgraded to support additional interfaces.

A PHP front-end was added to the SHDL tool, which now supports the MySQL database for model storage and user management. Examples of SHDL models used for a tutorial web page are stored on the server, and can be loaded into the tool through their link. The database support was added to help lecturers preparing SHDL assignments and checking the user-created models. The SHDL modeling web page now has an option to sign in, access the lecturer-provided models, and save or load user models from the server. The lecturer has administrative access, for adding users and checking their saved models.

4. Teaching with SHDL Web Tool

In this section, we propose an online teaching model based on the presented SHDL web tool for the DESD course. When the COVID-19 pandemic began in March 2020, the educational process had to be redesigned to meet the current needs. The DESD laboratory exercises provide practical experience with the design process, by hands-on learning on digital development boards that represent the greatest challenges of the online redesign. We start by constructing the online teaching model. We then present a set of introductory examples for online DESD laboratory exercises implementation.

4.1. Online Teaching Model

Online learning models originate from the distance learning first generation model, also known as the correspondence model [35], and have further evolved, with developing education technology, to form e-learning models [36]. Anderson’s Online Learning Model [37] was an attempt to build a common integrated theory of online education that could subsume all other models, with the exception of face-to-face interaction in formal classrooms.

We propose an online teaching model (Figure 5) based on Anderson’s online learning model elements [37], but designed for the specific needs of DESD teaching: here, the word ‘teaching’, in the proposed model, is used in the sense of the predominant teacher-centered approaches. The proposed teaching model can also be upgraded to blended teaching, by converting some of the online designed courses into face-to-face lectures [38]. Studies regarding the use of e-learning reveal that there are many critical factors that affect the usage or adoption of e-learning systems [39]. In this paper, we focus on the online teaching model that was required to address the needs generated by the COVID-19 pandemic. An e-learning system for DESD teaching purposes was integrated into the existing faculty e-learning system. Our main focus is on content quality, while other critical factors are not considered in this paper.

The teacher (T) gives theoretical lecture content transformed into e-learning materials for the students (S), when an online classroom (1) is used. The delivered e-learning material is explained through a remote online lecture using a video conferencing tool within the online classroom (1), or by using some other online communication tool. Thereafter, the students perform laboratory exercises remotely in an online laboratory (2), where the teacher can give additional instructions, if needed. The level of acquired cognitive knowledge is assessed by using knowledge assessment tools (1.1). In the case of a student’s misunderstanding being detected, the teacher can carry out an audio and/or video communication (3) via online tools. Each element of the proposed teaching model is described in the following text.

(1) Online classroom tools have evolved from e-learning management systems into what we know today as ‘learning platforms’, which provide the possibility of creating and organising/delivering assignments and other e-learning materials, providing feedback information, simple teacher–student communication, and more. There are various free-of-charge learning platforms, such as Edmodo, Beenpod, Goclass and Moodle, and newer popular alternatives, such as Schoology, Canvas and Google Classroom. We use Moodle for delivering e-learning material that comprises textual e-learning material, digital circuits design code examples, and video instructions; whereas, for a communication tool, we prefer using the Zoom online tool. We also use Moodle as a knowledge assessment tool (1.1). There are many different tools available on the World Wide Web. The following are the three most commonly used free tools with different usability domains: Google Forms; Kahoot; Quizizz. Google Forms is the most widely used tool developed for multiple operating systems and for mobile phones and tablets. With the created tests assignments, we can easily gain insight into the student’s cognitive domain knowledge. Responses to completed forms are collected on an ongoing, transparent, and automatic basis, in the form of response data and charts. The collected data can be further analyzed.

(2) The online laboratory consists of computers with installed FPGA tools (Quartus), a VHDL simulator (ModelSim), FPGA development boards, an SHDL web tool, cloud, and a webcam. Teacher and students can access the online laboratory using a remote access service. After a circuit model has been designed and tested, either with the VHDL simulator or online with SHDL (2.1), it can be implemented and verified on the development board. The operation of the circuit is monitored by webcams that show the status of the LED indicators, and display devices on the development boards. Instead of setting the switches and buttons manually, the in-system sources and probes provided by the Quartus tools are used. The designed circuit models are stored by uploading to the cloud (2.2). For each student, an account is generated within a classroom group. The teacher can demonstrate circuit model examples on developing boards, and has full access to the current student’s work through cloud storage insight. The essential part of the online laboratory is our developed SHDL tool (2.1).

(3) Communication. In particular, two online communication tools have been introduced for educational purposes—MS Teams and Zoom—which are available free of charge for educational purposes, in truncated versions. We chose the latter for giving the course lectures and in all the cases of additional instructions to, and guidance for, students, whether individually, by group, or for the whole class.

4.2. Introductory Examples

We introduce SHDL language on a set of example circuit models, starting with combinational building blocks. The modeling concepts are presented on several SHDL models of the same circuit, and the corresponding VHDL model. The presented examples can be used as a tutorial in a DESD online teaching model: here, digital circuit design code examples are presented, whereas for the online teaching model, additional textual e-learning material for code examples explanation/instructions and/or video instructions were prepared.

Binary decoder is a combinational circuit used for setting an active output bit based on the address input. Listing 1 presents binary decoder models with 2-bit input address and 4-bit output. The circuit model uses a constant table with a decoding pattern. The constants are set at declaration (SHDL line 3).

The table declaration in VHDL requires two statements: a new data type and a declaration with an assignment of initial values (lines 6–7). If the index for accessing the table is an unsigned vector, a type transformation to integer should be used.

Listing 1. Binary decoder: (a) SHDL; (b) generated VHDL (only entity is presented).

(a)		(b)
1	entity bindec2	1	entity bindec2 is
2	a: in u2;	2	port (a: in unsigned(1 downto 0);
3	y: out u4;	3	y: out unsigned(3 downto 0));
4	table: 4u4 = 1,2,4,8;	4	end bindec2;
5	begin	5	architecture RTL of bindec2 is
6	y = table(a)	6	type table_type is array (0 to 3) of unsigned(3 downto 0);
7	end	7	constant table : table_type := (“0001”, “0010”, “0100”, “1000”);
		8	begin
		9	y <= table(to_integer(a));
		10	end RTL;

Listing 1. Binary decoder: (a) SHDL; (b) generated VHDL (only entity is presented).

(a)		(b)
1	entity bindec2	1	entity bindec2 is
2	a: in u2;	2	port (a: in unsigned(1 downto 0);
3	y: out u4;	3	y: out unsigned(3 downto 0));
4	table: 4u4 = 1,2,4,8;	4	end bindec2;
5	begin	5	architecture RTL of bindec2 is
6	y = table(a)	6	type table_type is array (0 to 3) of unsigned(3 downto 0);
7	end	7	constant table : table_type := (“0001”, “0010”, “0100”, “1000”);
		8	begin
		9	y <= table(to_integer(a));
		10	end RTL;

Listing 2 presents constant declaration and binary expression, using logical shift operators to describe the same decoder.

Listing 2. Binary decoder described with constant and logic shift expression.

1	c: u4 = “0001”;	1	constant c: unsigned(3 downto 0) := “0001”;
2	y = c sll a	2	y <= shift_left(c, to_integer(a));

Listing 2. Binary decoder described with constant and logic shift expression.

1	c: u4 = “0001”;	1	constant c: unsigned(3 downto 0) := “0001”;
2	y = c sll a	2	y <= shift_left(c, to_integer(a));

A priority encoder has the inverse function of a binary decoder. Listing 3 presents a 4-input priority encoder with code and valid output described with a sequence of conditional statements checking input bits. The if—else statement order defines priority in cases where more conditions are satisfied.

Listing 3. Priority encoder description in SHDL and generated VHDL process.

1	valid = 1	1	process(d)
2	if d(1)=1 then	2	begin
3	code = 1	3	valid <= ‘1’;
4	elsif d(0)=1 then	4	if d(1) = ‘1’ then
5	code = 0	5	code <= to_unsigned(1, 2);
6	else	6	elsif d(0) = ‘1’ then
7	code = 0	7	code <= to_unsigned(0, 2);
8	valid = 0	8	else
9	end	9	code <= to_unsigned(0, 2);
		10	valid <= ‘0’;
		11	end if;
		12	end process;

Listing 3. Priority encoder description in SHDL and generated VHDL process.

1	valid = 1	1	process(d)
2	if d(1)=1 then	2	begin
3	code = 1	3	valid <= ‘1’;
4	elsif d(0)=1 then	4	if d(1) = ‘1’ then
5	code = 0	5	code <= to_unsigned(1, 2);
6	else	6	elsif d(0) = ‘1’ then
7	code = 0	7	code <= to_unsigned(0, 2);
8	valid = 0	8	else
9	end	9	code <= to_unsigned(0, 2);
		10	valid <= ‘0’;
		11	end if;
		12	end process;

The multiplexer circuit model is described by indexing an input vector. By adding input enable, various options of the combinational circuit description can be described with if statements. The model contains an if–else (Listing 4a) or an assignment and one if statement (Listing 4b,c). The order of the statements is important: the circuit will not work correctly if we change it.

Listing 4. Three SHDL models of a multiplexer with enable input: (a) if-else description; (b) and (c) assignment and one if statement.

	(a)		(b)		(c)
1	entity mux	1	entity mux	1	entity mux
2	data: in u8	2	data: in u8	2	data: in u8
3	en: in u1	3	en: in u1	3	en: in u1
4	sel: in u3	4	sel: in u3;	4	sel: in u3;
5	z: out u1	5	z: out u1;	5	z: out u1;
6	begin	6	begin	6	begin
7	if en then	7	z = data(sel)	7	z = 0
8	z = data(sel)	8	if en=0 then	8	if en then
9	else	9	z = 0	9	z = data(sel)
10	z = 0 end	10	end	10	end
11	end		end		end

Listing 4. Three SHDL models of a multiplexer with enable input: (a) if-else description; (b) and (c) assignment and one if statement.

	(a)		(b)		(c)
1	entity mux	1	entity mux	1	entity mux
2	data: in u8	2	data: in u8	2	data: in u8
3	en: in u1	3	en: in u1	3	en: in u1
4	sel: in u3	4	sel: in u3;	4	sel: in u3;
5	z: out u1	5	z: out u1;	5	z: out u1;
6	begin	6	begin	6	begin
7	if en then	7	z = data(sel)	7	z = 0
8	z = data(sel)	8	if en=0 then	8	if en then
9	else	9	z = 0	9	z = data(sel)
10	z = 0 end	10	end	10	end
11	end		end		end

We can further elaborate the example, and add an input which sets output to 1, regardless of selection. A fully specified if–else statement (Listing 5a) overwrites the previously assigned value producing wrong behavior. The correct models are obtained by changing the statements order or by using if–else conditions (Listing 5b).

The generated combinational VHDL process contains a list of input signals (Listing 5c, line 1), which should be fully specified to obtain correct model simulation.

Listing 5. Multiplexer with set and enable: (a) wrong; (b) correct SHDL; (c) VDHL process.

(a) SHDL—wrong		(b) SHDL		(c) VHDL
1	if set then	1	if set then	1	process(set,en,data)
2	z = 1	2	z = 1	2	begin
3	end	3	elsif en then	3	if set = ‘1’ then
4	if en then	4	z = data(sel)	4	z <= ‘1’;
5	z = data(sel)	5	else	5	elsif en = ‘1’ then
6	else	6	z = 0 end	6	z <= data(to_integer(sel));
7	z = 0 end	7	end	7	else
8	end	8		8	z <= ‘0’;
9		9		9	end if;
10		10		10	end process;

Listing 5. Multiplexer with set and enable: (a) wrong; (b) correct SHDL; (c) VDHL process.

(a) SHDL—wrong		(b) SHDL		(c) VHDL
1	if set then	1	if set then	1	process(set,en,data)
2	z = 1	2	z = 1	2	begin
3	end	3	elsif en then	3	if set = ‘1’ then
4	if en then	4	z = data(sel)	4	z <= ‘1’;
5	z = data(sel)	5	else	5	elsif en = ‘1’ then
6	else	6	z = 0 end	6	z <= data(to_integer(sel));
7	z = 0 end	7	end	7	else
8	end	8		8	z <= ‘0’;
9		9		9	end if;
10		10		10	end process;

The SHDL supports modeling of synchronous sequential circuits with all flip-flops triggered on the rising edge of the system clock. This is not a big limitation for an educational language. Even in VHDL, we encourage students to design synchronous models of digital system components that avoid potential timing problems.

Synchronous logic is modeled implicitly in SHDL by using the assignment operator <=. A flip-flop or register is described with a simple statement: q <= d. With multiple flip-flops we can build shift register models. The 4-bit parallel-input serial-output shift register in Listing 6a loads input vector d into internal signal q when the load is active, and performs bit shifting when the load is zero. The bit shifting statements order is not important, because each statement describes one flip-flop. The expressions can be replaced by one statement, with concatenation operator q <= 0 & q (3 down to 1);

Listing 6b presents a general shift register model with parallel or serial input and serial output. Note the usage of the combinational assignment for the serial output SOUT. With the sequential assignment operator, we would introduce additional unnecessary flip-flop to the output logic. Listing 6c presents the corresponding VHDL architecture of the shift register, containing a process with explicit clock rising edge condition.

Listing 6. (a) and (b) shift register models in SHDL; (c) corresponding VHDL architecture.

(a)		(b)		(c)
1	if load then	1	if load then	1	architecture RTL of shiftreg2 is
2	q <= d;	2	q <= d;	2	signal q: unsigned(3 downto 0): = “0000”;
3	else	3	else	3	begin
4	q(0) <= q(1);	4	q <= sin & q(3 downto 1)	4	process(clk)
5	q(1) <= q(2);	5	end	5	begin
6	q(2) <= q(3);	6	sout = q(0)	6	if rising_edge(clk) then
7	q(3) <= 0;			7	if load = ‘1’ then
8	end			8	q <= d;
9	sout = q(0)			9	else
				10	q <= sin & q(3 downto 1);
				11	end if;
				12	end if;
				13	end process;
				14	sout <= q(0);
				15	end RTL;

Listing 6. (a) and (b) shift register models in SHDL; (c) corresponding VHDL architecture.

(a)		(b)		(c)
1	if load then	1	if load then	1	architecture RTL of shiftreg2 is
2	q <= d;	2	q <= d;	2	signal q: unsigned(3 downto 0): = “0000”;
3	else	3	else	3	begin
4	q(0) <= q(1);	4	q <= sin & q(3 downto 1)	4	process(clk)
5	q(1) <= q(2);	5	end	5	begin
6	q(2) <= q(3);	6	sout = q(0)	6	if rising_edge(clk) then
7	q(3) <= 0;			7	if load = ‘1’ then
8	end			8	q <= d;
9	sout = q(0)			9	else
				10	q <= sin & q(3 downto 1);
				11	end if;
				12	end if;
				13	end process;
				14	sout <= q(0);
				15	end RTL;

4.3. Online Teaching Model Exercises Activities Delivery

DESD is a 15-week course with 2 h lessons and 2 h laboratory practice per week. The course covers the topics of digital systems technology, programmable devices, RTL digital circuit description, partitioning to control logic and datapath, and the following intellectual propriety (IP) components: processors; memory; communication units; hardware and software partitioning; design cycle with design automation tools; prototyping implementation; and system design examples. The intended learning outcomes of the course are that student will be able to:

• use logic building blocks in digital systems;
• understand digital system components, HW/SW task division, and design process;
• implement and analyze digital HDL models on RTL, behavioral, and structural levels;
• write an HDL model of a simple CPU, following the specifications, and produce test assembly code;
• develop a small digital system implemented by a programmable device.

The initial DESD course assumption is that students are familiar with the basic concepts of digital logic and microprocessors. The course begins with the presentation of the digital circuits design cycle, associated languages, and tools. We explain basic modeling principles on the register–transfer level of abstraction, which are independent of the modeling language. HDL modeling is demonstrated on a set of example circuit models describing basic combinational and sequential digital circuits. The HDL concepts are taught by presenting several models of the same circuit. We use an SHDL tutorial to emphasize the modeling principles, and to discuss the VHDL syntax.

Students who are already familiar with the VHDL repeat the subject, and are advised to use the provided examples and generated models from the web tool, to adapt the prescribed synthesizable coding style. Students without previous VHDL knowledge begin with the SHDL and the web tool, enabling them to comprehend the subject and follow laboratory practice.

The DESD course laboratory exercises include basic logic modeling, advanced system-level components, a small CPU project, a digital system based on the FPGA, and individual projects, as presented in

Table 2. DESD laboratory exercises.

Exercise Topic	Knowledge	Laboratory Lessons
1. Combinational	HDL design flow	2
a. select, sort	dataflow model
b. multiply, ALU	testbench, symbolic
2. Sequential		2
a. LFSR	sequential HDL
b. running lights	counter-usage
c. FSM	symbolic HDL
3. Components		2
a. NCO	structural HDL
b. microsequencer	RTL design
4. Mini-project		2
a. basic CPU	cycle accurate RTL
b. upgraded CPU	design an IP
5. Digital system		3–4
a. CPU IP	re-use existing IP
b. interface	state machines
c. display units	system timing
6. Project	develop FPGA-based digital system	3–4

. The exercise assignments range from simple, fully guided, to autonomous projects.

Initial exercises have detailed instructions regarding design flow and circuit modeling, which can be completed in SHDL or in VHDL, depending on the student’s existing skills. The CPU project has exact specifications, but students must derive the circuit model, which is able to execute the provided machine code. For the final digital systems project, the students should contribute the specification, design the system, present the operation, and justify the design decisions. The laboratory exercises are divided into 14–16 practical 2 h lessons.

The laboratory exercises begin with a selection of small combinational and sequential digital circuits. The introductory exercises gradually introduce HDL design flow and modelling principles, starting with declarations and dataflow assignments. A combinational introductory exercise is a selector of maximum and minimum values from the input vectors. The circuit is trivial for two input vectors, but has a variety of solutions for more than two inputs. The circuit is finally extended to a combinational sorting network. Students learn how to properly describe combinational circuits, to avoid latches, and to optimize and test the circuit. Testing the sorting network with simulation is not trivial, and the designers can benefit from easy-simulation setup in the web tool.

The arithmetic combinational circuits are adders, subtractors and multipliers, which can be combined into an arithmetic and logic unit (ALU). The ALU implements several operations on two vector inputs, and provides additional carry and zero flag outputs. Students learn modeling subtraction and addition with carry, saving results to internal signals for output flags and usage of symbolic identifiers.

The initial sequential exercises are models of flip-flops, registers and shift-registers. The model simulation is used to observe circuit states and the effects of the conditional statements sequence for reset and state transition enabling. The students design a pseudo-random numbers generator with linear-feedback shift register (LFSR). The synchronous counter is another sequential component used as a circular state machine or clock divider. Counters and a combinational state decoder are used in a running lights exercise. The basic register and counter are described with one SHDL code line, enabling students to effectively experiment with circuits consisting of multiple sequential components and conditions. The design of a finite state machine (FSM) for synchronous counting of a key press concludes the basic sequential exercises. The students learn the symbolic HDL description of a state transition diagram. The exercise is used to discuss sequential circuit timing and synchronization requirements.

In the next set of exercises, the students design IP digital system components: a digital signal generator; a digital sequence generator; and a small central processing unit (CPU). The signal generator is a numerically controlled oscillator (NCO), composed of a phase accumulating counter, a sine memory and an amplitude scaler. The NCO model is described by structural HDL, including read-only memory (ROM) with quantized sine wave values. The exercise can be upgraded to use quarter sine wave ROM for area optimization and saturation logic in the amplitude scaler. The microsequencer is an RTL design with combinational logic in a closed loop with the sequential counter. The correct operation of the closed loop is obtained only when the clock cycle timing of all signals is respected, which requires careful HDL combinational and sequential modeling.

4.3.1. Mini-Project

For the mini-project exercise, the students develop a small one-address CPU, consisting of program memory, program counter, state machine, ALU and registers. The memory has 12-bit words divided into a 4-bit instruction code and an 8-bit address. The state machine switches between instruction fetch and execution cycles. An initial model of the CPU, shown in Listing 7, can execute four instructions: Load Data (LDA); Store Data (STA); Add to Accumulator (ADD); and Jump (JMP). The first CPU model contains less than 50 lines of SHDL code, and is simulated using our SHDL tool.

Listing 7. Initial CPU model, with four instructions and program memory in SHDL.

1	entity micro	31	entity program
2	reset: in u1	32	adr: in u8
3	acum: out u12	33	data: out u12
4	st: (fetch, exec)	34	we: in u1
5	adr, adr1, pc: u8;	35	din: in u12
6	we:  u1;	36	rom: 16u12 = x”104”, -- LDA 05
7	data: u12;	37	x”805”, -- ADD 06
8	inst: u4;	38	x”204”, -- STA 05
9	LDA: u4=1; STA: u4=2; JMP: u4=4; ADD: u4=8	39	x”400”, -- JMP 01
10	begin	40	x”003”,
11	adr = adr1 when st=exec else pc	41	x”001”;
12	we = 1 when st=exec and inst=STA else 0	42	begin
13	program(adr, data, we, acum)	43	data=rom(adr);
14		44	if we then
15	if st=fetch and reset=0 then	45	rom(adr)<=din
16	st <= exec	46	end
17	pc <= pc + 1	47	end
18	adr1 <= data(7 downto 0)
19	inst <= data(11 downto 8)
20	else
21	st <= fetch
22	if inst=LDA then
23	acum <= data;
24	elsif inst=JMP then
25	pc <= adr1
26	elsif inst=ADD then
27	acum <= acum + data;
28	end
29	end
30	end

Listing 7. Initial CPU model, with four instructions and program memory in SHDL.

1	entity micro	31	entity program
2	reset: in u1	32	adr: in u8
3	acum: out u12	33	data: out u12
4	st: (fetch, exec)	34	we: in u1
5	adr, adr1, pc: u8;	35	din: in u12
6	we:  u1;	36	rom: 16u12 = x”104”, -- LDA 05
7	data: u12;	37	x”805”, -- ADD 06
8	inst: u4;	38	x”204”, -- STA 05
9	LDA: u4=1; STA: u4=2; JMP: u4=4; ADD: u4=8	39	x”400”, -- JMP 01
10	begin	40	x”003”,
11	adr = adr1 when st=exec else pc	41	x”001”;
12	we = 1 when st=exec and inst=STA else 0	42	begin
13	program(adr, data, we, acum)	43	data=rom(adr);
14		44	if we then
15	if st=fetch and reset=0 then	45	rom(adr)<=din
16	st <= exec	46	end
17	pc <= pc + 1	47	end
18	adr1 <= data(7 downto 0)
19	inst <= data(11 downto 8)
20	else
21	st <= fetch
22	if inst=LDA then
23	acum <= data;
24	elsif inst=JMP then
25	pc <= adr1
26	elsif inst=ADD then
27	acum <= acum + data;
28	end
29	end
30	end

The CPU instructions are specially designed for easy decoding of machine code in hexadecimal format: for example, a machine instruction x “104” consists of the instruction code “1” (LDA) and the operand address “04”. The instruction codes are 4-bit constants, and the educational CPU has up to 16 different instructions. The students are asked to add input and output ports and the corresponding CPU instructions; they extend the model with arithmetic, shift, logic instructions, and conditional jumps.

An online assembler and simulator are provided for students to test the operation of the educational CPU [40], and to generate machine code. The extended CPU model should be verified with a test machine code program. The online tools allow students to design and test their version of the educational CPU at home.

Later digital system laboratory exercises are based on the 16-bit version of the CPU educational system, with 4k words of memory provided as part of the intellectual property (IP). The processor includes debugging circuitry to facilitate testing on the FPGA prototyping board. The students design various digital system components: keyboard and encoder interfaces; display matrix; or VGA controller.

4.3.2. Final Project

The final course project is the design of a digital system containing an educational processor, application-specific logic and board interfaces. The provided digital system components presented in Figure 6 are hierarchically organized (e.g., the processor is composed of CPU, memory and debugger components), and the final system is expected to follow hierarchy and modularity recommendations.

After selecting their final project theme, the students develop a specification, describe and simulate application-specific logic, compose a digital system in VHDL, write CPU software, and verify operation on the FPGA boards. Examples of student projects are:

• animation or simple electronic game on VGA monitor or graphical matrix display;
• electronic music instrument playing notes from keyboard or saved music;
• digital function generator with pulse-width modulated output.

Students should make design space exploration, to determine the best partitioning of the proposed application tasks into hardware and software. The provided educational CPU with a small instruction set handles the system setup and user interface tasks. The developed hardware components are used for peripheral units and for timing critical parts of the system. We provide only guidelines for the final project, and the students should autonomously develop a digital system, write a report, and demonstrate operation in 3–4 laboratory lessons.

5. DESD Online Teaching Model Evaluation and Discussion

In the 2020/2021 academic year, we delivered the DESD course, using the proposed online teaching model, as described in Section 4. To further improve the suitability of SHDL and laboratory exercises, we conducted a study using a descriptive method and a quasi-experimental research design. The sample was selected purposively: it consisted of 3rd year undergraduate students, aged 22–23 years, enrolled in the elective DESD course. The research focused on measuring the students’ cognitive knowledge as an outcome of the DESD course, related to the SHDL web tool. The study design included a control group and a treatment group. Both groups received the DESD course using the online teaching model, while the control group used the online lab without the SHDL web tool. A quantitative and qualitative mixed-methods research approach was used for the analysis. A pre-knowledge test and a final test were used as instruments to measure knowledge, while a mini-project and a final project report were used as task instruments for data collection. Only basic statistics were used for quantitative description. The following are details of the methodology.

Method

The method was as follows. Before the first exercise topic in the DESD Laboratory course, Table 1, students answered a prior-knowledge test (I). In order to address SHDL application possibilities for teaching purposes, all enrolled students were divided into two groups: the treatment group (A) and the control group (B). The treatment group included the use of SHDL along with VHDL to design digital components. The control group used only VHDL for circuit design. At the end of the laboratory exercises, all the students solved the final test (II), and submitted mini-project (III) and final project reports (IV). The method for grading the mini-project and final project was presented to the students in advance.

(I) The prior-knowledge test was used to assess pre-knowledge of the different tracks in which the students could enroll. The students in the electronics track had covered these topics in previous subjects, while the students in the other track had only partially covered them. The purpose of the test was to find out whether the laboratory exercise topics were adequate for their prior knowledge. The test consisted of four multiple-choice questions (Q1–4) and one short-answer question (Q5) on the topics of digital circuits and VHDL language. According to the revised Bloom’s Taxonomy levels, they could be classified as Q1 (2A), Q2 (2B), Q3 (3A), Q4 (4A) and Q5 (4B), with the process dimension labeled 1–6 and the knowledge dimension labeled A–D [41].

(II) The final test assessed knowledge about HDL. It consisted of the following nine tasks (Q6–Q14): match the HDL structures best used to describe the different digital multiplexers (Q6 (2B)); understand concurrent statements: two assignments to the same signal (Q7 (4B)); understand block statements: sequence of conditional statements with the default assignment (Q8 (2C)); complete the HDL model of the modulus counter model (define the condition and reset assignment) (Q9 (3C)); analyze the vector adder with carry (select correct HDL statements) (Q10 (4B)); find feedback loops in the HDL model sections (Q11 (4B)); HDL code section analysis—determine inputs (Q12 (4B)); find statements that describe specified shift operation (Q13 (4B)); HDL code section analysis—determine registers (14 (3C)).

(III) Mini-project. The mini-project was used to assess student progress in the DESD course halfway through the semester. The students were required to independently complete two lessons on the design of a small central processing unit. The mini-project report evaluation consisted of two assessment criteria (C₁, C₂). C₁ evaluated the number of CPU proposed instruction extensions, and the set completeness. At least one complete instruction set was mandatory, and the maximum was three (scores: 1 to 3). C₂ evaluated the complexity of the CPU architecture extension. The CPU architecture was verified by simulation with the student assembly code (score: 1—simple—to 5—very complex).

(IV) Final project. The final project of the course involved the design of digital systems. Each student chose a topic for the final project, and set initial specifications. We helped the students, by suggesting topics that were graded (grade 1–4) according to the given study examples. The lower-level topics used the CPU for simple animations on the output display, while the higher-level topics included multiple peripheral units from the exercise examples and innovative design components. The tiered topics helped the students to select the correct difficulty level for the final project, considering their digital design skills, and were not part of the final project assessment. The system design for the selected topic was divided into two parts: the hardware components for signal processing (the datapath part), and the software CPU (the control part). The hardware components were designed in VHDL or in SHDL for the treatment group. The assessment of the final projects considered several digital systems’ characteristic design aspects: modularity; datapath; and controller [9]. The modularity assessment (MD) determined how modular and hierarchical the design was, and whether modular components were reusable and verified (levels 1 (low level)–10 (high level)). A low level of modularity resulted in a longer sequence of statements to perform the given algorithm task, implying an inappropriate decomposition of the digital system components, which would lead to difficulties in detecting and correcting system errors. A high degree of modularity meant that the system was properly decomposed, and that the components could be tested separately. The students’ topics provided the previous hierarchical digital systems required for the 4th grade. The datapath assessment (DP) analyzed each student’s digital system block diagram presentation. The datapath was given a score of 5–10: for a grade of 5, the presence of a block diagram in the final project report was mandatory, without explanation; grade 6 for the datapath included an explanation of the input and output signals; higher grades were reserved for adequate representation and explanation of data flow, parallelism or pipeline usage. The Controller assessment (CO) evaluated the student’s ability to justify the tasks assigned to SW, and to explain the HW/SW task partitioning and synchronization: it was scored 5–10, with a score of 5 representing working control software with the lowest level of justification. The students could submit their final project if they demonstrated the operation of a digital system.

6. Results

The results are presented separately for each category (I–IV).

(I) The prior-knowledge test was administered online, and was not mandatory. The questions were asked sequentially in random order, and the possible answers were randomly shuffled. The students had 15 min to answer the questions. The results are shown for 26 students, 19 of whom were from the EL study track, and 7 of whom were from other tracks (Figure 7). Questions Q1, Q2 and Q4 were scored 0% if incorrect and 20% if correct. Question Q3 had two correct answers, with the better one scored at 20% and the other at 10%. Question Q5 had five sub-questions, each contributing 4% to the total score of 100%.

The students who participated in the test scored an average of 27.5%. Some of the enrolled students had some basic understanding of HDL, but they still needed to improve their knowledge, to be able to design digital components and systems. The greatest area of knowledge was the procedural knowledge dimension of the applied cognitive process, at 55.8% (Q3). Higher knowledge in analyzing cognitive processes (Q4 and Q5) was greater than lower processes of remembering and understanding (Q1 and Q2). The EL study track average knowledge was the highest, at 31.2%, and was almost twice as high as the Other study tracks score. The logic delay of an arithmetic operator in HDL was understood by 19.2% of all students; 11.5% understood the logic optimization in the case of a constant value shift operation; 55.8% of the students understood the use of FPGA blocks for synchronous counters; 23.1% of students correctly responded to sample HDL statements execution; and 27.7% of students partially responded to the analysis of the HDL snippet model: they determined all inputs, outputs or vector signals, registers, and memory (no response was completely correct).

(II) There were 34 students enrolled in the DESD course during the 2020/2021 academic year. The final test was mandatory for all students. There were 18 students in the treatment group (A), and 16 in the control group (B). Group A comprised 61% students from the EL study track, and 39% from the other tracks. Group B was the control group, comprising 87.5% electronics students and 12.5% from the other tracks. The results for the final test are presented in Figure 8, and are tagged according to the revised Bloom taxonomy (the process dimension is tagged 1–6, and the knowledge dimension, A–D).

Group A students scored an average of 64.5%, while EL study track students scored an average of 5% lower than students from other tracks. Students from group B scored 68.1% on average in the final test. The average knowledge difference between group A and B was small and not significant, at 3.6%. The EL study track students from group B scored, on average, almost 9% higher than the students from the other tracks. The students from group B gained, on average, 3.7% more knowledge about HDL. We found that group A students scored, on average, 15.7% better on Q7(4B), 14.4% better on Q11(4B), and 22.4% better on Q14(3C), while group B students scored 21.5% better on Q8(2C), and 13.9% better on Q13(4B).

(III) Results of the mini-project. Figure 9 shows the results of the evaluation of the mini-project reports. For both criteria, C1 and C2, treatment group A scored higher, on average. For criterion C1, the students in group A fully executed an average of 1.94 out of a total of three of the proposed CPU instruction set extensions, while the students in group B executed an average of only 1.56 instruction sets. For C2, treatment group A showed an average 8.3% higher level of CPU architecture extension complexity in the mini-project. In both groups, A and B, the EL study track students executed more CPU proposed instruction extensions on average (C1) than did the students in the Other study tracks.

(IV) Final project results. Figure 10 shows the results of the final project report assessment. The students in both groups—the treatment group A (1.72) and the control group B (1.81)—selected, on average, moderately graded subjects that used the CPU for simple animations on the output display. While the difference in average-scored topics was only 2.5%, it should be noted that in groups A and B, students from the Other study tracks chose higher-scored topics on average than did the EL study track students. The topics included several peripheral units from the exercise examples and innovative design components. This finding is significant, because the students from the Other study tracks were the ones with the least prior knowledge. Both groups, the treatment and the control groups, scored almost the same on average (77%) in the total sum of MD, DP and CO. In both groups, the students scored highest on DP and CO (about 80% to 90%) while they scored a much lower average on MD, of about 60%. Four students designed innovatively: they represented 22%/25% of all students in the A/B group, while students from both groups chose mostly online design solutions, on average. Group A was 10% better on average DP (more parallelism), while group B was 2.7% better on average MD (better modularity), and 5% better on average CO (better rationale). In the group A EL study track, the average score CO was almost 13% better than from the Other study tracks (in group B, there were only two students from the Other study tracks). Group A’s EL study track scored about 10% better than the EL study track from group B.

7. Discussion

Prior to the introduction of SHDL, we spent a lot of time in the laboratory advising students on how to use the tools, and helping them with VHDL design issues. As a result, we were not able to focus on the important design aspects. Most final projects did not adequately address modularity, data path optimization, and task partitioning. Application-specific logic was described in a few non-reusable components that were difficult to verify in the simulator. The description of datapaths and controllers was oriented toward modelling complexity rather than task partitioning and design space exploration.

Using the SHDL language and web tool, we have created many examples of digital circuits in the DESD laboratory that prepare students to explore their own designs. The example components can also be used as digital system modules, leading to better modularity of the final project. Students with sufficient prior VHDL knowledge were able to solve the examples in VHDL, while the others used SHDL.

The proposed online teaching model for the DESD course delivered in the 2020/2021 academic year was evaluated in terms of student cognitive knowledge. Although the test of prior knowledge was not mandatory, about three quarters of the enrolled students participated in the test. The results show that the students from the EL study track had higher prior knowledge (about 44%) compared to the other tracks in both groups, i.e., treatment and control group. In the middle of the DESD laboratory exercises, the treatment group using the SHDL tool showed higher motivation for solving problems with digital systems, and higher orientation towards architectural complexity. At the end of the DESD laboratory exercises, difference in prior knowledge between the students in the EL study track and the other students was no longer present, as shown by the final test results. The same results were obtained in the final project results.

SHDL is used for modeling the low-complexity, synchronous digital circuit components used in teaching examples, but has limitations when considering hierarchical and generic models. The main advantage of using SHDL is the fast modeling process and the readable output that can be used for further development in VHDL.

The online tool has limitations in simulation compared to VHDL tools, but the test bench output can be used to quickly switch from the SHDL to the VHDL simulator. The simplicity of modeling and simulation that the SHDL tool provides is important for undergraduate e-learning.

8. Conclusions

We implemented the presented online teaching model during the COVID-19 lockdown, using the SHDL web tool as a key component. The simplified design process is especially important for students taking our course without prior HDL experience. The proposed teaching method allows more experiments to be conducted in the limited time frame of a laboratory class, and can be used as a key tool for e-learning the hardware description language.

The stimulating results support the further development of SHDL and Its use as a promising tool for traditional and online teaching purposes. By using the SHDL tool, a student who is not yet familiar with VHDL syntax can create more complex digital system components in less time, with greater success and independence. When using the proposed language, there are fewer syntax, simulation, and synthesis issues, and students can focus on important digital modeling concepts. In addition, SHDL has demonstrated the ability to overcome various prior knowledge issues, and to improve students’ HDL learning. Students can use our e-learning tool to make up missed contact hours and do additional exercises.

We also identified the limitations of the current study, by considering other critical factors that affect the adoption of the presented e-learning system—particularly system quality, training and support. The quality of the SHDL tool output (generated VHDL, error reports) could be further improved, and additional training material should be pro-vided and evaluated. Our other goal is to improve student knowledge, motivation and self-learning in the DESD laboratory course, by providing authentic digital circuit problems, using contemporary learning methods, and the evaluating results on a larger scale.