Relative Jitter Measurement Methodology and Comparison of Clocking Resources Jitter in Artix 7 FPGA

Round 1

Reviewer 1 Report

Thank you for addressing jitter problem, and performing details testing.

Here are my impressions about the paper:

0. Just remark: Jitter problems are dominant at high frequences (several hundreds of MHz), proposed test works about 25MHz. At lower frequencies in FPGA design all jitter caused problems can be solved by better design of circuitry. Uncontrolled usage of combinatory logic might cause majority of problems, as well as clock ditribution skew (two simple principles prior to design anything in FPGA). This is the reason I have a serious doubt about the significance of methodology and experiments presented in this paper. In the other words: everything you presented probably is true, but I don't see any practical significance of it, in sense that all presented problems in this paper can be avoided by proper FPGA design. I might be wrong, so please see other questions and remarks

2. Figure 1. For what you use XOR output? A reader with some previous background can guess (line 78-79). Please note that placement in FPGA has huge influence on results. Thus, I give my respect you did manual placement 

3. Figure 5. Please elaborate clocking in this diagram. This is crucial and might explain some results

4. Line 190 - 191 Probably not different clock generator (how you have synchronized them in this case). Probably you have used different output of Si5351 chip. Besides, I can not see how TIE junction can contribute to the jitter, except it reduces signal amplitude (if properly sourced and terminated)

5. Initial verification you have used 1ps - please elaborate details, because sounds unrealistic (line 194-195)

6. Section 3.1. - Please elaborate input assumptions for presented calculation (datasheet,...)

7. Chapter 4.2. Temperature influence - My experience If something become wrong with temperature it will occur on fast transition from -5 to +5 degC (even -2 to +2). Extreme temperature (e.g. -40 degC or +65 degC) rarely cause the problems. Maybe some more detailed data should be given without so strict answer: temperature has no influence. Besides, in table 5. please specify exact temperatures (-0.5 deg C) or temperature transitions instead of words "freezing", "ambient",...

8. Section 5. Results i too long, and a reader loose attention while reading. Suggestion:

8.1. Make a table with all measured cases (b-part of Fig. 11, 12,...), and explain the differences with references

(e.g.

- someone who never programed Xilinx FPGA, but did Lattice, Altera,.. migh not know what is MMCM

- what is the reason for making configuration Fig 18. b (Comparison of TDL outputs from Fig 4 will sure have the differences.

8.2 Make one parametric graph, or 3D graph (a-part of Fig. 11, 12,...)

9. Fig 6. Please explain clocking of the register after XOR

10. Lines 821 - 834 please comment the meaning of the results

11. Lines 839-855 I am not surprised by results, maybe you had just good luck. Suggestion: please repeat the measurement on other chip or on other series of FPGA (e.g. Kintex, Virtex, of from other manufacturer). From this you may get the answer.

12. Please correct (Error! reference source not found errors)

13. Lines 927-930 for sure not true!!! Even if it is true for current measurement, next series of the same chip can perform differently.

14. Lines 932-933 Please see remark 11 (and 13)

15. From cited references (and also from some parts of the paper - please see previous comment), I see you are missing basic PLL/Jitter references/text books (before FPGA technology was invented). My recommendation:

  F. M. Gardner, Phaselock Techniques, 3rd edition, Wiley, 2005. (original 1st edition is from 1968)

and maybe

U. Mengali , A. N. D'Andrea A.N., Synchronization Techniques for Digital Receivers, Plenum Press, N.Y., 1997.

 

 

 

 

 

 

 

 

 

 

 

 

 

Author Response

Dear Sir or Madam,
We would like to thank you for your comments as well as insightful and positive review. Please find uploaded the second revision of the manuscript with changes and improvements recommended by the reviewers. According to your comments and suggestions we introduced the following changes and improvements (please note the changed line numbers):

0. The 20-25 MHz frequency range was selected for two reasons:
- the ITU-T: Recommendation O.172 defines the "short-term" variations as jitter and "long-term" variations as wander. The two categories are separated by the threshold frequency of 10 Hz.
- the idea for the experiments and the paper emerged from a different project, which provisional version was being tested in the 20-25 MHz range.
Additionally, the cited "Follow me" jitter measurement technique ([5]) mentions frequencies up to kHz range. The other cited jitter measurement technique based on FPGA ([7]) does not mention the value of tested signal frequency.

The mentioned other project involves phase and frequency manipulation of several clock signals, using FPGA clocking resources (with potential usage of non-clock capable input pins) and phase comparison using a modified version of the presented jitter measurement system. For this reason, the presented measurements provide additional information for the resource selection. We will write a specific paper describing the project, once it is finished.

2. In lines 79-84 we commented in more details the usage of XOR gates to compare the values captured in TDLs. The XOR output is equivalent to temporary input signals misalignment (assuming a signal transition is captured in both TDLs).

3. In lines 122-123 we added the information about submodules clocking. The Figure 5 diagram was also updated to include the clock signal.

4. In lines 193-200 we added a specific statement about using two outputs of a single Si5351 chip and rephrased the paragraph to be less ambiguous. We also added a note regarding a potential tee connector influence on the signal.

5. In lines 201-203 we provided more detail description regarding achieved delays match.

6. In lines 217-232 and in the Supplementary Materials we provided additional information regarding the effects contributing to calculation of actual absolute jitter or period jitter.

7. In lines 347-351 we provided the exact temperatures obtained during measurements. The temperature influence was verified in -4.9°C to -1.4°C and 21.4°C to 30.3°C temperature ranges. Unfortunately, we were unable to repeat the measurements in -5°C to 5°C due to limited time for paper revision. But the provided measurement in range from -4.9°C to -1.4°C is partially similar to a suggested temperature range.

8. According to your suggestion we changed the structure of the Section 5 (Results) and organized the measured cases in a table. as a result we reduced the length of the paper. Thank you for the suggestion 8.1. We also added a brief explanation of what the MMCM block is in line 158.

9. All registers in Fig. 6 are clocked using the same system clock signal. This detail was added to the caption below the Fig. 6.

10. In lines 552-558 we provided more detail comment regarding achieved results.

11. In lines 559-561 we added more information on why we found the results surprising i.e. the best results regardless if the input pin is clock capable of not. Unfortunately, we were unable to repeat the measurements using a different series of FPGA due to limited time for paper revision.

12. We must have overlooked the references errors. My apology. We fixed the errors.

13. In lines 656-661 we added additional comment on the results and added the information that the results may differ in a different chip.

14. In lines 663-665 we removed the controversial statement.

15. Thank you for the suggestion of an additional reference. We added the citation in line 214.

Yours faithfully,
Andrzej Wojciechowski

Reviewer 2 Report

The paper details a study centered about measuring jitter using different clocking resources available on a commericial FPGA. Generally speaking, the paper is too detailed especially in Section 5, Results and the reviewer suggests it may be beneficial to provide a the results in the form of a one line summary of the configuration and the corresponding figure. Overall the results seem to make sense as described in Section 6. Conclusions and the reviewer has no significant concerns. Only that the paper organization and length can be improved further for easy of the reader.

Author Response

Dear Sir or Madam,
We would like to thank you for your comments as well as insightful and very positive review. Please find uploaded the second revision of the manuscript with changes and improvements recommended by the reviewers. According to your suggestion we changed the structure of the Section 5 (Results) and, as a result, reduced the length of the paper.

Yours faithfully,
Andrzej Wojciechowski

Round 2

Reviewer 1 Report

Thank you for addressing all my questions and remarks, especially for lines 607-612 in conclusion. I have no further remarks and apart from this paper wish you all the best and a lot of interesting project in which you will use FPGA technology.