Digitalized Control Algorithm of Bridgeless Totem-Pole PFC with a Simple Control Structure Based on the Phase Angle

Abstract

Compared to the conventional boost power factor correction (PFC) converter, a totem-pole bridgeless PFC has high efficiency because it does not have an input diode rectifier stage, but a current spike may occur when the polarity of the grid voltage changes. This paper proposes a digital control algorithm for bridgeless totem-pole PFC with a simple control structure based on the phase angle of grid voltage. The proposed algorithm has a PI-based double-loop control structure and performs DC-link voltage and input inductor current control. Rectifying switches operate based on the proposed rectification algorithm using phase angle information calculated through a single-phase phase-locked loop (PLL) to prevent current spikes. The feed-forward duty ratio value is calculated according to the polarity of the grid voltage and added to the double-loop controller to perform appropriate power factor control. The performance and feasibility of the proposed control algorithm are verified through a 3 kW hardware prototype.

1. Introduction

In the power electronics field, power factor correction (PFC) converters are widely used in various industrial areas, such as network server power [1,2], electric vehicle chargers [3,4,5], and LED drivers [6,7,8]. Power conversion systems must meet harmonic regulations in international standards such as IEC 61000-3-2 [9]. Therefore, PFC converters have been essential for the power factor control of an AC grid and stable DC voltage supply.

In the modern power conversion industry, there has been a continuous need to achieve high efficiency converters [10,11,12]. Among the boost PFC topologies, there are various topologies such as single-switch boost PFC [13], semi-bridgeless PFC [14], and interleaved boost PFC [15]. These topologies essentially require diodes to rectify the grid voltage and, accordingly, bridge-less topologies that do not use diode bridges have been researched. Among them, the totem-pole bridge-less PFC (TBPFC) topology is proposed. TBPFC comprises two switches operating at high frequency, two operating slowly according to the grid voltage frequency, and one inductor as shown in Figure 1. In particular, it does not have a rectifier diode in the front end, and two low-speed switches are responsible for the rectification operation. Furthermore, it is operated through only two high-speed switches controlled by the main duty ratio. Therefore, TBPFC can achieve high efficiency due to low conduction and switching loss and high power density due to its simple circuit configuration [16,17,18].

The control system configuration of PFC is generally a two-loop system, with a voltage controller in the outer loop and a current controller in the inner loop. The control system usually uses proportional-integral (PI) control, and three main methods are mainly used for switching modulation: continuous conduction mode (CCM), discontinuous conduction mode (DCM), and critical conduction mode (CrM) control. In CCM control, the current continuously flows through the inductor at a fixed switching frequency and is controlled in a sinusoidal shape. This method has low peak values of current, resulting in low conduction losses, and the requirements for switches are also relatively small [19]. In DCM control, the inductor current is controlled discontinuously by repeatedly going back and forth between the current command and zero current. Due to this operation, zero voltage switching (ZVS) can be achieved, there is no reverse recovery of the diode, and the switching frequency can be changed depending on the phase [20]. In CrM control, the inductor current repeatedly goes back and forth between the current command and zero current, but the current is controlled continuously without a zero-current section. CrM control also has no losses due to the diode reverse recovery phenomenon. It can reduce the size of the inductor by doubling the ripple of the inductor current, thereby improving power density [21]. However, when operating DCM or CrM, it is difficult to apply to high-power applications due to high conduction loss. Accordingly, CCM control, which has a general purpose, is widely used for PFC control.

Various control methods have been proposed for the stable operation of TBPFC. In [22,23], a digital notch filter is applied to remove the 120 Hz component of sensed DC-link voltage, and in [24], the authors presented a 120 Hz reduction method of the input current by adding a notch filter between the voltage and the current controller. To reduce a zero-current spike current, a partial open-loop operation method is proposed [25,26]. This method operates high-frequency switches to a predefined duty ratio at rectification. In [27], a DC bus feed-forward and variable gain control method based on the DC-link voltage is proposed. A current control loop operates independently, with the DC-link voltage, from this control method. In [28], a model predictive current controller is proposed. An appropriate current shaping and ripple reduction is achieved by variable sampling time. In [29], a polarity detection algorithm based on the sensed grid voltage is proposed. The sensed current value is reversed when the grid voltage is in a negative cycle, to control positive and negative inductor current control. These conventional methods are relatively complicated to implement, so simplification is necessary.

In this paper, a digitalized control algorithm for TBPFC with a simple control structure that can minimize zero-current spikes is proposed. The proposed algorithm has a PI-based double-loop control structure and performs DC-link voltage and input inductor current control. In addition, control and rectification switch operation sequences are implemented through phase angle information of the grid voltage to prevent zero-current spikes without complicated sequences. The phase information of the grid voltage is extracted through a general single-phase phase-lock loop (PLL). Additionally, a feedforward technique is applied to reduce the output of closed-loop controllers. The feedforward duty value is used according to the polarity of the grid voltage and performs appropriate power factor control accordingly. The contents of this paper are as follows. Section 2 analyzes the operating principle of TBPFC. Section 3 covers the details of the proposed algorithm. Section 4 presents experimental results to verify the feasibility of the proposed algorithm. The performance of the proposed control algorithm is verified through a 3 kW hardware prototype.

2. Operation Principle of TBPFC

Figure 1 is a circuit diagram of TBPFC. Here, v_ac, i_L, v_dc, L, C_dc, and R_L mean grid voltage, inductor current, DC-link voltage, inductor, DC-link capacitor, and equivalent load resistance, respectively. Like a typical single-phase PFC circuit, an EMI filter removes high-frequency noise at the input stage. s₁ and s₂ are switches that operate at high switching frequencies and operate complementarily. s_r1 and s_r2 are rectifier switches that operate at a low switching frequency equal to the grid voltage frequency.

The current conduction path for each switching operation of TBPFC is shown in Figure 2. Figure 2a,b show the situation when v_ac is in a positive cycle with a positive voltage value. In this case, s_r1 must be fully turn-off, and s_r2 must be fully turn-on for rectifying operation. Figure 2a shows an operation mode where s₁ is turned on. In a rectifying situation where power is supplied from the AC side to the DC side, the current flow is like an arrow direction as presented and, accordingly, the inductor voltage (v_L) has a negative value, and the slope of i_L has a (−) value. The rectified current charges the DC-link capacitor and supplies power to the load. Figure 2b shows the situation where s₂ is turned on. Likewise, s_r2 is turned on, and as s₂ turns on, v_L has a positive value, so the slope of i_L becomes a (+) value. In this mode, the DC-link capacitor is discharged and supplies current to the load.

Figure 2c,d show situations when v_ac is in a negative cycle with negative voltage value, s_r1 is fully turned on, and s_r2 is fully turned off for the rectifying operation. Figure 2c shows an operation mode where s₁ turns on, v_L has a negative value, and the slope of the i_L has a (−) value. As in Figure 2b, the DC-link capacitor is discharged and supplies current to the load. Figure 2d shows a situation where s₂ is turned on and, accordingly, v_L has a positive value, and the slope of i_L has a (+) value. As in Figure 2a, the rectified current charges the DC-link capacitor and supplies current to the load.

A simple expression of the TBPFC according to the polarity of v_ac is shown in Figure 3. In the positive cycle corresponding to Figure 2a,b, s₂ has the same role as the main switch of a general bidirectional boost converter, as shown in Figure 3a. When the duty ratio of the switch is D, the voltage transfer ratio M(D) and D can be expressed as Equations (1) and (2).

$$M\left(D\right)=\frac{V_{out}}{V_{in}}=\frac{v_{dc}}{v_{ac}}=\frac{1}{1-D}$$

(1)

$$D=1-\frac{v_{ac}}{v_{dc}}.$$

(2)

Here, V_in is the input voltage and is equal to v_ac, and V_out is the output voltage and is equal to v_dc. The switching operation of s₂ in the positive cycle should be the same as Equation (2).

On the contrary, in the negative cycle corresponding to Figure 2c,d, s₁ has the same role as the main switch of the bidirectional boost converter, as shown in Figure 3b. Therefore, in the negative cycle, s₂ must operate with a complementary duty ratio ($\overline{D}$), as shown below:

$$M\left(D\right)=\frac{V_{out}}{V_{in}}=\frac{v_{dc}}{\left(-v_{ac}\right)}=\frac{1}{1-D}$$

(3)

$$D=1+\frac{v_{ac}}{v_{dc}}$$

(4)

$$\overline{D}=1-D=-\frac{v_{ac}}{v_{dc}}.$$

(5)

When a cycle changes from negative to positive, the duty ratio applied to s₂ should suddenly change from 0 to 1. Likewise, the duty ratio must change rapidly from 1 to 0 when changing from a positive to a negative cycle. According to the characteristics of these switching operations, switching operations and control sequences of TBPFC should be appropriately implemented for the rectification point when the polarity of the AC voltage changes.

3. Proposed Control Algorithm

The overall control block diagram of the TBPFC proposed in this paper is shown in Figure 4. First, continuous conduction mode (CCM) control is performed through a PI-based double-loop controller to control the DC-link voltage and inductor current. And the d-axis voltage (v_d) and q-axis voltage (v_q) are calculated from the grid voltage through alpha-beta to the DQ transformation. A general single-phase PLL is used to extract the phase information of the grid voltage. Finally, a rectifying switch algorithm is applied to minimize the zero-crossing current spike problem. Details for each control algorithm are as follows.

3.1. Digitalized Double Loop Controller

A double-loop control structure based on PI control is applied to simultaneously perform DC-link voltage control and power factor control on the AC input side. This control structure is implemented by a digitalized control environment within a predefined sampling time (generally the same as the switching period) in a microprocessor such as a digital signal processor (DSP). For this purpose, the PI controller and the low-pass filter must be converted from the continuous-time domain to the discrete-time domain through methods such as bilinear and backward, and the converted formula is implemented in a programming language such as C language. As a result, the control structure in Figure 4 is calculated based on the sensed data acquired by an analog-to-digital converter (ADC) interface, and the duty ratio is converted into a final switching signal through pulse-width modulation (PWM) to operate the TBPFC hardware.

The outer-loop controller is a DC-link voltage controller that performs PI control for the error between the DC-link voltage command (V_dc^cmd) and v_dc. K_iv and K_pv refer to the I gain and P gain of the voltage controller, respectively. A limiter and an anti-windup control structure are applied to avoid excessive accumulation of error in the integral term. The output of the DC-link voltage controller is the inductor current reference, which means the maximum value of the inductor current to be controlled. Therefore, the DC reference value (i_L^ref_dc) must be converted to the AC reference value (i_L^ref_ac). Additionally, to maintain the power factor as an almost unity value, the phase of v_ac must be reflected in i_L^ref_ac, which is expressed in Equation (4).

$$i_L^{ref\_AC}=i_L^{ref\_DC}\cdot \frac{v_{ac}}{Max\left(v_{ac}\right)}.$$

(6)

Here, Max(v_ac) means the maximum value of v_ac. The proposed algorithm uses the periodic average of the v_d[n] (sampled value of v_d) to minimize unnecessary fluctuations due to disturbances such as sensing noise in calculating Max(v_ac), as shown below.

$$Max\left(v_{ac}\right)=\frac{1}{N}{\displaystyle \sum _{n=1}^N{v}_d\left[n\right]}.$$

(7)

Here, N is the number of data for periodic average calculation and, in this paper, the sampling frequency is set to 10 kHz, and N is set to 10,000 to reflect the Max(v_ac) value every one second.

The inner-loop controller is an inductor current controller that performs PI control for the errors of i_L^ref_ac and i_L. K_ii, and K_pi refer to the I gain and P gain of the current controller, respectively. Due to the topological characteristics of TBPFC, the duty ratio must change suddenly at the zero-crossing point of v_ac, and this change is challenging to handle with the output of the PI controller. Therefore, the feed-forward duty ratio (d_ff), as shown in Equation (6), is added to the output of the current controller (d_con) to perform stable control.

$$d_{ff}=\{\begin{array}{l}1-\raisebox{1ex}{$v_{ac}$}\!\left/ \!\raisebox{-1ex}{$v_{dc}$}\right.,Positivecycleof{v}_{ac}\\ -\raisebox{1ex}{$v_{ac}$}\!\left/ \!\raisebox{-1ex}{$v_{dc}$}\right.,Negativecycleof{v}_{ac}\end{array}.$$

(8)

The relationship in Equation (6) is the same as that derived in Equations (2) and (3). The final duty ratio is output as s₁ and s₂ through PWM, and s_r1 and s_r2 operate according to the positive flag (F_Pos) and negative flag (F_Neg) of the rectifying switch algorithm, which will be described in Section 3.3.

3.2. Coordinate Transformation and PLL

The coordinate transformation used in the proposed algorithm is alpha-beta to DQ transformation, and v_d is used to calculate the maximum value of the grid voltage shown in Equation (5). v_q is used as an input variable of single-phase PLL. For coordinate transformation, an all-pass filter (APF) is used to make a 90° lagging voltage based on v_ac. The transfer function of APF, G_APF(s), is shown in Equation (7).

$$G_{APF}\left(s\right)=\frac{-s+{\omega }_c}{s+{\omega }_c}$$

(9)

$${\omega }_c=2\pi f_c.$$

(10)

Here, ω_c and f_c mean a cut-off angular frequency and a cut-off frequency, respectively, and f_c is set equal to the frequency of the grid voltage (f_ac). The alpha-axis voltage (v_α) is the same as v_ac, and the beta-axis voltage (v_β) is 90° lagging voltage through APF. The formulas for v_d and v_q calculated through coordinate transformation are as follows.

$$\left[\begin{array}{c}{v}_d\\ v_q\end{array}\right]=\left[\begin{array}{cc}\cos \theta & \sin \theta \\ -\sin \theta & \cos \theta \end{array}\right]\cdot \left[\begin{array}{c}{v}_{\alpha }\\ v_{\beta }\end{array}\right].$$

(11)

In single-phase PLL, phase angle information is extracted using the v_q value, and the angular frequency based on f_ac is added as a feed-forward term (ω_ff), as shown in Equation (10), assuming that the frequency variation of the grid voltage is slight.

$${\omega }_{ff}=2\pi f_{ac}.$$

(12)

3.3. PLL Rectifying Switch Algorithm

The rectifier switch of TBPFC must be appropriately turned on and off according to the polarity of the grid voltage. The simplest way to implement an on/off sequence of rectifying switches is to use the sensed value of grid voltage directly. Although it has the advantage of being easy to implement, it may operate inappropriately due to a sensing noise. Accordingly, the rectifying switches may operate at an unwanted time, resulting in a zero-crossing spike current. As another method, a partial open-loop operation method is proposed. This method operates high-speed switches to a predefined duty ratio at rectification timing. This method requires initializing the closed-loop controller when operating the open-loop sequence, and there is a problem—that the transient response is repeated when the closed-loop control is reactivated. In addition, the complexity of the overall control sequence increases.

The rectifying switch algorithm proposed in this paper turns the rectifying switch on and off through the grid voltage phase angle (θ) extracted through the PLL. Basically, θ has a value from −π to +π and is a value that increases at every sampling time, so it is relatively robust to noise compared to conventional algorithms that directly use sensed values. In addition, because accurate judgment of the commutation point can be made through simple conditioning, false turn-on-off of the rectifying switch can be eliminated. And because there is no complicated switching sequence, it is easy to implement. The operating principle of the proposed rectifying switch algorithm is shown in Figure 5.

If the grid voltage is based on the cosine term, the θ value where a zero crossing of v_ac occurs is approximately 0.5π and −0.5π. Therefore, turn-off all switches before and after θ reaches 0.5π. Similarly, in the section before and after θ becomes −0.5π, all switches are equally turned off to prevent a zero-crossing spike current. The area where all switches turn off is the same as the red color section in Figure 5. At this time, the voltage-current controller also stops calculating to prevent unnecessary values from accumulating in the integral term and causing the output not to fluctuate significantly.

When the grid voltage is in a positive cycle, F_Pos is set to 1, and at this time, s_r1 is turn-off, and s_r2 is turn-on. Conversely, during a negative cycle, F_Neg is set to 1; at this time, s_r1 is turned on, and s_r2 is turned off. The conditions for generating flag signals are as follows.

$$\begin{array}{l}{F}_{Pos}=1when\left(-\frac{\pi }{2}+\Delta \theta \right)\le \theta <\left(\frac{\pi }{2}-\Delta \theta \right)\\ F_{Neg}=1when\theta \ge \left(\frac{\pi }{2}+\Delta \theta \right)or\theta <\left(-\frac{\pi }{2}-\Delta \theta \right)\end{array}$$

(13)

$$\Delta \theta =2\pi f_{ac}\cdot T_{samp}\cdot N_{hys}$$

(14)

Here, ∆θ means the hysteresis band for phase angle, and T_samp is the sampling period time. N_hys is a value that determines the width of the hysteresis band, and in this paper, N_hys is set to one to minimize the rectification area. In other words, since all switches turn- off only for two sampling times, a spike current does not occur, and a high power factor can be maintained due to the short rectification period. F_Ctrl is a flag signal for driving the voltage-current controller, and when F_Pos or F_Neg is 1, F_Ctrl also becomes 1. There is no need to initialize the values in the digital controller because the calculations of controller are stopped for only a short period.

4. Realization and Experimental Results

4.1. Hardware Specifications

A photograph of the prototype for verifying the proposed TBPFC control algorithm is shown in Figure 6. The input side consists of a relay and a thermistor to charge the initial DC-link voltage. The switch legs in Figure 1 are constructed using MOSFET switches and heatsink. Three sensors are used for DC-link voltage control and PFC control: input voltage, inductor current, and DC-link voltage. A control board based on TI’s DSP (TMS320F28377D) is used to implement the proposed algorithm. The detailed design specifications of the hardware prototype are listed in

Table 1. Hardware specification of TBPFC.

Parameters	Symbol	Values
Rated power	P	3 kW
Input grid voltage	vac	90~120 Vrms
Output voltage	vdc	190~250 V
Inductance	L	1.3 mH
Capacitance	C	1.05 mF
Switching frequency	fsw	10 kHz
Sampling time	Tsamp	100 μs

. The gains of the PI controller are shown in

Table 2. PI gains of proposed algorithm.

Parameters	Symbol	Values
P gain of voltage controller	Kpv	0.08
I gain of voltage controller	Kiv	10.0
P gain of current controller	Kpi	0.02
I gain of current controller	Kii	5.0

.

4.2. Algorithm Implementation

Figure 7 shows a graph of the DC-link voltage profile that varies depending on the magnitude of the input grid voltage. TBPFC is a boost PFC, so it is possible to boost the output voltage compared to the input voltage. In this paper, we verify the variation and control of the output voltage by implementing a sequence that allows the DC-link voltage to be varied according to input conditions without additional firmware modification. Based on the input voltage, it is divided into sections at approximately five V_rms intervals from 90 V_rms to 120 V_rms, and the corresponding DC-link voltage is defined to vary from 190 V to 250 V at 10 V intervals.

Figure 8 shows a flow chart of the entire controller sequence of TBPFC, including the rectifying switch algorithm. First, PLL is performed based on the sensing information, and the phase angle is calculated. Based on the phase angle, rectifying switches and flag states are predefined before activating the closed-loop controller. When the switching starts operating from the turn-off to the switching state after passing the rectification area, the switching status of s_r1 and s_r2 must be predefined before s₁ and s₂ operate, thereby preventing zero-crossing spike currents. In this paper, for s_r1 and s_r2 switching, the DSP peripheral is set to GPIO rather than PWM settings to activate immediately during control operations without on-off delay. Next, calculate the periodic average value of the v_d and calculate Max(v_ac) shown in Equation (5). Additionally, as defined in Figure 7, the V_dc^cmd is determined according to v_ac. Likewise, to prevent unnecessary changes in DC-link voltage, a calculation sequence of V_dc^cmd is performed every one second. Next, DC-link voltage control is performed according to the defined V_dc^cmd, and inductor current control is performed according to the output current command of the voltage controller. Finally, the final duty ratio with the feed-forward term is calculated, and the switching status of s₁ and s₂ is determined through PWM.

4.3. Experimental Results

Figure 9 shows the initial start-up sequence to which the proposed algorithm is applied. First, before t₁, the DC-link voltage is charged through the initial charging resistance and relay, and the control algorithm is not applied. Afterward, control begins at t, and to prevent an excessive initial rise in DC-link voltage, V_dc^cmd is set to increase only +20 V to the voltage before applying control. The sequence shown in Figure 8 is then used to increase V_dc^cmd from t₂ to t₃. At this time, V_dc^cmd value follows the voltage profile shown in Figure 7. Additionally, to prevent a sudden increase in the V_dc^cmd value, a ramp-up function is used to output the command value. Through this, it takes a certain amount of time from t₂ to t₃ to reach the final command value, but excessive overshoot of voltage or current can be prevented.

Next, t₃ to t₄ show the operating waveform in a no-load situation. Although there is no load on the output, the inductor current has a ripple component due to the voltage difference between the input and output. At t₄, the output load increases to about 600 W, and the inductor current increases accordingly. Through this, it can be confirmed that the initial no-load control is smoothly performed and adequately controlled without a sizeable transient state when the load suddenly changes.

Figure 10 shows the experimental results applying the proposed TBPFC control algorithm. The experiment is performed according to the input and output voltage conditions shown in Table 1 and Figure 7, and v_ac, i_L, and v_dc waveforms are measured at the maximum load of 3 kW. Figure 10a shows the situation when the minimum input voltage (90 V_rms) is applied. V_dc^cmd at this time is 190 V, and it can be confirmed that DC-link voltage control is performed according to the command. Likewise, Figure 10b,c show situations when the input voltage is 100 V_rms and 110 V_rms, respectively, and it can be seen that DC-link voltage control is properly performed depending on the input voltage conditions. Figure 10d shows the situation when the maximum input voltage (120 V_rms) is applied and, at this time, V_dc^cmd is 250 V, so DC-link voltage control is properly performed. Due to the topology characteristics of single-phase PFC, a ripple component of 120 Hz is inevitably present in the DC-link voltage, so it can be confirmed that low-frequency voltage ripple exists in all waveforms. However, it can be confirmed through the waveform that the low-frequency voltage ripple does not affect current control.

From Figure 10, it can be seen that, when the input voltage is gradually increased under the equal load conditions, the inductor current gradually decreases. Additionally, it can be confirmed that i_L has the same phase as v_ac for all operating situations and that appropriate power factor control is performed. In addition, it can be confirmed that zero-crossing current spike does not occur in all experimental conditions, which proves the validity of the proposed rectifying switch algorithm.

5. Future Considerations

In this paper, a general single-phase PLL was used to calculate the phase angle. However, in environments where the frequency variation range is significant due to a weak grid or the size of the grid voltage varies frequently, advanced PLL techniques must be applied to extract appropriate phase angle information, even under adverse conditions. In the future, we plan to use advanced PLL methods to enhance the performance of the proposed algorithm. Additionally, if the capacitance of the DC-link capacitor reduced, the 120 Hz voltage ripple component increases, and PFC control performance may also be reduced accordingly. We plan to incorporate research into the proposed method to improve the performance of DC-link voltage control.

6. Conclusions

This paper proposed a digitized control algorithm for TBPFC with a simple control structure. The proposed algorithm consisted of a PI-based voltage and current controller, coordinate transformation and PLL, and a rectifying switch algorithm. The phase angle information of the grid voltage was used to implement overall control sequences to prevent current spikes at zero crossing. In the voltage and current controller, a feedforward term of duty ratio was applied for stable power factor control. A predefined voltage profile was implemented to change the command of DC-link voltage according to grid voltage. The performance of the proposed control algorithm was verified through a 3 kW hardware prototype. From the results of the experiment, the accurate performance of DC-link voltage and power factor control was verified.