Design of a 0.4 V, 8.43 ENOB, 5.29 nW, 2 kS/s SAR ADC for Implantable Devices
Abstract
:1. Introduction
2. SAR ADC Architecture
3. Implementation of Key CMOS Blocks
3.1. Proposed Bootstrap Switch
3.2. Dynamic Comparator
- Increasing the transistor sizes of the differential pair;
- Matched capacitors can be added at the output nodes to reduce the relative mismatch;
- Constant current can be generated into the output nodes.
3.3. Modified Distributed Attenuation Capacitor Split-Capacitive DAC
3.4. SAR Logic
4. Simulation Results of the Proposed ADC
4.1. Static Performance
4.2. Dynamic Performance
4.3. Power Performance
5. Conclusions
Author Contributions
Funding
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
References
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Mp1 | Mp2, Mp3 | Mn2, Mn3 | Mn4, Mn5 | Mn1 | |
---|---|---|---|---|---|
W (nm) | 120 | 240 | 120 | 1000 | 120 |
L (nm) | 45 | 45 | 45 | 45 | 45 |
S. No. | [33] | [21] | [32] | [31] | Proposed |
---|---|---|---|---|---|
Technology (nm) | 45 | 45 | 45 | 45 | 45 |
Supply Voltage (V) | 0.4 | 0.4 | 0.4 | 0.4 | 0.4 |
No. of Transistors | 12 | 17 | 13 | 23 | 8 |
Offset Voltage (mV) | 35.6 | 25 | 43 | 42 | 20 |
Kickback Noise (mV) | 3.37 | 2.99 | 2.5 | 1.3 | 2 |
Power (nW) | 6.77 | 4.6 | 1.97 | 10 | 1.07 |
Leakage power (W) | 384 p | 1.33 n | 1.04 n | 33.2 p | 51.4 p |
Delay (ns) | 15.14 | 6.75 | 5.15 | 15 | 7.16 |
Binary Code | Thermometer Code | |||
---|---|---|---|---|
D2 | D1 | T3 | T2 | T1 |
0 | 0 | 0 | 0 | 0 |
0 | 1 | 0 | 0 | 1 |
1 | 0 | 0 | 1 | 1 |
1 | 1 | 1 | 1 | 1 |
Binary Code | New Code | |||
---|---|---|---|---|
D2 | D1 | C3 | C2 | C1 |
0 | 0 | 0 | 0 | 0 |
0 | 1 | 1 | 0 | 0 |
1 | 0 | 0 | 1 | 1 |
1 | 1 | 1 | 1 | 1 |
Reference | Leakage Power (pW) |
---|---|
[36] | 56.08 |
[37] | 41.8 |
Modified | 38.4 |
Technology | 45 nm |
Power Supply | 0.4 V |
Reference Voltage | 0.2 V |
DAC Size | 620 fF |
SAR logic complexity | 271 transistors |
Unit Capacitor | 20 fF |
Input Range | [0, 0.4] V |
DNL | −0.10/+0.13 LSB |
INL | −0.8/+0.5 LSB |
ENOB | 8.43 bits @ 2 kS/s |
SNDR | 56.63 dB |
SFDR | 57.14 dB |
Power | 5.29 nW |
Leakage Power | 1.5 nW |
FOM | 7.66 fJ/conv.step @ 2 kS/s |
[25] 2016 | [27] 2015 | [28] 2019 | [29] 2006 | [30] 2012 | [33] 2010 | [31] 2020 | [38] 2022 | Proposed | |
---|---|---|---|---|---|---|---|---|---|
Technology (nm) | 180 | 90 | 40 | 40 | 180 | 65 | 180 | 180 | 45 |
Result | Sim. | Sim. | Fab. | Fab. | Fab. | Fab. | Fab. | Sim. | Sim. |
Resolution (bit) | 9 | 9 | 9 | 9 | 8 | 10 | 8 | 10 | 9 |
Supply (V) | 0.6 | 1 | 0.4 | 0.6 | 1.1 | 0.9 | 1 | 0.6 | 0.4 |
Sampling Rate (kS/s) | 100 | 100 | 1 | 1 | 2 | 1 | 10 | 10 | 2 |
Power (nW) | 399 | 473 | 1.8 | 130 | 27 | 5.8 | 90 | 41 | 5.29 |
DNL (LSB) | - | +0.8/−0.6 | +0.36/−0.35 | +0.8/−0.65 | +0.28/−0.17 | +0.59/−0.62 | - | - | +0.13/−0.10 |
INL (LSB) | - | +0.5/−0.7 | +0.44/−0.35 | +0.85/−0.6 | +0.81/−0.27 | +0.89/−0.41 | - | - | +0.5/−0.8 |
SNDR (dB) | 53.5 | 53.55 | 50.1 | - | 46.3 | 56.5 | 65 | 61 | 56.63 |
SFDR (dB) | 61.7 | 60.16 | 59.5 | - | 61.9 | 75.3 | 69 | 57.14 | |
ENOB (bit) | 8.59 | 8.35 | 7.9 | 7.6 | 7.4 | 9.1 | 7 | 10 | 8.43 |
FOM (fJ/conv.step) | 10.4 | 14.5 | 7.7 | 666 | 79.9 | 10.94 | 50 | 4.14 | 7.66 |
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Lakshmi, P.V.; Musala, S.; Srinivasulu, A.; Ravariu, C. Design of a 0.4 V, 8.43 ENOB, 5.29 nW, 2 kS/s SAR ADC for Implantable Devices. Electronics 2023, 12, 4691. https://doi.org/10.3390/electronics12224691
Lakshmi PV, Musala S, Srinivasulu A, Ravariu C. Design of a 0.4 V, 8.43 ENOB, 5.29 nW, 2 kS/s SAR ADC for Implantable Devices. Electronics. 2023; 12(22):4691. https://doi.org/10.3390/electronics12224691
Chicago/Turabian StyleLakshmi, Posani Vijaya, Sarada Musala, Avireni Srinivasulu, and Cristian Ravariu. 2023. "Design of a 0.4 V, 8.43 ENOB, 5.29 nW, 2 kS/s SAR ADC for Implantable Devices" Electronics 12, no. 22: 4691. https://doi.org/10.3390/electronics12224691