A Calibration-Free Digital-to-Time Converter for Phase Interpolation-Based Fractional-N PLLs

Abstract

In this paper, a fractional frequency division phase-locked loop based on phase interpolation is proposed and implemented using the TSMC 0.11 $\mathsf{\mu }$m CMOS process. Compared with the conventional phase-locked loop, a digital time converter (DTC) module is added to this phase-locked loop, and the DTC module can reduce the fractional spurious by phase interpolation. The circuit and analysis method of this DTC module are given in this paper. Unlike the existing approaches, the proposed DTC is calibration-free, and the error introduced by it is only related to the DAC adopted in the DTC. In addition, the accuracy of the DTC is 8 bits. Finally, this paper verifies the proposed quantization noise reduction technique using a 0.11 $\mathsf{\mu }$m CMOS process. The proposed FNPLL achieves the overall power consumption of 20.3 mW, the noise of $-117$dBc/Hz@1 MHz and $-138$dBc/Hz$@$10 MHz, and the RMS jitter of $0.860$ps. The area of the proposed FDIV is $60\times 245\mathsf{\mu }$m${}^2$, and the power consumption is $1.356$mW. The phase noise of the proposed FNPLL in the fractional division mode is just $2$dB higher than that in the integer division mode.

1. Introduction

The fractional frequency division technique is widely used in the fractional-N phase-locked loop (FNPLL), which is used for clock generation [1], frequency synthesis [2], and clock and data recovery [3]. Most of the current PLLs are all-digital phase-locked loops (ADPLL) and charge pump phase-locked loops (CPPLL). An ADPLL is PVT-robust [4] and has easy-to-use algorithms [5] to improve the performance of the ADPLL. In addition, the area of the ADPLL is small, but the phase noise performance of the ADPLL is relatively poor. The area of the CPPLL is generally larger, especially the CPPLL with an LC-VCO, in which the inductor will occupy a large area, but the phase noise performance of this structure is better, and the operating frequency can be higher [6]. Both types of phase-locked loops require the delta-sigma modulator (DSM), which is used to control the frequency division ratio in the PLL in order to achieve the fractional frequency division. However, the DSM will introduce quantization noise and fractional spurious, which will significantly degrade the PLL output phase noise.

There are many studies on the reduction in noise introduced by the DSM. One of the methods is changing the structure of the DSM [2,7,8,9,10,11]. Considering the quantization noise suppression capability and circuit stability issues, a third-order DSM is generally used. The second method is compensation. When the initial value and structure of the DSM are determined, the quantization error it produces can be calculated so the error can be compensated [12,13,14,15,16,17,18,19,20]. However, the feedforward compensation paths in the existing methods are generally long, so the effect of the compensation is affected by a circuit mismatch and requires additional auto-calibration circuits for the correction [16,17,18], further increasing the complexity of the circuit. The third way is the phase interpolation, which is actually one of the compensation ways, but this way does not involve the charge pump of the PLLs. The phase interpolation technique is used in [11,21,22,23,24,25,26], and the implementations of these circuits are different. However, all of those existing methods require modifications to other blocks in the PLL and require additional functional blocks, which makes the circuit more complicated. In addition, calibration is necessary in those methods because of the nonidealities in the proposed phase interpolation circuits.

In this paper, a DTC module based on the phase interpolation technique is added to the PLL; there are three innovations in the proposed DTC compared with the existing methods based on the phase interpolation method. Firstly, the DTC is placed almost as an independent module between the conventional fractional divider and the frequency discriminator, and no modifications to other modules in the phase-locked loop are required. Secondly, this divider is simpler in structure as it does not require additional calibration circuits compared to the existing approaches. Thirdly, this DTC has a higher accuracy of the phase interpolation.

Before analyzing the DTC proposed in this paper, the error introduced by the fractional divider and the principle of reducing this error by phase interpolation are analyzed in Section 2. The proposed DTC and the blocks adopted in the fractional divider are introduced in Section 3. The measurement results of the FNPLL and the comparison with prior arts are presented in Section 4.

2. Overview

2.1. Phase Noise Introduced by DSM

To achieve fractional frequency division, a digital DSM is used to control the frequency division ratio in the PLL. The instantaneous division ratio is the sum of a base integer, $N_B$, and the integer output of the DSM, $n_Q\left(t\right)$, so the average fractional division ratio is:

$$N=N_B+\overline{n_Q\left(t\right)}$$

(1)

where $\overline{n_Q\left(t\right)}$ is the average output of DSM, and

$$\overline{n_Q\left(t\right)}=\frac{k}{M}$$

(2)

where k is the input number to the DSM, and M is the modulus used in the SDM. When the PLL reaches the steady state, its output frequency is:

$$f_{out}=N·f_{ref}=(N_B+\frac{k}{M})·f_{ref}$$

(3)

and the frequency resolution would be:

$$△f=\frac{f_{ref}}{M}$$

(4)

Therefore, there is an error in each division, which can be expressed as

$$q_{\left(t\right)}=n_Q\left(t\right)-\overline{n_Q\left(t\right)}$$

(5)

The power spectrum density (PSD) of $q_{\left(t\right)}$ is the introduced quantization noise, which is related to the structure of the DSM, the initial value, the input, and the DSM bit width. In addition, there is a periodicity in the output sequence of the DSM that introduces fractional spurious, which can be solved by adding dithering at the input of DSM [27]. The quantization noise is randomized by default in all subsequent analyses in this paper. According to the conclusions in [28], phase noise generated by the fractional divider (FDIV) is:

$$S_{\theta div}\left(f\right)={\left[\frac{f_{fref}·Q\left(f\right)}{f·N}\right]}^2$$

(6)

where $Q\left(f\right)$ is the rms spectral density of the DSM-shaped quantization noise:

$$Q\left(f\right)=\sqrt{\frac{1}{12f_{ref}}}\left|H_{NTF}\left(z\right)\right|{\mid }_{z=e^{j2\pi f/f_{ref}}}$$

(7)

where $H_{NTF}\left(z\right)$ is the noise transfer function (NTF) of DSM. The phase noise introduced by the quantization noise of the DSM can be expressed as

$$S_{\theta out}=10log\{\frac{f_{ref}}{12{\left(Nf\right)}^2}·|H_{NTF}\left(e^{j2\pi f/f_{ref}}\right){|}^2·|H_{cl}\left(f\right){|}^2\}\mathrm{dBc}/\mathrm{Hz}$$

(8)

where $H_{cl}\left(f\right)$ is the closed-loop input-to-output phase noise transfer function of PLL.

2.2. Principles of Phase Interpolation

The division ratio of the conventional fractional divider varies, and when the division ratio is set to (2+1/4), its output waveform is shown in Figure 1 (the effect of dithering is not considered here to illustrate the idea). The phase difference between this output waveform and the ideal waveform can be calculated with the quantization error E of the DSM, so the phase of the output signal of the conventional FDIV can be adjusted according to the phase error to obtain the ideal output. Theoretically, the quantization noise introduced by the DSM can be completely eliminated as long as the accuracy of phase interpolation is sufficiently high. However, due to the accuracy and nonidealities of the circuits, there will still be quantization noise, which will be introduced in Section 3. The minimal step of phase adjustment achieved by the phase interpolation circuit is called the phase interpolation accuracy, e.g., $T/256$, where T is the period of PLL output.

One of the implementations based on phase interpolation is shown in Figure 2. The VCO generates multiple clock signals with a fixed phase difference and then phase select block selects the signal according to the phase error. The output phase noise E of PLL is reduced with the structure, but the circuit is complex and the accuracy is not high enough, for example, only 16 outputs of VCO with fixed phase difference of $\pi /8$ are realized in [27], which means the phase interpolation accuracy is only T/16. In addition, a MUX array is needed to select the signals, which further increases the complexity, area, and power of the circuit. In addition, additional phase select block is required if the VCO can not generate multiple clocks itself, such as LC-VCO.

In addition to above structure, other implementations were proposed, such as the vector divider structure proposed in [9] by increasing the number of dividers, phase frequency detectors (PFD), and charge pumps (CP) exponentially, where each group of dividers, PFDs, and CPs has the same structure and function as those in the traditional PLL. When it works, each group has a different divider ratio N[m,n], where m is the number of divider and n is time. Each divider has a different division ratio, and the average of them is $N+\alpha$:

$$\frac{1}{M}\sum _{m=1}^{M}N(m,n)=N+\alpha$$

(9)

where $\alpha$ is the fractional frequency division ratio and M is the number of divider, PFD, and CP. This design moves the spurious introduced by the FDIV to higher frequency and filters it out by the low-pass characteristics of the PLL. However, the cost of area and power consumption is considerable for this circuit. Moreover, as multiple groups of dividers, PFDs, and CPs are used, mismatches between devices can seriously affect the performance of the circuit.

The FDIV proposed in this paper is based on the phase interpolation technique, but unlike the above approaches, the method proposed in this paper is completed inside the FDIV and the modifications to other blocks in the FNPLL are not required. In addition, the proposed FNPLL achieves the phase interpolation accuracy of $T/256$.

3. Quantization Noise Reduction Technique

The structure of the PLL proposed in this paper is shown in Figure 3, where a DTC block is added to the conventional divider, and the other blocks in the PLL remain unchanged. In this fractional divider, y[n] takes the value of 0 or 1, so the waveform of the multi-modulus divider output signal is similar to that of traditional waveform shown in Figure 1, and there is phase error. When the DSM structure is determined, the error is known, so the DTC can eliminate the phase error by delaying the edges of the FLAG signal by different times according to the error ($E[7:0]$).

3.1. $\Delta -\Sigma Modulator$

Shown in Figure 4 is the DSM used in the proposed FDIV. Conceptually, the input clock frequency is divided by $Int+\frac{M}{N}$. The phase error is computed by accumulating the fractional period of the input clock using the DSM. The accumulator includes storage element (D) and summer. The quantizer (Q) generates $Q_{OUT}=1$ when $Q_{in}>=N$, else $Q_{OUT}=0$. The summing circuit subtracts N, whenever $Q_{OUT}=1$. Summing circuit increases the divider control signal by one whenever the accumulated phase error is greater than a period of the input clock. In order for the phase adjust module to properly adjust the clock signal generated by divider, the phase error supplied on control line to DTC is quantized to 256 levels of a period of the input clock:

$$PE=mod(\frac{256\ast E[7:0]}{N},256)$$

(10)

where $E[7:0]$ is the output of the accumulator. The dithering is added to randomize the output of DSM, which can reduce the fractional spur.

3.2. Multi-Modulus Divider

The multi-modulus divider used in the proposed FDIV is shown in Figure 5. It is implemented with nine /2 dividers in series. The outputs of the dividers change at the rising edge of the input signal $Clk\_i$. When the $Set$ signal is enabled, the count value of the divider is set to $data[7:0]$. The additional NMOS transistors are connected at the outputs of each /2 divider. At the rising edge of the input clock signal ($clk\_in$), the counter decreases by one, and when the value decreases to zero, the FLAG is dragged to low level, then logic circuits will make set signal enabled, the initial value is reloaded, and the FLAG is dragged to high level, resulting in a low-level pulse with a pulse width of one clock cycle on FLAG.

3.3. Digital-to-Time Converter

The structure of proposed DTC is shown in Figure 6. The DTC consists of a control signal generator, a DAC controller, and a delay cell. Control signal generator generates a series of control signals when FLAG signal comes and the waveforms of the signals are shown in Figure 6, where T in period of input clock. The DAC controller generates the DAC input $C[7:0]$ according to $E[7:0]$, which is the phase error provided by the DSM. If $E\left[n\right]$ is high, $C\left[n\right]$ will generate a low-level pulse with pulse width of T; otherwise, $C\left[n\right]$ will generate a low-level pulse with pulse width of 2T. The DAC output transistors will be turned off if the corresponding signal $C\left[n\right]$ is 0. The delay cell generates a delay with the range from 0 to T and an accuracy of $T/2^8$ according to $E[7:0]$.

Figure 7 shows the waveforms of signals when the delay cell is working. From 0 to T, the multi-modulus divider counts to 0 and generates the FLAG signal. Control signal generator generates A1, A2, …, A5 according to the FLAG. From 2T to 3T, MP4 is turned on and the capacitor is discharged while the DAC is turned off. From 3T to 4T, the output current of the DAC is $E[7:0]·I_0$, where $I_0$ is the output current corresponding to the lowest bit of DAC. After 4T, the DAC output current is $256·I_0$, which continues to charge the capacitor. When $V_{sig}=V_b-V_{th,n}$, MN2 conducts, $VM=V_{sig}$, and A3 is pulled high. At this time, MN1 is diode-connected, so $V_{sig}$ is stable, and the delay is completed.

The simulation results of the signals in DTC are given in Figure 8. The simulation results are in accordance with the above theoretical analysis.

According to the analysis, the charging time t1 corresponding to the quantization error of $E[7:0]$ should be:

$$C(V_b-V_{th,n})=E[7:0]·I_0·T+I_0·t_1$$

(11)

The charging time corresponding to a delay time of t2 for $E[7:0]=0$ is:

$$C(V_b-V_{th,n})=I_0·t_2$$

(12)

The difference between $t_1$ and $t_2$ is:

$$\Delta t=(t_2-t_1)=\frac{E[7:0]}{256}·T$$

(13)

It can be seen that the delay time is only related to the error $E[7:0]$ and the input signal period T. It is independent of the capacitance of the capacitor and the reference current of the DAC. Therefore, the delay time of this DTC module is less affected by PVT. In addition, the DTC is calibration-free.

There is another problem that needs to be considered. If the bit width of the DSM is 8 bits, then the FDIV will not introduce quantization noise with an 8-bits DAC, and only the noise introduced by the nonidealities of the DAC needs to be considered. However, according to Equation (4), the bit width of DSM is generally larger than 8 bits to achieve better frequency resolution, in which case the proposed FDIV will still introduce quantization noise. Fortunately, because of the DTC block, the magnitude of the quantization error is reduced by a factor of $M=2^{b_{DAC}}$ compared to conventional divider, where $b_{DAC}$ is the bits width of DAC. According to Equation (8), the phase noise introduced by the FDIV in the PLL output can be expressed as:

$$S_{QN}\left(f\right)=\frac{1}{M^2}\frac{{\pi }^2{T}_{ref}}{3N^2}{\left|H_{cl}\left(f\right)\right|}^2{\left|2sin\left(\frac{\pi f}{f_{ref}}\right)\right|}^{2(L-1)}$$

(14)

3.4. DAC Nonidealities

The 8-bits DAC adopted in the DTC block is shown in Figure 9. The cascode structure is used to increase the output resistance and make the DAC output characteristics more ideal. In order to avoid the fluctuation of output current when the output transistors’ DAC is switched on and off, the structure is adopted, in which the current source is always turned on regardless of the value of control signal.

The quantization noise reduction ability of the proposed FDIV is degraded by the nonidealities of DAC. First, the mismatch between the components of the DAC, which is caused by the PVT, introduced considerable noise. According to the adopted DSM shown in Figure 4, it can be seen that the noise introduced by the mismatch of DAC components and the quantization noise of DSM are both added at the same point, so the noise transfer function (NTF) is same for the both. According to conclusion in [9] and Equation (14), the PLL output phase noise introduced by the DAC mismatch can be expressed as

$$S_{MN}\left(f\right)=\frac{1}{M}\frac{{\pi }^2{\sigma }^2{T}_{ref}}{3N^2}{\left|H_{cl}\left(f\right)\right|}^2{\left|2sin\left(\frac{\pi f}{f_{ref}}\right)\right|}^{2(L-1)}$$

(15)

where $\sigma$ is the standard deviation of DAC output current. Because an 8-bits DAC is used in the proposed FDIV, so M = 256. Comparing Equations (14) and (15), it can be seen that when $\sigma$ is smaller than $M^{-0.5}=6.25\%$, the phase noise caused by DAC mismatch is smaller than the phase noise caused by DAC accuracy. The Monte Carlo simulation results of DAC output current are shown in

Table 1. Monte Carlo Simulation Results of the DAC Output Currents.

Input Code	Min(A)	Max(A)	Mean(A)	Std Dev(A)
0000_0001	535.7 n	563.8 n	549.0 n	5.006 n (0.91%)
0000_0010	1.038 u	1.096 u	1.066 u	10.29 n (0.97%)
0000_0100	2.001 u	2.127 u	2.060 u	22.80 n (0.91%)
0000_1000	3.997 u	4.248 u	4.114 u	45.35 n (1.11%)
0001_0000	8.000 u	8.491 u	8.228 u	88.92 n (1.08%)
0010_0000	16.00 u	16.98 u	16.46 u	177.8 n (1.08%)
0100_0000	32.00 u	33.96 u	32.91 u	355.7 n (1.08%)
1000_0000	64.00 u	67.93 u	65.82 u	711.4 n (1.08%)

. It can be seen that the $\sigma$ is less than 1.11% for all outputs.

The simulation results of the output frequency of the proposed divider are shown in Figure 10. When the DTC is turned on, the frequency fluctuation at the SS process corner is the largest, 0.164 MHz, and when the DTC is not turned on, the frequency fluctuation at the TT process corner is 4.767 MHz. The DTC effectively reduces the fluctuation of the output frequency of the fractional divider.

The quantization noise reduction capability of the FDIV is also related to the bit width of the DAC. The effective number of bits of the DAC directly affects the quantization noise rejection capability of the FDIV, and the table shows the simulation results of the output currents corresponding to the different inputs of the DAC in the DTC, based on which the integral nonlinearity (INL) of the DAC is calculated as following:

$$INL=\frac{\left|data·A_{LSB}-I\right|}{A_{LSB}}\approx 0.1$$

(16)

The phase noise introduced by the INL of the DAC is negligible compared to that introduced by mismatch.

3.5. Phase Noise of the Proposed FNPLL

Up to this point, this paper has analyzed the principle of the proposed quantization noise reduction technique and the effects of the DAC nonidealities on the output phase noise of the PLL. Based on that, this paper compares the effects of different FDIV structures on the output phase noise of the proposed FNPLL, and the simulation results of the contribution of each block to the output phase noise of the FNPLL are shown in Figure 11. It can be seen that the phase noise within the whole frequency band is suppressed significantly compared to the FDIV with a first-order DSM, and the phase noise around the 1 MHz frequency offset is suppressed significantly compared to the FDIV with the third-order DSM. In the case of similar output phase noise, the phase noise suppression technique proposed in this paper can achieve a better bandwidth.

4. Measurements Results

In this paper, the proposed quantization noise reduction technique is implemented using the 0.11 $\mathsf{\mu }$m CMOS process. The photograph of the proposed FNPLL is shown in Figure 12 and the testbench is shown in Figure 13. The chip has a DC supply voltage of 1.8 V and a core area of 1.49 mm${}^2$, of which the FDIV has an area of 6660 $\mathsf{\mu }$m${}^2$. The total power consumption of the chip is 20.3 mW, and the power consumption of a single FDIV is 1.356 mW. In addition, the reference frequency is 25 MHz, the FNPLL achieves the phase noise of −117 dBc/Hz @ 1 MHz and $-138$ dBc/Hz @ 10 MHz, the RMS jitter of 0.860 ps, and a bandwidth of 1.65 MHz.

As shown in Figure 14, the phase noise of the proposed FNPLL under the integer division mode (N = 100) and the fractional division mode (N = 100.105) are tested with an on-chip LPF under the same configuration. The center frequency is close to 2.5 GHz. Around the 1 MHz frequency offset, the difference between the phase noise of the proposed FNPLL in the integer division mode and fractional division mode is about 2 dB. The spectrum of the proposed FNPLL with the phase interpolation on and off is shown in Figure 15 and Figure 16. The proposed FNPLL has no significant fractional spurious (<67 dBc) with the phase interpolation on, while the fractional spurious is about −63 dBc with the phase interpolation off.

In order to find out the effect of the temperature on the proposed PLL, the output spectrum of the PLL is also tested at different temperatures. As shown in Figure 17, the result of $32.9{}^{\circ }$C is measured immediately after the chip is powered on, and the other is measured after the chip has been running for 10 min, of which the temperature is $67.3{}^{\circ }$C. It can be seen that the white noise in the output spectrum of the proposed PLL increases after the chip temperature increases, but the fractional spurious and reference spurious are still not obvious, indicating that the PLL proposed in this paper can reduce the fractional spurs even at a high operating temperature. This shows that the PLL proposed in this paper can achieve good compensation at higher operating temperatures. However, we could not precisely control the temperature because of the lack of a temperature chamber. More interesting findings might be obtained by testing at more specific temperature points.

The comparison with the prior arts are listed in

Table 2. Summary and Comparison.

	This Work	[9]	[16]	[29]	[30]	[31]	[32]
Quan. Noise Elimination Tech.	DTC PI	16-channel STA	Hybird-P/C PI	New DSM	FIR-embeded PI	DTC cancel	Segmented PI
Accuracy of PI	$T_{VCO}/256$	$T_{VCO}/16$	$T_{VCO}/4$	N/A	$T_{VCO}/16$	$T_{VCO}/256$	$T_{VCO}/16$
Technology (nm)	110	40	65	130	130	65	40
Output Frequency (GHz)	2.2–2.8	1.67–3.12	4.25–4.75	2	1	2.0–5.5	1.87–1.98
Reference Frequency (MHz)	25	50	50	64	32	50	26
Bandwidth (MHz)	1.65	2.76	12	1	3.2	5	2
Phase Noise (dBc/Hz @ 1 MHz)	−117	−100	−104	−107 @ 500 kHz	−106 @ 100 kHz	−97	−98
Phase Noise (dBc/Hz @ 10 MHz)	−138	−114	N/A	−118 @ 3 MHz	−107.5 @ 6 MHz	N/A	−115
RMS Jitter (ps) (Integ. Range (MHz))	0.860 (0.001–50)	2.26 (0.001–100)	1.50 (0.004–40)	N/A	N/A	1.86 (0.01–100)	3.10 (0.004–40)
Supply Voltage (V)	1.8	N/A	1	1.1–1.3	N/A	0.9	2.5 and 1.2
Core Area (mm${}^2$)	1.49	0.086	0.48	0.35	0.31	0.084	0.055
Core Power (mW)	20.3	4.85	11.6	21	16.8	4	10
Area of PI Circuits 1 (um${}^2$)	6660	17122	N/A	N/A	87500	4000	20900
Power of PI Circuits (mW)	1.356	1.29	2.552	N/A	N/A	N/A	N/A
FOM 2	−228.2	−226.1	−225.8	N/A	N/A	−228.5	−219.4

¹ The area of the QN circuits in prior arts are measured from the die photography or layout. ² FoM = $10lg\left[{\left(\frac{{Jitter}_{rms}}{1 sec}\right)}^2\right(\frac{Power}{1 mW}\left)\right]$.

, and the comparison shows that the proposed FNPLL has a better output phase noise as well as signal jitter, and the power consumption is acceptable. The comprehensive performance of the proposed FNPLL is better in terms of the figure of merit (FoM). More importantly, the proposed FNPLL has a phase interpolation accuracy of T/256, which is the highest accuracy among the compared papers and can better suppress the quantization noise of the DSM.

5. Conclusions

In this paper, a calibration-free DTC for an interpolation-based FNPLL is proposed and implemented using the 0.11 $\mathsf{\mu }$m CMOS process. The theoretical analysis of the circuit is presented, and the simulation and measurement results show that the fractional spurs introduced by the DSM are reduced compared to the traditional PLL. The phase interpolation has a high accuracy of $T/256$. The proposed DTC is calibration-free and the phase interpolation is completed within the proposed FDIV, so it can be easily applied to the different structure of the PLL. The proposed FNPLL achieves a phase noise of −117 dBc/Hz @ 1 MHz and −138 dBc/Hz @ 10 MHz with the bandwidth of 1.65 MHz at 2.5 GHz and a power consumption of 20.3 mW. The RMS jitter is 0.860 ps and the fractional spur of the proposed PLL is less than −69 dBc with the DTC ON.