A 12-Bit 1-GS/s Pipelined ADC with a Novel Timing Strategy in 40-nm CMOS Process

Round 1

Reviewer 1 Report

The mansucript shows a 12-bit 1GS/s pipelined ADC, which has been  manufactured in a 40 nm CMOS process.  The article is clear and quite interesting to be published. However, there are two important points in order to improved the last version of the article before publication:

1.- Please, complete 4 (Measured Results and Discussion) in order to corroborate in a more accurate way the performance of the implemented design.

2.- Complete Section 5 (Conclusions) in order to enhance the advatatge of the article proposal compare to other previous implementations.

 

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

The paper is devoted for novel high speed analog to digital converter fabrication and characterization. The topic is generally interesting, however the paper contain unexplained places (below) and need major revisions.

1) Fig. 14 is missing

2) Figs. 13-19 and Table 2 should be more commented.

3) The aim of the paper is not indicated in Introduction part

4) All abreaviations should be explained by first using, for example line 23 DNL, INL.

5) Conclusions should be rewritten in more informative way.

6) Numbers and measurements units should be written separately, for example line 199.

7) In Fig. 13 measurements units are missing.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 3 Report

Dear Authors,

English should be carefully reviewed by a mother-tongue colleague. Very often, it is very hard to follow the circuit description. I tried to flag as many issues as possible, however the entire paper should be checked.

 

a signal-to-noise ratio (ENOB) of 9.2 bits -> S/N and ENOB are not the same!

with a 227 MHz input frequency -> at a 227 MHz input frequency

Sample-hold-amplify (SHA) is used -> Sample-hold-amplifier (SHA) is used

sample-hold-amplify -> sample-hold-amplifier

can reduce the MDAC -> MDAC should be defined the very first time the acronym is used

Third, the chip's bit error rate can be greatly improved when combined with a high-speed comparator,
which approaching 10-15 in final testing and verification. -> it seems that the error rate is combined
with a high-speed... Please, modify the sentence

On the other hand, 63 the external 2GHz input clock increases the application difficulty of the system.
-> Please, clarify

Based on the PQT mentioned above, the performance of the modules in ADC core 70 should also be carefully designed.
-> This sentence is ambigous, please clarify

and delay of it does -> which does not ....

Firstly, this ADC adopts the method of automatic calibration 91 of residual curve to calibrate the residual curve
-> weird sentence! Please clarify

The injection position is more flexible and can 98 effectively improve the spectrum.
-> please clarify

concrete -> remove it

buffer's current -> buffer current

Based on PTQ timing -> Based on PQT timing

PTQ, including sampling -> PQT, including sampling

PTQ, including sampling -> please, change all PTQ in PQT ....

comparator 169 resets the output to a high voltage in time about 100 ps. -> please, clarify

Clock generation circuit of PTQ 175
As PTQ pointed out in section 2.2.2, -> as before, please change PTQ in PQT ...

the non-180 overlapping timing -> the timing

by adding more buffer -> by adding more buffers or buffering

1:1 duty cycle -> 1:1 ? please clarify

2G clock -> 2 GHz clock

is composed of a variable delay line -> is composed of a variable delay line (VDL)

In order to adapt to the clock frequency of 1.25GHz~250MHz,
four same 199 cell delay Line1/2/3/4 is selected by control code P/N<0:2>.
-> please clarify

The timing of delay line is introduced. CK is the input clock with 201 a duty of 50%.
CK delays 25% of the period to generate CKA. CK delays 50% of the period 202 to generate CKB.
CKB is reversed to produce CKC. CKD can be received by the logical op-203 eration of CKA
and CKC. PFD can detect whether CK and CKC are consistent. If the edges 204 are not consistent,
DP and DN are sent to charge pumb to adjust vct in Figure 5(a), until 205 CK and CKC are consistent.
Finally, CLK_CMP_MUX can be used to generate a clock with 206 a 25% duty cycle, and then the
clock of Ф4e can be obtained.
-> this section is very hard to follow. it should be rewritten from scratch

The strong-arm latch -> please clarify

The offset occupied by 231 the pre-amplifier is about ± 36 mV -> What 'occupied' does mean ?

the flip-around structure -> this structure

fatherly -> ???

to improve the sensitivity of matches and errors. -> what does that mean? Please rephrase


In this design, the sequence of calibration: first, front calibration to correct
capacitor 331 mismatches. The second step is background calibration, which is used
to correct inter-332 stage gain error. Finally, jointly complete the main digital
calibration at last.
-> English should be improved...

Author Response

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Author Response File: Author Response.pdf

Reviewer 4 Report

In this work, the authors presented a novel pre-quantization timing (PQT) strategy in a 1GS/s 12-bit pipelined ADC and discussed in detail its architecture and calibration scheme. This work provides an alternative method for ADC op-amp settling time optimization from the timing strategy point of view and compares its performance with other state-of-art ADCs, which will be of great interest to the analog and digital electrics community. I would recommend publishing (with minor revision), and yet there are a few questions that should be clarified and discussed further. Minor adjustments are needed to address the following questions:

 

·       Power consumption for the ADC presented in this work is higher than other counterparts in table 2 and becomes a main limiter for FOM. Going forward with further power consumption optimization, what would be the best option with the current scheme that the authors proposed?  

 

·       Could the authors comment more on how does the bit error rate of this work compare with other ADCs based on conventional timing?

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

Authors make proper corrections according to reviewer remarks and I suggest 

to publish the paper as it is.

Reviewer 3 Report

Dear Authors,

I am fully satisfied with this new version.