3.1. Dimensioning
In
Table 1, the proposed specifications for the DAB converter are illustrated. The indicated high target value for the switching frequency
= 200 kHz that would enable high power density, as discussed, can be addressed for these voltage and current ratings only by exploiting WBG semiconductor technologies to limit the switching losses and to enable higher operating temperatures. In
Table 2, a short list of commercially available WBG devices that are potentially suitable for the design goals in
Table 1 is shown. GS66516B [
18] provides the best performance in terms of parasitics and maximum current level; in particular, the null reverse recovery charge of GaN devices is achieved due to the absence of a body diode, which typically allows them to work at higher frequencies than SiC transistors. GaN switching time is shorter due to its much lower input capacitance. Moreover, the high-frequency design of the GS66516B leadless package guarantees minimal stray inductance, facilitating the minimization of the switching time. The GS66516B device was adopted to implement the two full bridges of the converter. With the following calculations and simulations, it is demonstrated that using four switches for every FB is enough to meet the specifications (no need for switch paralleling).
Considering Equation (
7), the parameters to be identified for the converter operation according to its specification and the device maximum ratings are
L and
. In addition to what was discussed in the previous section regarding power transfer and ZVS conditions, ref. [
16] shows how the selection of
and
L deeply impacts the control characteristics and the converter efficiency performance. Indeed, in the SPS control technique, lower
values in the nominal condition allow the reduction of the RMS current on devices, transformers, and DC-link capacitors, but makes the control too sensitive to small variations in
, requiring very high resolution for the phase shift control. On the contrary, for higher values (close to
), the control is smoother, but losses increase due to the higher RMS currents. Considering the inductor, from Equation (
7), the higher the value of
L, the higher the value of
for a target power transfer [
16]. Based on these considerations, a value between 20
and 50
is suggested for the nominal operative full power condition, without exceeding the 15
–75
range for the rest of the working cases. Imposing a
in the nominal condition (
= 400 V,
= 7.5 kW,
= 200 kHz, and
) into Equation (
7), the corresponding inductance value results in
L = 5.3
H. Once
L is known,
Table 3 can be computed, where
represents the peak value of
and is computed with Equations (
4) and (
5).
Some other considerations are required for the final choice of the value of the inductance. The maximum continuous current for GS66516B is
at
and
at
. Because the converter is air cooled, a maximum case temperature of
can be envisaged. It must be noted that
in
Table 3 is a peak value and thus should be compared with the maximum pulsed current for GS66516B, which, from the data sheet, is 120 A (for a maximum pulse width of
s). Nonetheless, the conservative approach to consider the continuous current limit for
was also taken for this prototype design, so
should not exceed
. With this requirement, the
case in
Table 3 is not acceptable. To investigate the feasibility of delivering
at
, the
current limit value is entered into Equation (
5) (peak current in buck mode), and the obtained
is substituted into Equation (
7), providing the new inductance value
L = 1.8
H. This value is not a good choice for a couple of reasons: (1) it may be smaller than the leakage inductance of the planar transformers [
19], making the design unfeasible; (2) such low inductance value leads to a decrease in the ZVS region [
16] and poor exploitation of the useful phase-shift range. These considerations rule out the possibility of maintaining full power delivery at minimum output voltage (at least with the described conservative approach to the maximum current rating of devices). Accepting a power de-rating at the lowest output voltage, some other considerations can be made for the selection of the inductance value.
Figure 4, computed from Equations (
4) and (
5), shows how a larger leakage inductance enables meeting the maximum current limit for a wider phase-shift range, increasing the converter controllability range; for low inductance values, the phase-shift range is heavily limited by the maximum peak current on the devices. Thus, from this observations, we decided to proceed from an inductance value of 5
H toward a value close to 8
H. The final selection was
for the nominal phase shift and the corresponding inductance
L = 8.35
H: the results for this final choice are listed in
Table 4. It can be noted that a
peak current on the switches is reached when
: this represents the minimum output voltage for full power delivery. At
, the row is empty because the phase-shift value required to obtain
would be greater than
. At
, the maximum output power is
.
Figure 5a depicts the computed trend in the output power and peak current on switches for the entire output voltage span, highlighting the separation between constant-power and constant-current regions.
In this configuration,
Figure 5b shows the ZVS limits for the input and output FBs, where ZVS operation is guaranteed in the region within the two boundaries, that is, when
for the output full-bridge and
for the input full-bridge, plus a contribution obtained from Equation (
9). The latter has a negligible effect on the boundaries above
, due to the low value of
; therefore, the nominal condition
always provides soft switching beyond this threshold. For
, the ZVS condition is above a phase shift of
; because this value is lower than the phase-shift value for
(
Table 4), soft switching is always verified in the actual design for nominal power. Moreover, for
,
(
phase-shift value), the ZVS condition is possible because the output power is
. In
Figure 6, the output power is related to the phase shift and output voltage with a threshold plane at
.
Once these parameters were selected, the converter was modeled and simulated in the PSIM simulation environment. These simulations were also used for the correct selection and sizing of the other components of the converter. Concerning the identification of the DC-link capacitors of both bridges, by allowing a voltage ripple with the maximum current value flowing in the switches (), the resulting computed capacitance value was F. Values in the range of tens of microfarads allow the employment of film capacitors, which have a higher voltage rating and less parasitics than electrolytic technology. The DC-link capacitor RMS current, ESR, and ESL must be carefully assessed in DAB converter design because of the high values of circulating currents in SPS modulation, along with unfiltered RMS currents in both the input and output ports. The most stressful operating point is when both the current and power are at their maximum values, and this happens for , where constant current and constant power regions collide. In this condition, the time-domain PSIM simulations showed how the RMS currents on the output and input capacitors are and , respectively. These values set a condition for the maximum ESR of the capacitors. Regarding the ESL, this also must be minimized to avoid high-voltage spikes due to the very fast commutations of the GS66516B switch, with the corresponding being as high as . These considerations lead to the use of multiple film capacitors in parallel in order to share the RMS current and obtain a lower equivalent ESL. Three TDK B32776P6226K000 polypropylene film capacitors are used: their main characteristics are . Even with a wise selection of capacitors, the voltage spikes and ringing on the output voltages are not compatible with the direct connection to a battery in a battery-charging operation. Thus, an additional light LC filter was inserted at the output to remove the voltage spike and ringing and to facilitate an output current control strategy.
A high-frequency (i.e., ) transformer in planar technology was custom made by Himag Planar, Quedgeley, England with a 1:1 turn ratio. In contrast with a wound transformer, the planar architecture provides easier thermal management, the low profile perfectly suits the typical charger form factors, and its realization increases the reliability and the precise control and repeatability of parasitics as the leakage inductance.
The total selected input series inductance
L = 8.35
H was obtained as the sum of the transformer leakage inductance and external power inductor in series to the primary. The realized component is depicted in
Figure 7: the external inductor was realized in the same enclosure of the transformer, practically doubling the transformer volume. The transformer characteristics are shown in
Table 5. The specified RMS current was obtained from the simulations. A transformer with a leakage inductance equal to the target value of
H would have minimized the dimensions and maximized efficiency (the estimated inductor power loss is
against the
of the transformer for full power operations) but was not possible because, to obtain such leakage inductance, the deterioration of the magnetizing inductance would have been too large. Nonetheless, the transformer + inductor component was still very compact (94 mm × 53 mm × 65 mm), and its predicted efficiency at full power was very high (
.
3.2. Simulations of Relevant Working Points and Efficiency Evaluation
In
Figure 8, the computed relationship between the output voltage and output current of the converter is shown. Different relevant operating points are highlighted and were selected for simulations. As discussed before, points A, B, and C are at maximum output power, whereas in D, the output power is limited by the maximum peak current on the switches (
). As shown in
Figure 9, the primary current and the voltages across the primary and secondary windings were obtained through PSIM simulations for each operating point. The different shape of the current allows distinguishing buck mode (points B and C), boost mode (point A), and nominal (i.e.,
, point B) conditions. The main results are summarized in
Table 6: as expected, the RMS and the peak device current values were the highest in the point C case. Clearly, point B is the most convenient point in terms of RMS currents, controllability, and efficiency; on the other hand, point C is the most stressful operating condition for the converter due to the high circulating currents.
The thermal/efficiency assessment of the converter in the steady-state condition was also computed in PSIM simulations, because the switches were modeled by using “thermal modules” models. These models allowed us to evaluate both the conduction and switching losses of the switches, exploiting a look-up-table approach, thus avoiding long waveform integration during switching events as in Spice-like simulators. Conduction losses were calculated using the vs. characteristics, referred to as the first and third quadrants at different temperatures ( during switch conduction). Switching losses were retrieved by inserting , values for different and switching conditions and the adopted gate resistance (). The junction temperature of the switches was computed because the models also accounted for temperature increases due to power dissipation and the thermal impedance of the switch in the actual set up (i.e., also taking into account the isolation layer beneath the devices, the heat sink of the IMS board for each leg, and the forced air velocity of of the cooling system, as described in the next section).
In
Table 7, the computed power dissipation values of all the eight GaN devices (four in the primary-side bridge and four in the secondary-side bridge) and their maximum junction temperatures are listed with the losses of the main passive components within the power stage (capacitors, inductance, and transformer, considering all their known parasitics). The ambient temperature used in the simulations was
.
The efficiencies reported in
Table 7 are in line with the state-of-the-art efficiencies of DAB converters in GaN technology for charging applications reported in [
9,
10,
11]. The main difference is that the proposed converter delivers twice the power with respect to the one described in [
9,
10,
11]. The converter efficiency is is very high in the conditions close to the nominal one. Indeed, as expected, point B is the most efficient condition for the DAB converter due to the unit voltage gain, where the RMS current is minimized under the same power conditions. The maximum junction temperature reached in the worst condition (point C) is
, which guarantees a large safety margin from the maximum rating of
. The converter is designed to operate at full power at up to a
ambient temperature. Particularly interesting is point D, where the switching losses in the secondary-side bridge are notably low. As described in
Figure 10, this is due to an almost ZCS behavior, because the drain current of switches Q5/Q8 is near to zero during the ON and OFF transition, whereas Q1/Q4 manage a higher current level at commutations.
Finally,
Figure 11 shows how the losses are distributed on the overall system for point B. For these computations, the losses of device drivers and low voltage controlling and sensing circuitry that are described in the next section were considered in terms of budget. It is evident that transistor losses account for more than
of total losses, where
is due to conduction losses, while the leakage inductor overcomes the transformer losses. If the inductance value can be directly embedded into the planar transformer, the efficiency gain would be significant. This graph also points out that the selection of a
switching frequency is a good compromise between compactness and performance for this voltage and current levels: at lower current/voltage levels, this GaN technology can switch up to
, but for the I/V levels of this circuit, the switching losses at such high frequency would significantly decrease the efficiency. Moreover, the core losses in the transformer would significantly increase at higher frequencies.
From the losses breakdown shown in
Figure 11, it is evident that the ZVS condition is very important for converter efficiency maximization. Indeed, the elimination of the turn ON switching losses assured by ZVS makes the switching loss contribution about
of that of the conduction loss, even though the switching frequency is high. For an accurate evaluation of the actual ZVS commutations implemented by the selected components, the Spice model of the GaN transistor and a behavioral model of the drivers were employed to perform accurate time-domain nonlinear dynamic simulations in the Advanced Design System (ADS) simulation environment, which is a circuital simulation tool by Keysight Technologies.
Figure 12 shows the voltage and channel drain-source current of the the switches (lower charts) and gate signals (upper charts) of each device in the DAB converter, during the turn-ON commutations for operative point C. It can be noted how for every switch of the DAB, at the switching off of the complementary transistor (i.e., during the dead time (
)), the
drops to zero, allowing a lossless switch-ON commutation of the transistor:
and
(channel conductive current), and the transistors do not overlap in the lower charts.
3.3. Architecture of the Prototype Converter
The converter was built following a modular approach and with a sparse component distribution in the main board in order to increase the prototype testability and eventual tweaking. This choice for the first development of the prototype obviously decreased the overall power density, which can be considerably increased in a successive design iteration. The three modules constituting the system were the mother board, control board, and GaN daughter module. The schematic of the entire converter is shown in
Figure 13. The mother board was a
FR4 PCB with
thickness with 4 layers of 2 oz of copper to withstand the high current levels of the power section. In addition, a wide exposed copper area, either on top and bottom layers connected by thermal vias, was arranged for the better thermal conductivity of the transformer. The low voltage section was populated by sensors and conditioning circuits of analog signals and by PWM signal traces. Power and low-voltage sections reference grounds were kept separated by a commercial isolated DC/DC AE40-EW-S12 by CUI that acted as an auxiliary supply providing a maximum of
and
. This auxiliary supply was largely over-sized for this application and was mainly selected for its availability: the dimensions of this functional block can be widely reduced with a custom design. In the layout design,
and
for clearance and creepage distance, respectively, were applied in conformity with the IEC 61010-1 and IEC 60335-2-29 standards. The control board was a 4-layer
FR4 board specifically designed to implement the control law of the converter. The board received sensed signals from the mother board and output PWM signals. The main component was a UCD3138 [
20] controller by Texas Instruments. The controller is a dedicated solution for power supplies characterized by a digital environment that manages a fast hardware state machine. This yielded less general-purpose microcontrollers than the typical C2000 family, with the advantage of being less energy-consuming. In this way, multiple feedback loops could be handled, sectioning fast paths for higher bandwidth response. An important feature is the possibility to generate 4 PWM signal couples at a higher time resolution (
) interlocked by an embedded phase-shift mechanism. The GaN daughter module consisted of two separated boards, a driver board and an IMS board. This solution was implemented to satisfy the need for enhanced thermal management together with minimal parasitics [
21]. These boards are described in
Figure 14 and
Figure 15.
The IMS board was a
PCB, where two GS66516B transistors were placed to form a half bridge, while the insulated metal substrate was in charge of conveying the heat produced to the heat sink, minimizing the thermal resistance. The driver board was implemented in a 4-layer
FR4 PCB and was populated by isolated gate drivers, isolated DC–DC converters for power supply, and ceramic capacitors for the local DC decoupling of the DC link for the minimization of the power-loop stray inductance. Two isolated single-channel ADUM4121 [
22] gate drivers by Analog Devices boosted the digital PWM signals from the microcontroller in two +6/−3 V gate signals with fast transitions and high peak/sink current capabilities, fundamental characteristics when driving WBG devices. Given a maximum skew of the delay time among two different ADUM4121 of
and the very fast commutation of the switches (delay time + rise/fall time <
), a
nominal dead-time value was selected and implemented in the PWM command generation. The placement of the drivers in the board was optimized to reduce the distance between their output and the gate ports of the transistors as much as possible to minimize the inductance of the gate driving loop. To this aim, a short
connector toward the IMS board was used, and the connection was made with the transistor Kelvin-source.
Sensing
The controller acquired 10 analog signals: 4 currents, 2 voltages, and 4 temperatures, plus a flag signal for over-current protection.
Concerning the first characteristics, the primary current (
), the input current (
), and two output currents (
,
) are sensed. As described in
Figure 13, the difference between
and
is the position of the sensor with respect to the capacitance of the output filter in particular. For the current flowing through the primary and leakage inductor, the ACS732KLATR-75AB-T [
23] Hall sensor by Allegro was employed. This sensor was able to sense a 75 A bidirectional current with a 1 MHz bandwidth. Its output was opportunely scaled by an OPAMP in differential configuration. The sensor provided a fast flag signal that was set to trigger when the peak current exceeded 65 A. For
and
, the MLX91221KDC [
24] Hall sensor by Melexis was used. Here, just the DC component was relevant, so high bandwidth was not required. The maximum current sustained was 38 A, which was sufficient to acquire a 28 A
in the worst case (
,
). Regarding
, an ACS724KMA Hall sensor by Allegro was used, which allowed 65 A bidirectional current sensing. Because the current before
had a strong harmonic content, the use of a sensor with wider input range was required. One signal between
and
sensing was provided to the uC by the position of a jumper. The choice could be made depending on the speed of the current feedback loop, because
gives a slower response than
.
All the low-voltage output signals were conditioned by an OPAMP in differential configuration. Voltages at the input and output ports were sensed by two resistive dividers. Because electrical isolation must be kept between the high- and low-voltage sections, the output of divider was provided to an ACPL-C87A [
25] Broadcom isolated OPAMP with dual power supply. The
signal was used to close the voltage loop, while
was used for OVP and for the feed-forward operation.
The temperature signals provided information about the GaN transistors’ case temperature. A PT100 resistor was placed on each IMS board close to the power devices, giving a good approximation owing to the metal substrate. The variable voltage dropout on the PT100 was managed by a Wheatstone bridge designed on the current rating of the thermistor.