Layout of MOS Varactor with Improved Quality Factor for Cross-Coupled Differential Voltage-Controlled Oscillator Applications

Abstract

In this study, we designed an MOS varactor for application in the differential voltage-controlled oscillator (VCO). To improve the quality factor of the MOS varactor, we proposed a symmetric layout technique of the MOS varactor with reduced parasitic components. Compared with the typical MOS varactor layout, the metal line for the interconnection of the MOS varactors that is inevitable in the typical MOS varactors for the cross-coupled VCO was minimized to reduce the parasitic resistance. In addition, with the reduced interconnection metal line, the overall size of the proposed MOS varactor was also reduced compared with the typical one. To verify the feasibility of the proposed MOS varactor structure, the typical and proposed MOS varactors were designed using a 180 nm RFCMOS process. Compared to the typical MOS varactor, the measured quality factor of the proposed MOS varactor was improved by approximately 32% at the operating frequency of 5.0 GHz. Additionally, we successfully verified that the parasitic capacitance induced by the lossy silicon substrate was reduced in the proposed MOS varactor structure.

1. Introduction

With an advancement in electronic devices, the need for wireless communication technology continues to increase. The voltage-controlled oscillator (VCO) is one of the key components in wireless communication systems. In general, the cross-coupled VCO is popular for GHz-order RF systems because of its low-phase noise characteristics [1]. Accordingly, studies on various modified VCOs based on the cross-coupled type have been actively conducted [2,3,4,5,6,7,8,9]. However, as RF systems become more sophisticated to cover a higher data rate, further improvements in the phase noise of the VCO are required.

Such phase noise is one of the most important indicators of the VCO’s performance, and many studies related to the phase noise have been conducted. Based on Lesson’s model, the phase noise of L(Δω) of the VCO with the LC tank can be derived as follows:

$$\begin{array}{l}\mathrm{L}\left(\mathsf{\Delta }\mathsf{\omega }\right)=10\log \left(\frac{2\mathrm{FkT}}{{\mathrm{P}}_{\mathrm{S}}}\left(1+{\left(\frac{{\mathsf{\omega }}_0}{2{\mathrm{Q}}_{\mathrm{L}}\mathsf{\Delta }\mathsf{\omega }}\right)}^2\right)\left(1+\frac{\Delta {\mathsf{\omega }}_{1/{\mathrm{f}}^3}}{\left|\Delta \mathsf{\omega }\right|}\right)\right)\\ \mathrm{F}:\mathrm{Empirical}\mathrm{parameter}\\ \mathrm{k}:\mathrm{Boltzmann}’\mathrm{s}\mathrm{constant}\\ \mathrm{T}:\mathrm{Absolute}\mathrm{temperature}\end{array}$$

(1)

where P_S, ω₀, Q_L, and Δω₀ are the average power dissipated in the parasitic resistance of the LC tank, the oscillation frequency, the effective quality factor of the LC tank, and the offset from the carrier frequency, respectively. Δω_1/f³ is the frequency of the corner between the 1/f³ and 1/f² regions. This implies that the quality factor of the LC tank affects the phase noise of the VCO [10]. Therefore, in order to improve the phase noise, it is important to improve the quality factor by minimizing the parasitic resistance of the inductor, capacitor, and MOS varactor constituting the LC tank [11,12,13].

Many extant studies have attempted to minimize the parasitic resistance induced by the spiral inductor of the LC tank to improve the phase noise of the VCO. Although the parasitic resistance induced by the spiral inductor degrades the phase noise of the VCO the most significantly, the low quality factor of the MOS varactor that is essential in the VCO also degrades the phase noise of the VCO significantly [14,15]. Moreover, given the channel resistance and complicated structure of the MOS varactor, the varactor itself has a relatively low quality factor compared to the metal–insulator–metal (MIM) capacitor. Additionally, if the size of the MOS varactor is increased to improve the frequency tuning range of the VCO, the quality factor of the MOS varactor is further deteriorated.

In this work, we propose a layout technique that can improve the quality factor by reducing the parasitic resistance component of the MOS varactor for VCO applications. In Section 2, the quality factor of the MOS varactor is investigated, and the proposed layout technique of the MOS varactor is described in Section 3. Measurement results to verify the effectiveness of the proposed layout technique are shown in Section 4.

2. Quality Factor of the LC Tank with MOS Varactor

Figure 1 shows the typical cross-coupled VCO with a differential structure. As shown in Figure 1a, two MOS varactors are essential to obtain the symmetrical differential signal and to block the dc voltage of the control voltage, V_CTRL. Therefore, the metal line to connect two MOS varactors is also required between two MOS varactors. However, the interconnection metal line causes additional parasitic components, which can further degrade the quality factor of the LC tank. Figure 1b shows the parasitic components induced via the contact and metal line. In particular, the contact that is essential for the interconnection of the metal lines significantly degrades the quality factor of the MOS varactors. Consequently, to improve the phase noise of the VCO, the loss induced by the interconnection metal line should be suppressed.

To investigate the effect of the MOS varactors on the quality factor of the LC tank, we analyzed the simple LC tank structure shown in Figure 2. As shown in Figure 2b, to obtain the required tuning range of the operation frequency of the VCO, the MOS varactor was used in parallel with the MIM capacitor. In general, the quality factor of the MIM capacitor is much higher than that of the MOS varactor. Accordingly, if the capacitance of the MOS varactor increases to expand the tuning range of the operation frequency, the overall quality factor of the LC tank may be deteriorated. In Figure 2c, the MOS varactors with an interconnection line are shown. For the convenience of analysis, the equivalent circuit of the interconnection metal line was simplified to parasitic resistance and inductance.

The quality factor of the LC tank can be expressed as follows [15,16]:

$$\frac{1}{{\mathrm{Q}}_{\mathrm{LC}}}=\frac{1}{{\mathrm{Q}}_{\mathrm{L}}}+\frac{1}{{\mathrm{Q}}_{\mathrm{C}}}$$

(2)

where Q_LC, Q_L, and Q_C are the quality factors of the LC tank, inductor, and capacitor, respectively. Considering the MOS varactor for frequency tuning, the Q_C can be expressed as follows:

$$\mathrm{C}={\mathrm{C}}_{\mathrm{MIM}}+\frac{1}{2}{\mathrm{C}}_{\mathrm{VAR}}$$

(3)

$${\mathrm{Q}}_{\mathrm{C}}=\left(1+\frac{{\mathrm{C}}_{\mathrm{MIM}}}{0.5{\mathrm{C}}_{\mathrm{VAR}}}\right){\mathrm{Q}}_{\mathrm{VAR}}$$

(4)

$$\frac{1}{{\mathrm{Q}}_{\mathrm{LC}}}=\frac{1}{{\mathrm{Q}}_{\mathrm{L}}}+\frac{1}{\left(1+\frac{{\mathrm{C}}_{\mathrm{MIM}}}{0.5{\mathrm{C}}_{\mathrm{VAR}}}\right){\mathrm{Q}}_{\mathrm{VAR}}}$$

(5)

where C, C_MIM, C_VAR, and Q_VAR are the total capacitance of the LC tank, the capacitances of the MIM capacitor and MOS varactor, and the quality factor of the MOS varactor including the interconnection metal line, respectively. In this case, considering the parasitic components of the interconnection metal line for two MOS varactors, Q_VAR can be expressed as follows:

$${\mathrm{Q}}_{\mathrm{VAR}}=\frac{1}{0.5\mathsf{\omega }{\mathrm{C}}_{\mathrm{VAR}}\left(2{\mathrm{R}}_{\mathrm{VAR}}+{\mathrm{R}}_{\mathrm{ML}}\right)}$$

(6)

where R_VAR and R_ML are the parasitic resistances of the MOS varactor and interconnection metal line. As a result, Q_LC with parasitic components of the MOS varactors and interconnection metal line can be calculated as follows:

$$\frac{1}{{\mathrm{Q}}_{\mathrm{LC}}}=\frac{1}{{\mathrm{Q}}_{\mathrm{L}}}+\frac{\mathsf{\omega }{\left(0.5{\mathrm{C}}_{\mathrm{VAR}}\right)}^2\left(2{\mathrm{R}}_{\mathrm{VAR}}+{\mathrm{R}}_{\mathrm{ML}}\right)}{{\mathrm{C}}_{\mathrm{MIM}}+0.5{\mathrm{C}}_{\mathrm{VAR}}}$$

(7)

Here, C_SUB and R_SUB in Figure 2c were ignored in the equations for the convenience of analysis. As can be seen in the analyzed Q_LC, the metal line for the two MOS varactors degrades the overall quality factor of the LC tank, and consequently the performance of the VCO can be degraded.

The degradation of Q_LC via the interconnection metal line can also be confirmed by the simulation results in Figure 3. In Figure 3, electromagnetic simulation was performed by increasing the length of the interconnection metal line. The length of the metal line being zero means an ideal case without an interconnection metal line. As can be seen in Figure 3, Q_LC was degraded as the length of the interconnection metal line increased. In addition, since the parasitic capacitance occurs between the metal line and the silicon substrate, the parasitic capacitance of the metal line also increased as the length increased. The parasitic capacitance of the metal line also causes power loss and is one of the reasons for the deterioration of Q_LC. The parasitic capacitance shown in Figure 3b includes C_SUB by the metal line and parasitic capacitance in the varactor. As a result of analysis and simulation, the degradation of the quality factor by the metal line cannot be ignored.

3. Proposed MOS Varactor Structure

In this study, we proposed a layout technique for two varactors that can remove the degradation of the quality factor caused by the metal line by removing the metal line located between the two varactors. Figure 4 shows the conceptual layouts of the typical and proposed MOS varactors.

Generally, in the cross-coupled VCO, as shown in Figure 4, two MOS varactors face each other. The V_CTRL for tuning the capacitance is applied through a node in which two MOS varactors are connected to each other. In general, each MOS varactor consists of unit-transistors in the form of a finger, combining the drain and the source to form a single node. As described above, it is essential to use a metal line for connecting two MOS varactors to each other in the typical structure of Figure 4a.

For cross-coupled VCO applications, two MOS varactors are required in the case of the typical structure. On the other hand, in the case of the proposed structure, a cross-coupled VCO can be applied with only one MOS varactor, as shown in Figure 4b. As shown in Figure 4b, the proposed structure was formed by grouping both drains and sources of the MOS varactor into one node. On the other hand, in the case of the gate nodes, gates that are not adjacent to each other were connected to each other, and as a result, two gate nodes were formed. In this work, as shown in Figure 4b, the two gate nodes are indicated as Gate 1 and Gate 2, respectively. The right side of Figure 4b is a conceptual diagram to aid understanding, and the actual layout is similar to the left side of Figure 4b. As a result, in the proposed structure, two MOS varactors were designed to share sources and drains with each other, and eventually the two MOS varactors were combined into one MOS varactor. Therefore, in the proposed MOS varactor structure, the interconnection metal line which is essential in the typical structure was removed, resulting in the removal of parasitic resistance and capacitance of the metal line. Accordingly, the quality factor of the proposed structure can be improved compared with the quality factor of the typical structure.

As described above, the two MOS varactors for the typical structure were combined into one MOS varactor for the proposed structure. Therefore, the MOS varactor of the proposed structure doubles the total gate width compared to the MOS varactor of the typical structure. The method of increasing the total gate width of the MOS varactor for the proposed structure aims to increase the unit gate width or the number of fingers. In the case of the method of increasing the number of fingers, the length of the MOS varactor may be excessively long, and thus the metal lines forming the Gate 1 and Gate 2 nodes are also lengthened, which may cause the quality factor to degrade again. Therefore, in this study, the unit gate width was increased to increase the total gate width of the MOS varactor for the proposed structure.

Figure 5 shows the simulation results of the quality factors of the MOS varactor according to the unit gate width. The results in Figure 5 are the simulation results of the MOS varactor itself, not the MOS varactor with a differential structure. In addition, if the gate length increases excessively, the parasitic resistance increases excessively, so the gate length was set to 4, 6, and 8 μm. As the total gate width of the MOS varactor increased, the dependence of the quality factor on the unit gate width weakened. In general, to expand the tuning range of the operation frequency, the total gate width of the MOS varactor should increase. In this study, the total gate width of the MOS varactor was selected for the 5.0 GHz applications. The total gate width of the MOS varactor was chosen to be 192 μm. Consequently, it can be seen that the unit gate width of the MOS varactor with the proposed structure increased; however, the degradation of the quality factor is insignificant, accordingly.

4. Measurement Results

To verify the feasibility of the proposed MOS varactor structure, we designed the MOS varactors with typical and proposed structures using a 180 nm RFCMOS process. The photographs of the designed MOS varactors are shown in Figure 6. In this study, the selected unit gate width was 4 μm. As shown in Figure 6, the interconnection metal lines for the MOS varactor were removed in the proposed structure. Accordingly, the parasitic components induced by the interconnection metal lines were also removed.

For a fair comparison, the total gate width of the two MOS varactors for the typical structure and the total gate width of the MOS varactor for the proposed structure were designed to be the same. The core sizes of the typical and proposed MOS varactors were 42 × 33 μm² and 32 × 33 μm², respectively. As a result, the size of the proposed structure decreased by approximately 23.8% compared to the size of the typical structure.

In the measurement, the V_CTRL varied from 0.0 V to 2.4 V. Figure 7 shows the measured quality factors and capacitances according to operation frequency. As can be seen in Figure 7, because of the parasitic capacitance of the interconnection metal line of the typical structure, the capacitance of the typical structure was higher than that of the proposed structure. With V_CTRL of 2.4 V, the measured capacitances of the typical and proposed structures were approximately 0.32 pF and 0.25 pF, respectively. On the other hand, in the case of the variable range of the capacitance according to the V_CTRL, the proposed structure was measured to be wider than the typical structure. In addition, the proposed structure was measured to have a higher quality factor regardless of the V_CTRL compared to the typical structure. The measurement results in Figure 7 showed the same tendency as the simulation results in Figure 3. That is, as the interconnection metal line of the typical structure was removed from the proposed structure, the parasitic capacitance of the proposed structure decreased and the quality factor increased.

5. Conclusions

In this study, we proposed a layout technique of the MOS varactors for cross-coupled VCO applications. First, the effect on the quality factor of the metal line for the MOS varactor was analyzed. In order to improve the quality factor by mitigating the parasitic components of the metal line for the typical MOS varactor structures, the metal line for connecting the two MOS varactors was removed by combining the two MOS varactors for the typical cross-coupled VCO into one MOS varactor. The proposed MOS varactor structure consisted of several MOS transistors in the finger type, and all of the drains and sources of the fingers were connected to each other to form a single node, through which a control voltage for varying the capacitance of the MOS varactor was applied. On the other hand, gates that were not adjacent to each other were connected to each other, and the proposed MOS varactor had a total of two gate nodes. These two gate nodes were connected to the differential nodes of the differential cross-coupled VCO, respectively. To verify the feasibility of the proposed MOS varactor structure, the typical and proposed MOS varactors were designed using a 180 nm RFCMOS process. Compared to the typical structure, it was confirmed that the proposed structure had a reduced chip area by approximately 32%. In addition, it was confirmed through measurements that the parasitic capacitance induced by the interconnection metal line which was essential in the typical MOS varactor structure was successfully removed. Finally, regardless of the control voltage of the MOS varactor, it was confirmed that the MOS varactor with the proposed structure had a higher quality factor than that of the typical structure.