Design and Performance Analysis of a [8/8/8] Charge Domain Mixed-Signal Multiply-Accumulator

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

In this article the authors present the design and performance analysis of a charge domain mixed-signal MAC. The 8-bit resolution is chosen to be enough for general purpose AI processors. The multiply and accumulate operation is implemented using an RDAC to convert the digital input to an analog quantity, which is weighted using a CDAC and the sum of the contributions (in the charge domain) is converted back to the digital domain using a capacitive SAR ADC. The performances of a proof-of-concept implementation is presented.

However, some of the presented details are not clear:

·        in section 2.2 it is stated that the capacitance of the CDAC is 5fF. Assuming that the authors mean that the unit capacitance is 5fF, and considering that there are capacitances of CDAC, it would seem that the CDAC contains capacitances as small as 19.5aF (atto farads!). In this case, please elaborate on the effect of the stray capacitances of the interconnect wires on the matching of the capacitances in the CDAC;

·        please elaborate on the analysis that led to the error model presented in Fig. 9, as it is not clear how the errors in the RDAC and the errors in CDAC linearly add up in the model;

·        for the derivation of the result in equation (9) has the effect of the stray capacitance of the interconnects been considered?

·        in section 3.1, line 133 it is said that the upper 4 bits use a thermometer code – is this accurate?

Author Response

Answers to the reviewer’s comments

Dear Associate Editor and Reviewers,

We express our sincere gratitude for the time and effort you have dedicated to reviewing our paper. Your insightful comments and feedback have been instrumental in enhancing the quality of our work.

In response to your suggestions, we have made revisions to the manuscript. The sections that have been modified are highlighted in red in the updated version. We have addressed all the comments and concerns raised by the reviewers, and the specific changes made are detailed below:

Reviewer 1:

We greatly appreciate your kind words and constructive feedback!

1- In section 2.2 it is stated that the capacitance of the CDAC is 5fF. Assuming that the authors mean that the unit capacitance is 5fF, and considering that there are capacitances of, it would seem that the CDAC contains capacitances as small as 19.5aF (atto farads!). In this case, please elaborate on the effect of the stray capacitances of the interconnect wires on the matching of the capacitances in the CDAC.

The authors want to thank the reviewer for this question.

The capacitance has a minimum value of approximately 20aF, which is remarkably small, yet it functions with an 8-bit precision. Figure 17 presents the actual measurement of the MAC’s linearity. The accuracies of the RDAC, CDAC, and SAR-ADC have been evaluated and documented.

The linearity error of the RDAC is minimal, and the CDAC’s error is averaged and thus mitigated. As a result, the linearity observed appears to primarily reflect the error of the SAR-ADC. Similar to the MAC, the SAR-ADC employs a CDAC with a total capacitance of 5 fF. The measured DNL is less than 0.4 LSB, and the best-fit Integral Nonlinearity INL is less than 0.5 LSB, meeting the 8-bit precision requirement. Consequently, even with a minimum capacitance of 20aF, it is simulation and measurement results indicate that an 8-bit precision CDAC has been successfully implemented.

The capacitance between the two terminals, which determines the accuracy of the interconnect part’s parasitic capacitance, is largely influenced by the sidewall capacitance in the case of the MOM capacitance utilizing the wiring. Therefore, it is inferred that the parasitic capacitance of the wiring’s protruding part contributes marginally to the capacitance between the two terminals.

Figs. 4 (b) and 5 (b) were added to describe the MOM capacity used in CDAC in more detail. The following text was also added on pages 3-4 of the manuscript:

The overlap length of the MOM capacitor is 1.02μm and the total length of 8-bit MOM capacitor is 3.08μm with a unit MOM capacitor pitch of 0.28μm.

Figure 5 illustrates the structure of the LSB capacitors and a side view of the MOM capacitance. The capacitance density is high with C5 using four layers, C4 two, and C3, C2, and C1 one each. C2 and C1 are half and a quarter the length of the others, respectively. This design reduces the CDAC area and stray capacitance. Despite minor accuracy concerns, the 8-bit resolution requirement is met as shown in Figure 17.

2- Please elaborate on the analysis that led to the error model presented in Fig. 9, as it is not clear how the errors in the RDAC and the errors in CDAC linearly add up in the model.

The authors want to thank the reviewer for this question.

The error of the MAC portion composed of RDAC and CDAC is considered to be determined by the error of charge Q. The output of the RDAC can be expressed as the capacitance error,  Therefore, . Therefore, the error can be treated as a linear addition of the error due to resistance and the error due to capacitance. 

To explain this approximation, the following sentence was added on page 7.

Voltage generated by the RDAC and capacitance of the CDAC are multiplied by taking a product, but for the sake of simplicity, we used an approximation in which the product of two variables, including the error of the RDAC and the CDAC, can be approximated by adding each error if the error is small enough.

3- For the derivation of the result in equation (9) has the effect of the stray capacitance of the interconnects been considered?

The authors want to thank the reviewer for this question.

As described in question 1, the effect on the capacitance between the two terminals in the parasitic capacitance of the wiring is considered to be extremely small, so the effect was not incorporated.

4- In section 3.1, line 133 it is said that the upper 4 bits use a thermometer code – is this accurate?

The authors want to thank the reviewer for this question.

Indeed, as illustrated in Figure 2 of the manuscript, the RDAC adopts a segmented architecture. It comprises a unary section for the Most Significant Bits (MSB) using equal resistors for the top 4-bits, and a binary type section for the Least Significant Bits (LSB) employing R-2R resistors for the bottom 4-bits. As a result, the thermometer code is utilized for the upper 4-bits, as observed by the reviewer.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

This work presents the on-chip implementation of an analog MAC module suitable for AI applications in low-power environments.

The paper satisfactorily presents the design and its operational principle, together with an analysis of the major error sources and their effects. A prototype was also measured, and it outperforms the current SotA in several aspects, despite being build with a not-so-new technology node.

I think the work is interesting to the scientific community and can be published. I have no particular recommendation to make as the content is already satisfactory, just carefully proofread it as there are symbols sometimes defined more than once and the formatting is not always perfect.

Author Response

Answers to the reviewer’s comments

Dear Associate Editor and Reviewers,

We express our sincere gratitude for the time and effort you have dedicated to reviewing our paper. Your insightful comments and feedback have been instrumental in enhancing the quality of our work.

In response to your suggestions, we have made revisions to the manuscript. The sections that have been modified are highlighted in red in the updated version. We have addressed all the comments and concerns raised by the reviewers, and the specific changes made are detailed below:

Reviewer 2:

This work presents the on-chip implementation of an analog MAC module suitable for AI applications in low-power environments. The paper satisfactorily presents the design and its operational principle, together with an analysis of the major error sources and their effects. A prototype was also measured, and it outperforms the current SotA in several aspects, despite being built with a not-so-new technology node. I think the work is interesting to the scientific community and can be published. I have no particular recommendation to make as the content is already satisfactory, just carefully proofread it as there are symbols sometimes defined more than once and the formatting is not always perfect.

Thank you for your insightful review and positive feedback on our work. We appreciate your recognition of the novelty and relevance of our research to the scientific community. We acknowledge your suggestion regarding the proofreading of the manuscript. We will ensure a thorough review of the document to rectify any inconsistencies in symbol definitions and formatting. Once again, we express our gratitude for your time and valuable comments.

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

Specific comments and recommendations:

1) It is not acceptable to include abbreviations in article titles, and this should be avoided. All abbreviations in the text have to be detailed in a separate table;

2) It is not clear from the comparison given in Table 1 what the advantages of the proposed configurations are. The authors have to perform a deeper and more detailed analysis;

3) The authors must describe in more detail the practical application of the proposed configurations. Specific schemes or structures must be presented. For mixed circuits, 8-bit resolution is in any case a relatively small value;

4) The authors have to describe in detail how the experimental study of the proposed configuration was performed.

Comments on the Quality of English Language

Minor editing of English language required.

Author Response

Answers to the reviewer’s comments

Dear Associate Editor and Reviewers,

We express our sincere gratitude for the time and effort you have dedicated to reviewing our paper. Your insightful comments and feedback have been instrumental in enhancing the quality of our work.

In response to your suggestions, we have made revisions to the manuscript. The sections that have been modified are highlighted in red in the updated version. We have addressed all the comments and concerns raised by the reviewers, and the specific changes made are detailed below:

Reviewer 3:

The authors want to thank the reviewer for these questions.

Specific comments and recommendations:

1- It is not acceptable to include abbreviations in article titles, and this should be avoided. All abbreviations in the text have to be detailed in a separate table.

Thank you for your comment. In line with your suggestions, the title has been revised to: “Design and Performance Analysis of a Charge Domain Mixed-Signal Multiply-Accumulator”. This change has been reflected in the revised manuscript.

2- It is not clear from the comparison given in Table 1 what the advantages of the proposed configurations are. The authors have to perform a deeper and more detailed analysis.

We appreciate the reviewer’s insightful question. The previous works listed in Table 1 primarily employ Computing In Memory (CIM) technology. However, their descriptions of the MAC circuit are often unclear, making a quantitative comparison with our proposed MAC challenging.

The significance of our paper lies in demonstrating that a standard Mixed-Signal MAC can achieve sufficient computational accuracy and world-leading computing efficiency. We also show that technology scaling can further enhance this efficiency. Our work presents a model of computational accuracy and efficiency and illustrates that by increasing the number of parallels (m), element variations can be averaged to improve accuracy, and the energy consumption of the SAR-ADC can be proportionally reduced.

While our work has been presented at a macro level without actual data from a practical system-level application, we believe that showcasing the standard form of a Mixed-Signal MAC and its high potential, both theoretically and experimentally, is extremely valuable for future technological advancements.

Since this point is also related to question 3, we have combined the replies for these two questions. The additional descriptions are explained in the subsequent section.

3- The authors must describe in more detail the practical application of the proposed configurations. Specific schemes or structures must be presented. For mixed circuits, 8-bit resolution is in any case a relatively small value.

We appreciate the reviewer’s insightful question. Our work, while presented at a macro level without actual data from a practical system-level application, showcases the standard form of a Mixed-Signal MAC and its high potential, both theoretically and experimentally. This is extremely valuable for future technological advancements.

Benchmarking at the application and system level provides a comprehensive view of tradeoffs across multiple design dimensions. However, it’s not always feasible, especially for academic and industrial research chips. Our work benchmarks a chip at lower abstraction levels, where the influence of circuit-level metrics on specific tasks at the system level remains unclear. This study aims to bridge this gap by analyzing a case study of a charge domain mixed-signal multiply-accumulator (MS-MAC) using RDAC, CDAC, and SAR-ADC with an 8-bit resolution. Our goal is to establish a framework that guides the specification, extraction, and extrapolation of circuit-level metrics to higher abstraction levels.

Lastly, we believe that the AI processor often supplies weight data to the CDAC by utilizing nearby non-volatile memory such as MRAM, FeRAM, and PRAM. This reduces the power consumption caused by data transfer from the memory. In signal processing for optical communications, reducing power consumption through ultra-high-speed operation is crucial, and achieving a resolution of about 8 bits is feasible.

We have also included the following text on page 17 of the revised manuscript:

The MS-MAC macro has a fully digital I/O interface and can be seamlessly used as a replacement for digital MAC circuits. Moreover, the energy consumption associated with data transfer, and consequently, the system-level energy efficiency, can be improved by combining the MS-MAC macro with non-volatile memory, such as MRAM, FeRAM, and ReRAM. 

Furthermore, one interesting candidate to be used is the high-speed and low-power digital filters on an ultra-high-speed DSP for optical communication systems [16] since data resolution is 8-bit and the power consumption of current digital circuits is very large.

Reference [16] has also been included.

[16] J. Cao, et al.,” A Transmitter and Receiver for 100Gb/s Coherent Networks with Integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS,” IEEE International Solid-State Circuits Conference, Dig. Tech. Papers, pp. 484-485, Feb. 2017.

4- The authors have to describe in detail how the experimental study of the proposed configuration was performed.

We appreciate your comments. In response, we have added new illustrations (Fig. 18, r-MVM test method and measurement setup) and photographs (Fig. 16, Physical interface for measurement setup) to provide a more detailed description of the evaluation circuit of the chip on pages 13 and 14.

We have also included the following text on pages 12-13 of the revised manuscript:

Fig. 16 illustrates the setup of the measurement environment and the system implementation. To maintain a low-noise measurement environment, all controllers and the MS-MAC were battery-powered. Communication was established using USB/SPI interfaces, which are standard features in commercially available FPGA boards.

The r-MVM test, as outlined in [5] and [10], is a hardware-centric method designed to assess and quantify the precision of mixed-signal processors. This technique holds particular importance in mixed-signal processing, where the accuracy of data conversion between analog and digital formats is crucial. Figure 18 visually depicts the r-MVM test methodology, providing an overview of the test process and highlighting the various stages involved in executing the r-MVM test. The implementation of the r-MVM test methodology was facilitated using MATLAB/Simulink, which enabled more efficient manipulation and testing of data sets. The study also incorporated FPGA-based controllers, which processed 192K points across three distinct chips, further enhancing the testing process.

Author Response File: Author Response.pdf

Round 2

Reviewer 3 Report

Comments and Suggestions for Authors

In this version of the manuscript, the authors have tried to implement all recommendations and remarks in the review. Therefore, I propose that the manuscript be accepted for publication in the journal.

Comments on the Quality of English Language

Minor editing of English language required.