A 3216 μm² MOS-Based Temperature Sensor with a Wide Temperature Measurement Range and Linear Readout

Abstract

This paper introduces an MOS-based intelligent temperature sensor with a linear readout. Compared with similar designs, the proposed sensor utilizes the DIBL effect to reduce the precision requirement for the voltage reference source and compensate for the temperature measurement range. A compact voltage reference circuit is introduced, which generates two reference voltage bases using only three transistors. In addition, the proposed digital readout circuit does not require a subtractor or a divider, further saving area. Fabricated in a 55 nm CMOS process, the proposed sensor occupies a compact area of 3216 $\mathsf{\mu }{\mathrm{m}}^2$. Post-simulation results show it has a maximum error of −0.52/+0.28 °C within the temperature range of −20 °C to 120 °C after two-point calibration. The power supply voltage range of the sensor is 0.8 to 1.8 V. It has a maximum voltage sensitivity of 5.7 °C/V and its power consumption is only 166 nW, with a power supply voltage of 0.8 V.

1. Introduction

Intelligent temperature sensors have found widespread application in diverse fields, encompassing hot-spot detection in large-scale systems-on-chip (SoCs), biomedical devices [1,2] and Internet of Things (IoT) devices [3,4]. Conventionally, bipolar junction transistors (BJTs) or resistors have served as the temperature-sensing elements in these sensors. While offering high measurement precision, they often occupy a significant chip area and consume considerable power [5,6]. In contrast, intelligent temperature sensors employing metal-oxide semiconductors (MOSs) as temperature-sensing elements provide advantages in area and power consumption [7,8]. Furthermore, these sensors are more suitable for integration into digital circuits. These advantages make the MOS-based intelligent temperature sensors more popular in recent research.

MOS-based intelligent temperature sensors typically leverage the temperature-dependent characteristics of MOS sub-threshold current for accurate temperature measurement. Nevertheless, due to the exponential relationship between sub-threshold current and temperature, some temperature sensors necessitate the execution of logarithmic operations to determine temperature [9,10]. Implementing a logarithm operation unit in digital circuits requires excessive power consumption and area, contradicting the original design intent of MOS-based intelligent temperature sensors.

Some studies have indicated that, under specific conditions, a nearly linear relationship can be observed between sub-threshold current and temperature. This observation has motivated the development of temperature sensors capable of delivering linear readout values [11,12,13,14]. Nevertheless, such linearity is confined to a narrow temperature range, restricting its measurement capabilities. To achieve a linear relationship between sub-threshold current and temperature, it becomes imperative to design either a low-voltage reference voltage source or a low-voltage differential reference. The voltage of a reference source is typically designed within the range of several hundred millivolts or higher [15,16,17], while a reference with lower voltages increases circuit complexity.

In this paper, we propose an innovative linear readout MOS-based temperature sensor that, compared with prior research, does not necessitate the usage of a low-voltage reference voltage source and offers a broader temperature measurement range.

2. Operation Principle

The drain current of the MOS in the sub-threshold region can be expressed as:

$$I_D=\mu C_{ox}^{\prime }\frac{W}{L}(n-1)V_t^2·exp\left(\frac{V_{GS}-V_{TH}+\lambda V_{DS}}{n{V}_t}\right)$$

(1)

where $\mu$ is carrier mobility, $C_{ox}^{\prime }$ is sheet oxide capacitance density, W and L are the width and length of the MOS, $V_{TH}$ is the threshold voltage, $\lambda$ is the drain-induced barrier-lowering (DIBL) effect coefficient, $V_{DS}$ is the drain-source voltage of the MOS, n is the sub-threshold slope, and $V_t$ is the thermal voltage given by:

$$V_t=\frac{kT}{q}$$

(2)

where k is the Boltzmann constant and q is the electron charge.

Assuming that two identical MOS transistors are interconnected in the configuration illustrated in Figure 1a, where each transistor possesses a distinct gate voltage but identical source-drain voltages, the ratio of their drain currents can be expressed, by (1), as follows:

$$\frac{I_1}{I_2}=exp\left(\frac{\Delta V_{GS}}{n{V}_t}\right)$$

(3)

where $\Delta V_{GS}=V_{GS1}-V_{GS2}$. Assuming that $x=\Delta V_{GS}/(n{V}_t$), (3) can be expressed via the Taylor series expansion as:

$$\frac{I_1}{I_2}=exp\left(x\right)=1+x+\frac{x^2}{2!}\dots \dots$$

(4)

When x approaches 0, that is, $|\Delta V_{GS}|$ is much less than $n{V}_t$, the higher-order terms of x can be neglected. (4) can be written as:

$$\frac{I_1}{I_2}=exp\left(x\right)\approx 1+x=1+\frac{\Delta V_{GS}}{n{V}_t}$$

(5)

After phase-shifting (5) and taking its reciprocal, presuming that $V_{GS2}>V_{GS1}$ and $I_2>I_1$, we can conclude:

$$\frac{I_2}{I_2-I_1}\approx -\frac{n{V}_t}{\Delta V_{GS}}=-\frac{nkT}{q\Delta V_{GS}}$$

(6)

Since $\Delta V_{GS}$ is less than 0, the term $I_2/(I_2-I_1)$ in (6) exhibits a proportional-to-absolute temperature (PTAT) characteristic. This relationship holds when $|\Delta V_{GS}|$ is much smaller than $n{V}_t$, where the value of it is approximately tens of mV. Figure 2a depicts the linear fit result of $I_2/(I_2-I_1)$ at a $\Delta V_{GS}$ of −15 mV simulated over a temperature range of −20 °C to 120 °C. The plot shows slight curvature. Figure 2b shows that the maximum temperature error, calculated according to the fit line, is 1.9 °C.

It is evident that the scheme of achieving the linear temperature readout using $\Delta V_{GS}$ possesses two inherent disadvantages:

• Obtaining a stable $|\Delta V_{GS}|$ value below 20 mV is challenging.
• The temperature measurement range is limited.

In light of these limitations, this paper proposes utilizing the DIBL effect to obtain an equivalent $\Delta V_{GS}$. As depicted in Figure 1b, the proposed design employs two identical MOSs, subject to the same $V_{GS}$ but different $V_{DS}$. Consequently, their current ratios can be formulated according to (1):

$$\frac{I_1}{I_2}=exp\left(\frac{\lambda \Delta V_{DS}}{n{V}_t}\right)$$

(7)

From this, we can derive a formula similar to that of expression (6):

$$\frac{I_2}{I_2-I_1}\approx -\frac{n{V}_t}{\lambda \Delta V_{DS}}=-\frac{nkT}{\lambda q\Delta V_{DS}}$$

(8)

Given that the value of $\lambda$ approximates 0.1 in the 55 nm process, this eliminates the necessity to maintain the differential reference voltage, $\Delta V_{DS}$, at a low level. Furthermore, the value of $\lambda q/\left(nk\right)$ exhibits minimal variation with temperature, which can compensate for the non-linearity introduced by the higher-order terms in the Taylor expansion in (8). The simulation result shows the $\lambda q/\left(nk\right)$ curve across different temperature points, as depicted in Figure 3a. Additionally, Figure 3b illustrates the linear fit image and Figure 3c is the error of $I_2/(I_2-I_1)$ from −20 °C to 120 °C when $\Delta V_{DS}$ is set at 200 mV. Simulation results reveal that this non-linear factor effectively compensates for the temperature error in Figure 2b, resulting in a reduced error of less than 0.3°C. Given that both (6) and (8) incorporate the term $\left(nk\right)/q$, and the temperature error in Figure 3c is significantly superior to that in Figure 2b, it is clear that this compensatory effect is induced by $\lambda$.

3. Circuit Implementation

The overall circuit diagram is shown in Figure 4. The voltage generator produces differential reference voltages $V_{ref1}$ and $V_{ref1}$ to provide bias voltage for the $V_{DS}$ of $M_1$ and $M_2$ via sub-threshold operation amplifiers, respectively. The $V_{ref1}$ is also used to provide the $V_{GS}$ for $M_1$ and $M_2$. The current-to-frequency converter (CFC) utilizes the structure from [11], allowing for the linear conversion of current into oscillation frequency. In the diagram, the drain currents of $M_1$ and $M_2$ are copied to CFC1 and CFC2 using current mirrors. $F_{CLK1}$ and $F_{CLK2}$ are output oscillation signals from CFC1 and CFC2, which are proportional to $I_1$ and $I_2$. The digital controller accepts $F_{CLK1}$ and $F_{CLK2}$, processes them to acquire $I_2/(I_2-I_1)$, and outputs this value via a shift register.

The circuit diagram of the voltage generator is presented in Figure 5a, generating two voltage references composed solely of three MOS transistors. Specifically, $M_t$ is a native NMOS, and $M_{r1}$ and $M_{r2}$ are two identical RVT NMOS transistors. This circuit is designed to generate two voltage references that exhibit low-temperature drift and minimal sensitivity to the supply voltage. The gate voltage of $M_t$ is lower than its source voltage, rendering $M_t$ in the sub-threshold region where its drain current is relatively small. Since the three MOSs depicted in Figure 5a share the same drain current, that is, $I_{Mt}=I_{Mr1}=I_{Mr2}$, $M_{r1}$ and $M_{r2}$ are also in the sub-threshold region. Consequently, their currents can be expressed using (1), yielding:

$$V_{ref1}=\frac{1}{2}(n{V}_{t}ln\left(\frac{W_{Mt}/L_{Mt}}{W_{Mr}/L_{Mr}}\right)+V_{TH,Mr}-V_{TH,Mt})=\frac{1}{2}{V}_{ref2}$$

(9)

Given that the term in $V_{ref1}$ containing $V_t$ possesses a PTAT characteristic, and the term containing $V_{th}$ holds a CTAT (complementary to absolute temperature) characteristic [18], by tuning the aspect ratio of the MOS, $V_{ref1}$ and $V_{ref2}$ can be temperature-independent. After adjustment, the values of $V_{ref1}$ and $V_{ref2}$ are approximately 169 mV and 372 mV, respectively. Figure 5b presents the simulation result of $V_{ref1}$ and $V_{ref2}$ from 20 °C to 120 °C under a supply voltage of 0.8 V. They have varied by a maximum of 1.7 mV and 1.8 mV. The expressions of $V_{ref1}$ and $V_{ref2}$ are unrelated to VDD, manifesting exceptional power supply rejection traits. Figure 5c displays the variations of $V_{ref1}$ and $V_{ref2}$ at 25 °C when supplied with voltages ranging from 0.8 V to 1.8 V, showing a maximum shift of 5.5 mV and 11.9 mV respectively. Due to the low drain currents of $M_{r1}$ and $M_{r2}$, both of them operate in the sub-threshold region, resulting in relatively low $V_{GS,Mr1}$ and $V_{GS,Mr2}$ values. This accounts for the low values of $V_{ref1}$ and $V_{ref2}$.

CFC, composed of three-stage delay cells, functions as a ring oscillator, generating oscillation through these cells’ charge and discharge processes. As depicted in Figure 6, the structure of the delay cell consists of a comparator operating in the sub-threshold region and a charge control circuit. Taking a delay cell in CFC1 as an example, $V_{in}$ is connected to $V_{out}$ of the previous stage. Assuming the voltage of $V_{in}$ and node A is zero initially, $M_{d5}$ and $M_{d8}$ are off, and $M_{d6}$ is on, enabling the charging process, and $V_{out}$ is at a low level. $M_{d10}$ copies current from $M_1$ and charges $C_{d1}$. When the voltage at node A is below $V_{ref2}$, node B remains low; after the voltage exceeds $V_{vref2}$, node B and $V_{vout}$ toggle. $M_{d7}$ and $M_{d9}$ form a common-source amplifier, enhancing the slew rate at $V_{out}$. Then, when the previous stage also toggles, $V_{in}$ becomes high, turning off $M_{d6}$ and turning on $M_{d5}$ and $M_{d8}$. These transistors discharge $C_{d1}$ and enable a rapid toggle of $V_{out}$, thus completing a charge and discharge cycle. Consequently, the delay time of a single charge–discharge cycle in the delay cell can be expressed as:

$$t_d=\frac{C_{d1}{V}_{ref2}}{I_1}$$

(10)

The CFC consists of three-stage delay cells, and its oscillation frequency can be written as:

$$F_{CLK1}=\frac{1}{3t_d}=\frac{I_1}{3C_{d1}{V}_{ref2}}$$

(11)

Similarly, $F_{CLK2}$ can be expressed as:

$$F_{CLK2}=\frac{I_2}{3C_{d1}{V}_{ref2}}$$

(12)

Hence, the oscillation frequency of the CFC is proportional to the bias current, and the subsequent equation can be derived according to (8), (11), and (12):

$$\frac{F_{CLK2}}{F_{CLK2}-F_{CLK1}}=-\frac{1}{3C_{d1}{V}_{ref2}}·\frac{nkT}{\lambda q\Delta V_{DS}}$$

(13)

Based on (13), it can be concluded that $F_{CLK2}/(F_{CLK2}-F_{CLK1})$ exhibits a linear relationship with temperature.

To ensure minimal power consumption, $M_{d1}$ and $M_{d2}$ within the sub-threshold comparator are required to operate in the sub-threshold region. Furthermore, to decrease the comparator’s operating current, HVT MOS transistors are utilized for $M_{d1}$ and $M_{d2}$. The magnitude of the reference voltage at the gate of $M_{d1}$ has a substantial influence on the power consumption of the sub-threshold comparator. Figure 7 depicts the average current consumption of the comparator as the reference voltage ranges from 300 mV to 600 mV, applying a supply voltage of 0.8 V. It is evident that, while the current consumption is extremely low at a reference voltage of 300 mV, it escalates significantly as the reference voltage increases. The proposed design employs $V_{ref2}$ as the gate voltage for $M_{d1}$, which is less than 400 mV, according to Figure 5. Once the voltage at node A reaches $V_{ref2}$, the comparator flips, resulting in a rapid discharge of $C_{d1}$. Consequently, the voltage at node A does not exceed $V_{ref2}$, thereby ensuring that the delay cell operates within the sub-threshold region and sustains minimal power consumption.

The block diagram of the digital controller is depicted in Figure 8. The CLK1 frequency outputted by CFC1 is lower than the CLK2 frequency outputted by CFC2. CLK1 serves as the clock signal for a D-flip-flop (DFF), which toggles its output signal in each cycle. This signal passes through the clock synchronizer and undergoes edge detection in the CLK2 clock domain, where a rising edge or falling edge each signifies a single oscillation of CLK1.

There are two counters in the digital controller: CNT_DIFF and CNT2. The CNT2 counter records the oscillation times of CLK2. The CNT_DIFF counter, on the other hand, registers the frequency differences between the two oscillations. When counting is over, the value of CNT2 is processed by a shift register and output through DOUT.

Figure 9 illustrates the timing diagram representation when the ratio $F_{CLK1}$:$F_{CLK2}$ is 1:4. CLK1 undergoes frequency division, clock synchronization, and edge detection, subsequently transforming into a pulse signal within the CLK2 clock domain. The counting process is initiated when the START signal is pulled high and a CLK1_SYNC pulse is detected. In each CLK2 cycle, CNT2 increments by one. Similarly, in a CLK2 cycle in the absence of a CLK1_SYNC pulse, CNT_DIFF increases by one. However, in the CLK2 cycle when a CLK1_SYNC pulse is received, CNT_DIFF ceases to count. At this juncture, the effective count is CNT_DIFF = CNT_DIFF + 1 − 1, a counting methodology that presents for the computation of $F_{CLK2}-F_{CLK1}$. Upon reaching a count of 4096 by CNT_DIFF, the counting process concludes, triggering the STOP signal to be high and the value of CNT2 to be outputted.

In a clock synchronization circuit, the frequency of the sampling clock must be three times or more the frequency of the sampled signal to guarantee signal integrity. As the DFF in the digital controller functions as a frequency divider, it oscillates at half the frequency of CLK1. Consequently, to ensure proper synchronization in the clock synchronizer within the digital controller, the frequency of CLK2 must exceed one and a half times the frequency of CLK1. It means that $I_2/(I_2-I_1)$ needs to be less than 3, and Figure 3b shows that $I_2/(I_2-I_1)$ is always below 2.6. Thus, in the digital controller, the clock synchronizer can accurately synchronize the DFF output signal from the CLK1 clock domain to the CLK2 clock domain without distortion.

The digital controller exhibits the following advantages:

• The value of CNT_DIFF is fixed at 4096 upon the completion of counting, thus $F_{CLK2}/(F_{CLK2}-F_{CLK1})$ can be represented as CNT2/4096. Therefore, it is only necessary to output the value of CNT2, which inherently exhibits PTAT characteristics. This approach eliminates the need for a digital divider.
• The conventional approach to compute $F_{CLK2}/(F_{CLK2}-F_{CLK1})$ entails designing CNT1 and CNT2 to, respectively, represent $F_{CLK1}$ and $F_{CLK2}$, followed by obtaining $F_{CLK2}-F_{CLK1}$ through CNT2-CNT1. However, the proposed circuit utilizes the logic of CNT_DIFF to present the value of $F_{CLK2}-F_{CLK1}$, thereby eliminating the step of calculating CNT2-CNT1. This consequently reduces the area and power consumption required for the subtractor.

4. Simulation Results

The proposed sensor, designed using a 55 nm process, is depicted in the layout shown in Figure 10. The analog and digital parts only span areas of 1657 $\mathsf{\mu }{\mathrm{m}}^2$ and 1559 $\mathsf{\mu }{\mathrm{m}}^2$, respectively.

Two hundred Monte Carlo analyses vs process variations were performed under a supply voltage of 0.8 V. Figure 11a and Figure 11b represent the output value of CNT2 and the temperature error after two-point calibration, respectively. The maximum error in the temperature range from −20 °C to 120 °C after two-point calibration in the Monte Carlo analysis is only −0.64/+0.57 °C.

Post-simulation of the circuit was conducted within five process corners: tt, ss, ff, snfp, and fnsp. Figure 12a shows CNT2 values from −20 °C to 120 °C, with a power supply voltage of 0.8 V. Since $F_{CLK2}/(F_{CLK2}-F_{CLK1})=CNT2/4096$, $F_{CLK2}/(F_{CLK2}-F_{CLK1})$ is always below 3, this ensures that there is no distortion occurring in digital sampling. Figure 12b represents the temperature error after two-point calibration for results in Figure 12a. The maximum temperature error recorded is −0.52/+0.28 °C.

In the proposed design, the $V_{DS}$ of $M_1$ and $M_2$ is supplied by $V_{ref1}$ and $V_{ref2}$, and the temperature output value is the ratio of $I_2$ to $I_2-I_1$. It endows the temperature sensor with a high-voltage suppression characteristic. Figure 12c displays the temperature inaccuracy at power supply voltages of 0.8 V, 1.2 V, 1.5 V, and 1.8 V at 20 °C. The maximum supply sensitivity can be calculated from Figure 12c as 5.7 °C/V.

Owing to most of the transistors in the analog part of the circuit operating in the sub-threshold region, and the clock frequency of the digital circuit being relatively low, the proposed circuit exhibits commendable power consumption performance. In the tt corner, at 25 °C with a power supply voltage of 0.8 V, the power consumption is only 166 nW.

Table 1. Performance comparison with state-of-the-art MOS-based temperature sensors.

	This Work 1	[10] 2	[13]	[14]	[19]	[20]	[21]
Type	MOS	MOS	MOS	MOS	MOS	Resistor	BJT
Process (nm)	55	55	65	130	180	28	180
Supply (V)	0.8~1.8	0.8~1.3	0.75~1.05	0.9~1	0.5	0.9	0.95~1.4
Power (nW)	166	860	6.4	196	976.4	12,500	810
Area ($\mathsf{\mu }{\mathrm{m}}^2$)	3216	2400	320,000	70,000	20,400	9200	250,000
Calibration	2	2	2	2	2	2	1
Temp. range (°C)	−20~120	−40~85	−30~70	0~80	−40~125	−40~100	−55~125
Inaccuracy (°C)	−0.52/+0.28	±0.25 3	−1.0/+0.7	−0.4/+0.44 3	−0.9/+0.88	−0.62/+0.81	±0.15
Relative inaccuracy (%)	0.57	0.4	1.7	1.1	1.07	1.02	0.16
Conv. time (ms)	156	1.04	765	59	0.1	0.404	128
Resolution (mK)	58 5	17	75	100	220	56.5	1.8
Resolution FoM 4 (pJ·K2)	86.9 5	0.26	27	120 5	4.73	51.9	0.34
Line sensitivity (°C/V)	5.7	5.8	2.8	13.7	∖	∖	0.2
External ref.	No	Yes	Yes	No	No	No	Yes
Linear readout	Yes	No	Yes	Yes	Yes	Yes	Yes

¹ The performance of the proposed work is based on post-simulation results whereas other compared work is based on chip test results. ² It requires logarithmic operations to be performed off-chip. ³ This accuracy is achieved by off-chip non-linearity correction. ⁴ Resolution FoM = (energy/conversion) × (resolution)². ⁵ Counter resolution is used here.

compares the proposed sensor with state-of-the-art temperature sensors. While conventional sub-threshold-current-based temperature sensors may slightly outperform the proposed sensor regarding temperature error and area [10], they require off-chip logarithmic computations for readout data and systematic error correction of measurement outcomes. In contrast, compared with similar sub-threshold-current-based sensors with linear readout values [13,14], the proposed sensor offers a broader temperature measurement range and occupies a significantly smaller area due to its lower voltage reference requirements. Additionally, compared with MOS temperature sensors based on gate-source voltage [19], the proposed sensor demonstrates superior performance in both area efficiency and temperature accuracy, along with enhanced power supply sensitivity characteristics. Furthermore, compared with traditional temperature sensors based on resistors or BJTs [20,21], the proposed sensor provides substantial advantages in terms of area and power consumption.

5. Conclusions

In this paper, an intelligent MOS-based temperature sensor that features a linear readout is presented. The current bias circuit of the sensor is designed utilizing the DIBL effect, which broadens the temperature measurement range and simplifies the design of the reference voltage source. The circuit is fabricated in a 55 nm CMOS process, and the total area of the sensor is 3216 $\mathsf{\mu }{\mathrm{m}}^2$. Simulation results indicate an error of −0.52/+0.28 °C at a temperature range of −20 to 120 °C, with a voltage sensitivity of 5.7 °C/V. The circuit’s power consumption is 166 nW.