Hybrid Quantum-Dot Cellular Automata Nanocomputing Circuits

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

This paper proposed a hybrid quantum dot nano computing circuit utilizing a logic system.

This research can be a interesting subject in the field of integrated circuit design, but, some of questions have to be addressed.

 

1. This work is implemented in tool level, not real implementation. Could you explain the reliability issue and verification methods for this work.

2. The gate symbol of Figure 3 can be seen as the DAC symbol. It can be confused to readers.

3. What is the main strength of QCA comparing to the conventional CMOS logic circuit?

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The proposed work is interesting, but in my opinion the novelty of the paper is not demonstrated. This is my main major review. Even if some references are presented and compared to the proposed design method, in state it is not enough. Some papers have been done several years ago on the same method such as V. Pudi and K. Sridharan, "Efficient Design of a Hybrid Adder in Quantum-Dot Cellular Automata," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 9, pp. 1535-1548, Sept. 2011, doi: 10.1109/TVLSI.2010.2054120.

The authors should justify the novelty of their work prior publication.

 

Please find below some other minor reviews: 

The figures (figure 8, 9, 10, and 11) with the waveforms are not readable. Moreover, the axises are not named and there is no unit.

Figure 13: circuit cost is not defined and not unit is provided.

 

Comments on the Quality of English Language

no remark

Author Response

Please see the attachment.

Author Response File: Author Response.pdf