Effects of a Spike-Annealed HfO₂ Gate Dielectric Layer on the On-Resistance and Interface Quality of AlGaN/GaN High-Electron-Mobility Transistors

Abstract

Various high-k dielectrics have been proposed for AlGaN/GaN MOSHEMTs for gate leakage and drain-current collapse suppression. Hafnium oxide (HfO₂) is particularly interesting because of its large bandgap, high dielectric constant, and ferroelectricity under specific phase and doping conditions. However, defects and surface scattering caused by HfO₂ dissimilarity and degraded HfO₂/GaN interface quality still leave the challenge of reducing the SS and R_on. In this study, we investigated the effects of the first spike-annealed HfO₂ (6 nm) layer, compared with the conventional ALD-HfO₂ (6 nm) layer in the HfO₂ bilayer gate dielectric structure on AlGaN/GaN HEMTs. Both devices exhibit negligible hysteresis and near-ideal (~60 mV/dec) subthreshold slopes of more than three orders of magnitude. The device with the first annealed HfO₂ layer exhibited a reduced R_on with notably less gate bias dependency and enhanced output current. On the other hand, the capacitance–voltage and conductance methods revealed that the border and interface trap densities of the device were inferior to those of the conventional HfO₂ layer. The trade-off between enhanced electrical performance and oxide traps is discussed based on these results.

1. Introduction

Gallium nitride (GaN)-based high-electron-mobility transistors (HEMTs) have emerged as compelling candidates for high-power and radio frequency (RF) applications, leveraging their superior attributes, including their high electron mobility and robust breakdown fields. III-Nitrides (InN, GaN, and AlN) have been previously investigated for their intrinsic spontaneous polarization and piezoelectricity, augmenting the appeal of GaN-based HEMTs [1,2,3]. These distinctive material characteristics have propelled extensive research and commercialization efforts, leading to the widespread adoption of AlGaN/GaN-based HEMTs in high-frequency and high-power applications [4,5,6,7]. Over the past two decades, AlGaN/GaN-based HEMTs have gained increased attention and commercialization by harnessing the exceptional intrinsic material properties of III nitrides [8,9,10].

Despite the many advantages of AlGaN/GaN HEMTs, suppressing gate leakage and isolating an AlGaN surface from the surrounding environment remain challenging when optimizing the performance of AlGaN/GaN HEMTs [11,12,13]. To overcome the shortcomings of conventional AlGaN/GaN HEMTs, a metal-oxide semiconductor (MOS) AlGaN/GaN HEMT has been proposed and investigated. The dielectric layer not only prevents gate leakage but also isolates the AlGaN surface from the surrounding environment, promoting reliability [14,15]. Since the introduction of the AlGaN/GaN MOS-HEMT structure, many studies have searched for promising building materials. Notably, high-k dielectric materials have the potential to increase physical thickness, owing to their high dielectric constants, and reduce the tunneling leakage current [16,17,18,19]. Among high-k dielectric materials, HfO₂ is particularly attractive because of its unique characteristics. It is well known that HfO₂ not only possesses a high dielectric constant, but also induces ferroelectricity under specific conditions, in which the implementation of a dopant or annealing at high temperatures is applied [20,21,22,23].

The current collapse and low switching speed of AlGaN/GaN MOS-HEMTs, determined by the poor subthreshold slope (SS) and high on-resistance (R_on), significantly impact its power efficiency degradation [7,24,25]. Although harnessing HfO₂ in AlGaN/GaN MOS-HEMTs is promising for mitigating the aforementioned problems, defects, and surface scattering caused by HfO₂ dissimilarity, and host materials still present the challenge of reducing the SS and R_on [15,26]. Consequently, the requirement for the introduction of additional steps to enhance the interface quality of HfO₂/AlGaN results in the exploitation of the spiking annealing process [12]. As previously reported, the spiking annealing process enables the device to have a low SS and a simple fabrication process. Nevertheless, owing to a thick HfO₂ layer of ~60 nm and a non-optimized fabrication process, spike-annealed HfO₂-based AlGaN/GaN MOS-HEMTs are responsible for the low drain current and high R_on [21].

In this study, we investigated the effects of the first annealed HfO₂ (6 nm) layer compared to the conventional ALD-HfO₂ (6 nm) layer in the HfO₂ bilayer gate dielectric structure on AlGaN/GaN HEMTs. Spike annealing was conducted on the first HfO₂ layer, and a capping HfO₂ (10 nm) layer was formed to suppress gate leakage into the gate electrode. The transfer length method (TLM) and direct-current (DC) characterizations were conducted to compare the channel conductivity and electrical performance. Furthermore, the conventional frequency-dependent capacitance–voltage was measured to compare the hysteretic behavior and border traps. Finally, the conductance method was employed to evaluate the interface traps in both bilayers with AlGaN, and the interface trap density and trap lifetime were extracted and compared.

2. Device Fabrication and Characterization

Figure 1a shows a cross-sectional schematic of the fabricated AlGaN/GaN MOSHEMT, with an HfO₂ bilayer. The AlGaN/GaN heterostructure was grown via metal–organic vapor deposition (MOCVD) on a 2 in silicon substrate. The structure consists of a 3 nm GaN cap layer, 25 nm Al_0.26Ga_0.74N barrier, 1 nm AlN interlayer, 2 μmm GaN channel layer, and 1 μmm buffer layer. The room temperature Hall mobility and sheet carrier concentration were >1300 cm²/Vs and ~10¹³ cm⁻², respectively. The fabrication began with mesa isolation via an inductively coupled plasma reactive ion etching (ICP-RIE) system using mixed BCl₃/Cl₂ gas. For ohmic contact, a Ti/Al/Ni/Au metal stack was deposited through e-beam evaporation and annealed using a rapid thermal annealing system at 830 °C for 30 s in an N₂ environment. Subsequently, 6 nm of HfO₂ was deposited via atomic layer deposition (ALD) with a tetrakis (ethylmethylamino) hafnium (TEMAH) precursor and ozone reactants at a stage temperature of 350 °C [27]. Then, thermal annealing at 650 °C for 30 s in an N₂ environment was conducted to improve the interface [18,28,29]. This additional annealing was not performed on the other control devices. To minimize gate leakage through the grain boundaries of the 6 nm HfO₂ layer, an additional 10 nm thick HfO₂ dielectric layer was deposited under the same ALD conditions. No final passivation layer was applied on top of the HfO₂ layer. ICP-RIE was conducted to open the S/D contacts. Finally, a Ni/Au gate electrode was deposited using an e-beam evaporation system. The gate length, channel length, and channel width were 8, 35, and 120 μm, respectively. Figure 1b shows the main steps of the fabrication process. All electrical measurements were conducted using a semiconductor parameter analyzer with a pre-amp (Keithley-4200A-SCS). An HP4284A LCR meter was used to characterize the capacitance and conductance.

3. Results and Discussion

TLM measurements were conducted to compare the contact resistance (R_c) of the S/D metal scheme, as well as the sheet resistance (R_sh) of devices A and NA. The total resistance (R) for variable gap spacings between 4 and 10 µm was calculated from the I_DS–V_DS curves shown in Figure 2a,b for devices A and NA, respectively. Subsequently, R_c, R_sh, and contact resistivity (ρ_c) were extracted from the slopes and y-intercepts of a linear fit on the results, as shown in Figure 2c,d. The R_sh of device A decreased from 783 to 544 Ω/□,compared with that of device NA, while its R_c increased from 3.01 to 3.41 Ω·mm. The high-temperature annealing process induced the polycrystallization of the HfO₂ layer (6 nm), and generated additional charges within the layer, resulting in an increased carrier density in the 2DEG channel. Therefore, the channel conductivity improved, and R_sh decreased for device A.

Further direct comparison was conducted based on the transfer and output characteristics. Device A exhibited an overall improvement in device performance, with a lower R_sh in the channel layer. Figure 3a,b show the bidirectional I_DS–V_GS transfer curves for the log and linear scales at V_DS = 1 and 10 V, respectively. Negligible hysteresis was observed for both devices A and NA, and the gate leakage was well suppressed for both V_DS = 1 and 10 V during the sweep. The peak field–effect mobility of devices NA and A was estimated to be 1252 cm²/V·s and 1401 cm²/V·s, respectively, at V_DS = 1V. Using a linear extrapolation method at the forward sweep, V_th of −3.92 V and −3.74 V was extracted at V_DS = 1 V and 10 V, respectively, for device NA. In the case of device A, the V_th of −4.26 V and −4.01 V was extracted at V_DS = 1 V and 10 V, respectively. The transfer curves of device A shifted in a negative direction compared to those of device NA due to the increase in the electron density of 2DEG. Also, R_on was reduced, which is particularly advantageous for power-switching applications. The amount of V_th shift was approximately −0.3 V for both V_DS = 1 and 10 V. This result stems from the generation of positive fixed charges after the annealing process of the 6 nm HfO₂ layer [30,31]. To further investigate the electrical characteristics of both devices, the SS was extracted using the following equation:

$$SS=\frac{\partial V_{GS}}{\partial \log \left(I_{DS}\right)} .$$

(1)

Figure 3c,d show the SS in the forward and reverse sweeps for both devices, exhibiting near 60 mV/dec, which is referred to as the Boltzmann limit, owing to the abrupt interface between the AlGaN and the 6 nm thick HfO₂ layer [12]. For both devices, nearly 60 mV/dec SS was maintained for more than three orders of magnitude of I_DS during the sweep. Figure 3e shows the output characteristic of devices A and NA measured for V_GS ranging between −6 and 1 V with a 1 V step. Device A exhibited higher output currents than device NA for the same gate bias. In addition, the on-resistance (R_on) for variable V_GS was extracted from the measured output curves to compare the R_on characteristics, as shown in Figure 3f. Initially, the R_on of device NA decreased as V_GS increased, because of the channel conductivity enhancement. As V_GS further increased, R_on saturated to a particular value, indicating that R_on was mainly limited by the resistance of the drift region. In contrast, device A exhibited a lower R_on, with negligible variation in the measured V_GS range, owing to the enhanced channel conductivity, as observed earlier from the reduced R_sh, as well as negatively shifted V_TH. These results show that spike-annealing can enhance electrical performance, such as lower R_on, which could contribute to high performance and low static power dissipation in RF applications. However, because charge trapping effects within different layers of the AlGaN/GaN HEMT structure can affect RF performance [32], further investigation of the interface quality of the HfO₂/AlGaN interface is needed.

Figure 4a,b show the frequency-dependent capacitance–voltage (C–V) curves of devices A and NA for comparison with the HfO₂/AlGaN interface. A typical two-step response in the C–V curves corresponding to 2DEG at the AlGaN/GaN interface and electrons accumulated at the AlGaN/HfO₂ bilayer interface was observed. The first slope, which was formed by the AlGaN/GaN interface, exhibited a similar quality. Compared with device NA, device A exhibited a less dispersed oxide capacitance (C_ox) at the second slope, owing to the further crystallization of the HfO₂ layer (6 nm) after the annealing process. Figure 4c shows a comparison of the extracted C_ox from the second slopes for a frequency range of 1 kHz to 1 MHz; the C_ox of device A shows less frequency dependency. Based on the extracted C_ox and amount of flat band voltage shift (ΔV) for device A, the calculated border trap densities (N_it) are presented in Figure 4d. Device A exhibits a higher N_it than device NA because of the oxide defects, including interface traps at the second HfO₂ (6 nm)/HfO₂ (10 nm) interface. During double-voltage sweeps, a high positive gate bias induces the capture and release of electrons by the traps at the second interface, owing to the increased dipole-induced band bending, which functions as an active trap [33]. The HfO₂ bilayer of device A had a higher dipole density at the interface than the homogeneous HfO₂ bilayer of device NA [23,30].

Subsequently, the conductance method was adopted to further investigate the interface traps at the first and second interfaces. The conductance method is based on measuring the normalized equivalent parallel conductance (G_p) of a MOS capacitor as a function of gate bias voltage and frequency, and it is extensively used to determine interface trap density (D_it) [34]. The AC conductance (G_m) and capacitance (C_m) from the C–V measurements were used to calculate the normalized equivalent parallel conductance (G_p) as follows:

$$\frac{G_P}{\omega }=\frac{\omega G_m{C_{ox}}^2}{G_m^2+{{\omega }^2({C_{ox}}^2-C_m)}^2},$$

(2)

where C_ox is the oxide capacitance and w is the angular frequency [19]. Figure 5a,b show the extracted G_p as a function of w for the first slope, while Figure 5c,d show the G_p corresponding to the second slope. Clearly, the G_p extracted from the second slope exhibits a discrepancy between devices A and NA. Device A shows a larger variation in the conductance peak, indicating electron trapping and detrapping at the AlGaN/HfO₂ bilayer interface. The interface trap time constant (τ_T) and D_it were respectively determined by fitting the following equations to the G_p/w curves:

$${\tau }_T=\frac{1}{\omega }={\left({\sigma }_T{N}_C{\nu }_T\right)}^{-1}exp\left(\frac{E_C-E_T}{kT}\right),$$

(3)

$$D_{it}={\left(\frac{G_p}{\omega }\right)}_{peak}\times \left\{1+{\left(\omega {\tau }_T\right)}^2\right\}\times \frac{1}{q\omega {\tau }_T}.$$

(4)

Figure 6a shows the calculated D_it as a function of ΔE, which is the difference between trap level energy (E_T) and the conduction band energy (E_C) [19]. Both devices exhibit a similar trend of shallow trap density corresponding to the AlGaN/GaN interface [15,23]. However, device A had a higher deep-trap density than device NA, indicating a higher trap density at the AlGaN/HfO₂ bilayer induced by the additional annealing process [23]. Figure 6b shows the extracted shallow trap τ_T from the AlGaN/GaN interface; no discrepancies were observed between the two devices. However, the deep-trap density τ_T from the AlGaN/HfO₂ bilayer exhibits a clear discrepancy; τ_T from device A is three times shorter than that from device NA for the studied V_GS range, as shown in Figure 6c. The trap lifetime at the second interface of device A was shorter than that of device NA, which is attributed to the larger D_it of device A [19]. Since the highly crystallized HfO₂ layer induced by spike-annealing increases the leakage current through the materials, more carriers in device A can penetrate the insulator from 2DEG and increase trapping probability. Consequently, the deep-trap density for device A is larger than device NA. Moreover, the increased dipole-induced band bending at the HfO₂ interfaces in device A contributes to the activation of additional trap states [33], further shortening the trap lifetime. Although device A exhibits a superior static electrical performance, its increased trap density and shorter trap lifetime indicate that transient responses, including dynamic R_on, could be more affected by charge trapping effects in comparison with device NA. This result highlights the importance of optimizing the annealing process to balance both static and dynamic characteristics for switching applications [35]. Time constant and trap density can be changed by annealing processes, and thus they could be controlled by optimizing the conditions of spike-annealing [36].

4. Conclusions

In summary, we investigated a spike-annealed HfO₂ (6 nm)/HfO₂ (10 nm) bilayer gate dielectric for an AlGaN/GaN HEMT and compared it with a conventional HfO₂ (6 nm)/HfO₂ (10 nm) bilayer. Both devices exhibited negligible hysteresis and near-ideal (~60 mV/dec) SS for more than three orders of magnitude of I_DS during the gate sweep, which is attributed to the high-quality AlGaN/HfO₂ interface. According to the TLM analysis results, the annealed first HfO₂ layer increased the carrier density in the 2DEG channel, and thus decreased R_sh from 783 to 544 Ω/□. Consequently, the device with the first annealed HfO₂ layer exhibited a notably reduced R_on, with less gate bias dependency and enhanced output current compared with the conventional ALD-HfO₂ layer. Unlike the enhanced overall electrical performance, the border trap density of the device with the first annealed HfO₂ layer was determined to be inferior, owing to the increased dipole-induced band bending, which functions as an active trap, at the second HfO₂ (6 nm)/HfO₂ (10 nm) interface. Moreover, a higher interface trap density and shorter trap lifetime were verified using the conductance method. These results show that the first crystallized HfO₂ (6 nm) layer, obtained via annealing, can enhance the channel conductivity, and other aspects of electrical performance. Further research on bilayer gate dielectric structures for AlGaN/GaN HEMTs is needed to avoid compromising the interface quality.