1. Introduction
In modern electronics, temperature sensing is a fundamental aspect that underpins the performance, reliability, and safety of numerous devices and systems. From industrial process control to microprocessors and consumer electronics, the accurate measurement of temperature is essential for maintaining optimal operation and preventing catastrophic failures [
1].
Smart temperature sensors are essential in the design and operation of Application-Specific Integrated Circuits (ASICs) due to their ability to provide precise information to other acting circuits which can then perform thermal management. These sensors help maintain optimal operating temperatures, which is crucial for the performance and reliability of ASICs. Overheating can lead to thermal throttling, reduced efficiency, and potentially permanent damage to the circuit. By continuously monitoring the temperature, smart sensors allow for dynamic adjustments, such as modulating clock speeds or power delivery, to prevent overheating. This ensures that ASICs operate within their specified temperature ranges, enhancing their longevity and stability. Thus, smart temperature sensors contribute significantly to both the quality and reliability of ASICs throughout their lifecycle. As technological advancements continue to push the boundaries of miniaturization and integration, the demand for highly precise and compact temperature sensors has intensified. In response to this need, researchers and engineers have endeavored to develop innovative solutions capable of delivering exceptional accuracy, reliability, and efficiency [
2,
3,
4,
5].
As previously said, there is the need for robust temperature sensing solutions in a wide range of applications. Accurate temperature monitoring is essential for optimizing the performance and longevity of electronic equipment, ensuring compliance with regulatory standards, and enhancing user experience in consumer products. One of the critical challenges in temperature sensing is achieving high accuracy across a broad range of operating conditions. Traditional temperature sensors often struggle to maintain precision in extreme environments or exhibit significant errors due to variations in process, voltage, and temperature (PVT) [
6]. Moreover, the quest for low-area and low-power integrated circuits (ICs) adds further complexity to sensor design, necessitating novel architectures and techniques to address these constraints effectively. Two of the most important performances of a smart temperature sensor are accuracy and conversion speed. In smart temperature sensors, there is often a trade-off between these two performances. High accuracy means the sensor can measure temperature very precisely, which is essential for applications requiring exact temperature control, such as in medical or scientific equipment. However, achieving this high accuracy typically requires more time for each measurement, as the sensor may need to average multiple readings or perform complex calibrations to reduce noise and enhance precision.
On the other hand, fast conversion speed allows the sensor to provide real-time temperature readings, which is crucial for dynamic systems like HVAC controls or automotive applications. However, increasing the speed of conversion can introduce more noise and reduce the accuracy of the measurement. Manufacturers of smart temperature sensors often need to balance these two factors, optimizing the design to meet the specific needs of the application, whether it prioritizes rapid updates or precise measurements. The objective of this work is to achieve a very high accuracy but with smaller conversion times than typical smart sensors with the same accuracy [
7,
8].
In this context, the present paper introduces an advancement in temperature sensing technology by proposing a ±0.15 °C (considering 3σ) error CMOS smart temperature sensor across a broad range of temperatures (−40 °C to 125 °C) and implemented in a 65 nm CMOS technology. This sensor leverages dynamic element matching (DEM) techniques and chopping in order to mitigate the effects of noise, nonlinearity, and process variations inherent in CMOS-based sensors and obtain such a high accuracy. Since all the primary sources of error are reduced to a 0.01 °C level, in this temperature sensor, the primary source of error stems from the variability in the characteristics of the bipolar transistors [
2]. Hence, calibration at a single temperature proves adequate to identify and rectify this error through trimming. Given the essentially unidimensional nature of this variability, the correction remains effective across the entire operational spectrum.
Central to the functionality of the smart temperature sensor is the sigma–delta (Σ∆) analog-to-digital converter (ADC), which operates differently from traditional converters. Instead of directly converting the incoming analog signal into a digital sample of n-bit precision at the Nyquist rate, they employ oversampling. This means the analog signal is sampled at a much higher rate, denoted as fN, where fN << fS (with oversample rates like 16, 32, 64, or 128 being common). During oversampling, the ADC captures the analog signal at a lower precision (coarser quantization), often effectively functioning as a 1-bit ADC (as in our case). The output of the modulator or 1-bit ADC is a bitstream (bs). The density of the ones in this stream correlates with the magnitude of the sine-wave input. The 1-bit ADC stream undergoes digital filtering to derive an n-bit representation of the analog input. Put simply, the 1-bit ADC stream is summed over N sampling cycles and then divided by N. This process produces a decimated value, representing the average value of the bitstream from the modulator [
3]. The circuit that performs such decimated value is called a decimator filter. The output of the decimator can then be converted to temperature; hence, the Σ∆ ADC (modulator and the decimator) operates as a voltage to temperature converter.
The Σ∆ modulator needs to feed several bits to the decimator filter in order to achieve sufficient resolution. This will therefore increase the number of cycles that the Σ∆ needs to run in order to achieve a good temperature resolution and therefore accuracy. This time is known as conversion time. In order for obtain fast conversion times, higher sampling rates can be used, second-order Σ∆s [
4], or higher order decimation filters can be used [
5]. However, each of those solutions has its cost in design complexity, power consumption and area. Hence, the relationships among complexity, power consumption, and area are difficult to manage, and novel approaches must be followed in order to minimize all previous parameters. However, this is never trivial in circuit design.
Hence, in order to improve the conversion speed while keeping the area, power consumption, and design complexity to a minimum, in our work, we have developed a novel adaptative decimation filter which is able to dynamically adjust the number of cycles used for the decimation in order to keep topmost accuracy without resorting to extra area, power or increasing the design complexity of the analog circuits, like using a higher-order Σ∆. This adaptive feature distinguishes the proposed sensor from conventional temperature sensors, which often rely on fixed or predetermined filtering strategies that may compromise accuracy or efficiency in dynamic environments. This adaptative decimation filter will be explained in detail in
Section 3.
The remainder of this paper is organized as follows:
Section 2 discusses the basics of smart temperature basics.
Section 3 presents the implementation details of the proposed smart temperature sensor, and
Section 4 showcases the performance characteristics and capabilities of the smart temperature sensor through comprehensive pre- and post-layout simulations. Finally,
Section 5 draws the conclusions.
2. Smart Temperature Sensor Basics
To obtain a digital temperature reading, a comparison measurement must be performed, comparing a temperature-dependent signal with a reference signal. Although most devices exhibit temperature-dependent characteristics and could ideally be used for such purpose, bipolar transistors are especially well-suited for that [
6]. They can produce both a voltage proportional to absolute temperature (PTAT) and a temperature-independent bandgap reference voltage. In CMOS technology, substrate bipolar transistors can fulfil this role effectively.
Figure 1 depicts the operational concept of a temperature sensor. It employs two diode-connected substrate PNP transistors to generate two voltages, V
BE and ∆V
BE. These voltages are then combined to create the necessary PTAT and reference voltages [
2]. Subsequently, these voltages are converted into a digital temperature reading through an ADC thus generating a temperature reading in a digital format D
OUT.
The base-emitter voltage of a bipolar transistor in its forward-active region can be described by the following well-known logarithmic equation:
where
k, is the Boltzmann constant,
q is the electron charge,
T is the absolute temperature, I
S the transistor saturation current, and I
BIAS is its collector current, determined by a bias circuit [
2]. It is well known that the bipolar transistor saturation current highly depends on the temperature, hence the base-emitter voltage exhibits a negative temperature coefficient of around −2 mV/°C. And it can also be shown that for two bipolar transistors operating with a collector current ratio of 1:p, the ∆V
BE can be given by the following:
Hence, ∆V
BE only depends on the ratio of currents p, making it an accurate measure of temperature. A larger current ratio p results in a larger ∆V
BE, but the designer must ensure that the two transistors remain in the same operating region [
1]. In this work, a current ratio p of 5 is used, resulting in a temperature coefficient of ~0.14 mV/°C. For the ADC, a 1.2 V bandgap voltage can be used to digitize ∆V
BE. Such reference is generated by adding an amplified version of ∆V
BE to V
BE so as to obtain a temperature-independent voltage V
REF as follows:
In order to obtain a V
REF = 1.2 V, the necessary
is 14. However, in our design, since we are operating with V
DD = 1.8 V, we have reduced the V
REF to around 0.4 V so that the Σ∆ does not saturate. This was performed by properly designing the number of capacitances in the charge balancing Σ∆. The ADC then converts the ratio of
·∆V
BE and V
REF in order to obtain a digital reading D
OUT as follows:
where the coefficients A and B are chosen so as to obtain a digital output in degrees Celsius [
1]. In our design, these coefficients are chosen to be around 600 and 273, respectively.
3. Proposed Temperature Sensor
Figure 2 shows the block diagram of the sensor. The front-end is constituted by a bias circuit, that generates a PTAT voltage (with an I
BIAS current) and a bipolar core that generates the voltages ∆V
BE and V
BE. These voltages serve as inputs to the Σ∆ modulator, which produces a bitstream
bs, which average value is equal to the ratio between α·∆V
BE and V
REF. The converter uses a charge-balancing scheme which will be detailed in
Section 3.2. To filter the quantization noise from the bitstream and achieve the required scaling as outlined in Equation (3), a decimation filter is utilized.
3.1. Biasing Circuitry
Figure 3 shows the bias circuit of the front end, used to generate a PTAT current and V
BIASP. While some variance in the absolute value of the bias current can be accepted since it can be trimmed, it is crucial to minimize other sources of error in the bias current, such as fluctuations with the supply voltage and temperature dependence. Typically, bias current is obtained from a bias voltage through a resistor. Opting for a bias voltage derived from the difference in base-emitter voltage is favorable because, as previously mentioned, it relies solely on a current ratio. Additionally, employing such a PTAT bias voltage offers the advantage of reducing the temperature dependency of the bias current, thereby mitigating the curvature of V
BE compared to a constant bias voltage. Furthermore, chopping is also applied to the current source in
Figure 3 to remove unwanted offsets.
Figure 4 illustrates the implementation of the complete current source used to generate V
BE and ∆V
BE. One of the most important sources of inaccuracy is the mismatch of the 1:p (1:5 in our design) current ratio depicted in
Figure 1, consequently affecting ∆V
BE. In order to improve such a mismatch and achieve the desired level of accuracy, dynamic element matching (DEM) must be employed to mitigate mismatches.
Figure 4b illustrates the configuration of the current source when generating ∆V
BE [
2].
Six PMOS current sources, each nominally providing 2 µA, replicate the current generated in the bias circuit. Through a set of switches, each current is directed to either Q
1 or Q
2 (in
Figure 4b). One of these switches is routed to one transistor, delivering the unit current in the 1:5 ratio, while the remaining currents are routed to the other transistor. The mismatch between the unit current source and the average of the other sources introduces errors in the resulting current ratio. By alternating the unit current source in successive modulator cycles, mismatch errors are averaged out. The integrator of the modulator performs the required averaging. The front-end also allows us to perform current trimming, in order to compensate for variations in the nominal value of the transistor’s saturation current and the spread of the bias current itself. Traditional trimming methods involve adjusting the emitter area or bias current using switchable binary-scaled transistors or bias current sources [
2].
However, given the extensive required range, such techniques become complex and demand substantial chip area. Alternatively, in this work, the same six PMOS current sources utilized for generating the 1:5 current ratio are repurposed for generating the trimmed current. This is feasible because ∆V
BE and V
BE are never used simultaneously. Hence, five of these sources facilitate coarse trimming, controlled by the digital input, and the sixth current source enables fine trimming, by using the I
DAC in
Figure 4c. Such small 4-bit current DAC is employed to achieve a trimming resolution of 64 nA. With a total trimming range of 2–12 µA, with a 64 nA step, it adequately compensates for practical variations, and it is sufficient to reduce the mismatch to acceptable values. In the implementation, unused current sources are connected to an additional diode-connected transistor (not depicted in
Figure 4), effectively limiting switching transients at their outputs.
3.2. Sigma–Delta ADC
The ADC, comprising a Σ∆ modulator and a decimation filter, converts ∆
VBE and
VBE into a digital temperature reading D
OUT. The design of the ΣΔM in smart temperature sensors greatly influences their performance by enhancing or degrading its accuracy, resolution, noise immunity, and conversion speed. ΣΔs enable precise analog-to-digital conversion by oversampling the input signal and employing noise shaping techniques, which significantly reduces quantization noise within the signal bandwidth. This results in more accurate temperature measurements, even in the presence of electronic noise and varying environmental conditions. Additionally, ΣΔs allow for simpler and more cost-effective sensor design by integrating high-resolution digital output and reducing the need for complex analog circuitry, making the overall sensor system more reliable and efficient. Fundamentally, the ΣΔ requirements will depend on two performances, namely conversion time and quantization error. This will impact the choice of topology, order of the modulator, and if the decimator filter can be a simple counter or something more complex. The higher the ΣΔ order, the less cycles it will need to measure the temperature, but it will consume more power, area, and it will be more complex to design as well. The order of the modulator will dictate how many cycles we will need for a temperature reading and therefore is directly related to the conversion speed as well as the decimation filter. In our approach, we target a 14-bit resolution, and the maximum conversion time is set to 10 ms and the operation frequency is 1 MHz. The modulator generates a certain number of bits, which are converted into a single temperature reading by the decimation filter. This mode of operation, termed “incremental”, enables the use of a relatively simple decimation filter of similar order as the modulator. A first-order modulator is utilized, employing a fully differential switched-capacitor implementation. The switched-capacitor implementation of the modulator is depicted in
Figure 5. Mismatch between the unit capacitors constrains the accuracy of the integration. Hence, to limit the temperature error resulting from this mismatch to ~0.01 °C, it is imperative that the matching be precise, which cannot be solely achieved through layout precision. Once again, DEM techniques are employed to the C
IN and C
S capacitances to average out mismatch errors by alternating the unit capacitor used in successive modulator cycles. To ensure minimal errors due to finite gain, an operation amplifier with a DC gain of around 120 dB was implemented. The comparator is designed as a dynamic latch preceded by a preamp, which prevents any kickback to the output of the second integrator. The modulator adopts nonoverlapping clocks.
Furthermore, while offset and 1/ƒ noise of the integrator are reduced by the applied correlated double-sampling, charge injection mismatch in the switches still exists, resulting in some offset. The used CMOS switches were designed to minimize this offset, however, an offset of a few tens of µV remains. In order to reduce the offset, the modulator is chopped at the system level. A chopper switch at the input and a switch at the output periodically reverse the polarity of the input signal and the bitstream. To avoid disturbing the operation of the modulator when chopping, its state is also inverted by swapping the integration capacitors of both integrators. The chopping is done at a slow speed to make errors due to charge injection in the chopper switches negligible. Two chopping periods per conversion are used in order to average and cancel the offsets. The CINT capacitor is chosen as three times the value of the CS capacitor so as to reduce the effective VREF seen at the input of the modulator.
3.3. Decimation Filter
The Σ∆ modulator runs for 8192 cycles of 1 µs (4096 cycles times two complete chopping periods) and then feeds such bitstream to the decimation filter to produce a decimated value which is then correlated to a produce a temperature reading. A symmetrical filter function must be used in order to adequately average out the modulated offset and dynamic element matching (DEM) residuals, thereby accurately representing the average temperature during a conversion. However, during the operation of the temperature sensor, the bitstream produces very similar codes for two consecutive temperature readings and therefore, it may happen that the decimator “cuts” the reading before reaching different patterns, and it would then produce an error in the output temperature. When targeting lower accuracies, this effect would not be a problem, but when targeting an accuracy of ±0.15 °C, this is problematic; hence, in this work, we developed a decimation filter in the hardware which solves this issue.
To first illustrate the concern addressed, please consider a mid-range voltage that would result in a bitstream “0101010101…”. Voltages that differ by only one or two LSBs from the mid-range voltage result in an identical bitstream during a very long number of clock cycles before they present a pair of “11” or “00”. If the decimator only considers 512 or 1024 bits of the bitstream, it will output a huge error. This behavior was observed when performing the conversion of temperatures from −40 °C to 125 °C, with steps of 0.1 °C and it was noticed for temperatures around the ones that produce the bitstreams with patterns “1010101…”, “0100100100…”, and “1011011011…”. The corrective measure was to detect these patterns and to change the oversampling ratio to double the number of bits to include in the analyzed bitstream when one of these patterns is present. When a start of conversion occurs, the analog part of the ADC is expected to be powered down. The digital state machine of the ADC has a timer that allows the analog part of the ADC to achieve a steady state. The bitstream is ignored while the digital timer counts and waits for the analog circuitry to power up. However, the most recent four ignored values are stored in a four-bit shift register. When the timer ends the waiting period, the four bits in the shift register are compared with “1010” and “0101” to detect the regular pattern “1010101…”. The four bits are also compared with ”1001”, “0100”, and “0010” to detect the pattern “0100100100…”; and with “0110”, “1011”, and “1101” to detect the pattern “1011011011…”.
To solve this issue, a second-order Σ∆ could be used, or a more complex decimation filter. However, this would impact the power, area, and complexity of the design. Therefore, in order to comply with the accuracy, in this work, an adaptative decimation filter is implemented that is able to recognize such repetitive patterns in the problematic reading areas (such as Σ∆ modulator mid-scale code) and increase the oversampling ratio in order to compensate and avoid high errors in such mid-scale areas. When such patterns are identified, the conversion time is increased; however, the accuracy is maintained at a low cost, both in terms of power and area, since the decimation filter is kept simple.
5. Conclusions
In conclusion, this paper presents a significant advancement in the field of temperature sensing with the development of a highly accurate and fast-conversion CMOS smart temperature sensor. This sensor achieves an impressive ±0.15 °C (3σ) inaccuracy over a broad temperature range from −40 °C to 125 °C. These results are possible to achieve since many analog counterparts of the circuit leverage from DEM techniques and the fast conversion times are achieved by innovative adaptive decimation filtering techniques. The circuit has been implemented in 65 nm CMOS technology and the sensor not only attains exceptional accuracy but also maintains a swift 10 ms conversion time. This makes it highly suitable for real-time temperature monitoring applications.
By integrating advanced Dynamic Element Matching (DEM) and chopping methods, the sensor effectively minimizes its inaccuracy, ensuring reliable and precise temperature measurements even in challenging operating conditions. This substantial advancement underscores the potential of CMOS technology in enabling high-performance temperature sensing solutions for a wide range of industrial, medical, and consumer electronics applications. The development of such a sensor highlights the promising future of accurate and rapid temperature sensing technologies.