A ±0.15 °C (3σ) Inaccuracy CMOS Smart Temperature Sensor from 40 °C to 125 °C with a 10 ms Conversion Time-Leveraging an Adaptative Decimation Filter in 65 nm CMOS Technology

Abstract

This paper presents the design and implementation of a highly accurate smart temperature sensor designed in 65 nm CMOS technology. The sensor exhibits a ±0.15 °C (3σ) error across a wide temperature range from −40 °C to 125 °C, catering to diverse application needs. Leveraging advanced CMOS technology, the sensor employs an adaptive decimation filter that allows us to control the conversion time, ensuring that the accuracy of the conversion is maintained even in challenging conditions. The proposed sensor architecture integrates advanced techniques for temperature sensing for improved accuracy and reliability. Through meticulous circuit design and the usage of dynamic element matching, chopping, and calibration/trimming, the sensor demonstrates exceptional performance characteristics, making it suitable for various industrial, automotive, and consumer electronics applications demanding high precision temperature monitoring.

1. Introduction

In modern electronics, temperature sensing is a fundamental aspect that underpins the performance, reliability, and safety of numerous devices and systems. From industrial process control to microprocessors and consumer electronics, the accurate measurement of temperature is essential for maintaining optimal operation and preventing catastrophic failures [1].

Smart temperature sensors are essential in the design and operation of Application-Specific Integrated Circuits (ASICs) due to their ability to provide precise information to other acting circuits which can then perform thermal management. These sensors help maintain optimal operating temperatures, which is crucial for the performance and reliability of ASICs. Overheating can lead to thermal throttling, reduced efficiency, and potentially permanent damage to the circuit. By continuously monitoring the temperature, smart sensors allow for dynamic adjustments, such as modulating clock speeds or power delivery, to prevent overheating. This ensures that ASICs operate within their specified temperature ranges, enhancing their longevity and stability. Thus, smart temperature sensors contribute significantly to both the quality and reliability of ASICs throughout their lifecycle. As technological advancements continue to push the boundaries of miniaturization and integration, the demand for highly precise and compact temperature sensors has intensified. In response to this need, researchers and engineers have endeavored to develop innovative solutions capable of delivering exceptional accuracy, reliability, and efficiency [2,3,4,5].

As previously said, there is the need for robust temperature sensing solutions in a wide range of applications. Accurate temperature monitoring is essential for optimizing the performance and longevity of electronic equipment, ensuring compliance with regulatory standards, and enhancing user experience in consumer products. One of the critical challenges in temperature sensing is achieving high accuracy across a broad range of operating conditions. Traditional temperature sensors often struggle to maintain precision in extreme environments or exhibit significant errors due to variations in process, voltage, and temperature (PVT) [6]. Moreover, the quest for low-area and low-power integrated circuits (ICs) adds further complexity to sensor design, necessitating novel architectures and techniques to address these constraints effectively. Two of the most important performances of a smart temperature sensor are accuracy and conversion speed. In smart temperature sensors, there is often a trade-off between these two performances. High accuracy means the sensor can measure temperature very precisely, which is essential for applications requiring exact temperature control, such as in medical or scientific equipment. However, achieving this high accuracy typically requires more time for each measurement, as the sensor may need to average multiple readings or perform complex calibrations to reduce noise and enhance precision.

On the other hand, fast conversion speed allows the sensor to provide real-time temperature readings, which is crucial for dynamic systems like HVAC controls or automotive applications. However, increasing the speed of conversion can introduce more noise and reduce the accuracy of the measurement. Manufacturers of smart temperature sensors often need to balance these two factors, optimizing the design to meet the specific needs of the application, whether it prioritizes rapid updates or precise measurements. The objective of this work is to achieve a very high accuracy but with smaller conversion times than typical smart sensors with the same accuracy [7,8].

In this context, the present paper introduces an advancement in temperature sensing technology by proposing a ±0.15 °C (considering 3σ) error CMOS smart temperature sensor across a broad range of temperatures (−40 °C to 125 °C) and implemented in a 65 nm CMOS technology. This sensor leverages dynamic element matching (DEM) techniques and chopping in order to mitigate the effects of noise, nonlinearity, and process variations inherent in CMOS-based sensors and obtain such a high accuracy. Since all the primary sources of error are reduced to a 0.01 °C level, in this temperature sensor, the primary source of error stems from the variability in the characteristics of the bipolar transistors [2]. Hence, calibration at a single temperature proves adequate to identify and rectify this error through trimming. Given the essentially unidimensional nature of this variability, the correction remains effective across the entire operational spectrum.

Central to the functionality of the smart temperature sensor is the sigma–delta (Σ∆) analog-to-digital converter (ADC), which operates differently from traditional converters. Instead of directly converting the incoming analog signal into a digital sample of n-bit precision at the Nyquist rate, they employ oversampling. This means the analog signal is sampled at a much higher rate, denoted as fN, where fN << fS (with oversample rates like 16, 32, 64, or 128 being common). During oversampling, the ADC captures the analog signal at a lower precision (coarser quantization), often effectively functioning as a 1-bit ADC (as in our case). The output of the modulator or 1-bit ADC is a bitstream (bs). The density of the ones in this stream correlates with the magnitude of the sine-wave input. The 1-bit ADC stream undergoes digital filtering to derive an n-bit representation of the analog input. Put simply, the 1-bit ADC stream is summed over N sampling cycles and then divided by N. This process produces a decimated value, representing the average value of the bitstream from the modulator [3]. The circuit that performs such decimated value is called a decimator filter. The output of the decimator can then be converted to temperature; hence, the Σ∆ ADC (modulator and the decimator) operates as a voltage to temperature converter.

The Σ∆ modulator needs to feed several bits to the decimator filter in order to achieve sufficient resolution. This will therefore increase the number of cycles that the Σ∆ needs to run in order to achieve a good temperature resolution and therefore accuracy. This time is known as conversion time. In order for obtain fast conversion times, higher sampling rates can be used, second-order Σ∆s [4], or higher order decimation filters can be used [5]. However, each of those solutions has its cost in design complexity, power consumption and area. Hence, the relationships among complexity, power consumption, and area are difficult to manage, and novel approaches must be followed in order to minimize all previous parameters. However, this is never trivial in circuit design.

Hence, in order to improve the conversion speed while keeping the area, power consumption, and design complexity to a minimum, in our work, we have developed a novel adaptative decimation filter which is able to dynamically adjust the number of cycles used for the decimation in order to keep topmost accuracy without resorting to extra area, power or increasing the design complexity of the analog circuits, like using a higher-order Σ∆. This adaptive feature distinguishes the proposed sensor from conventional temperature sensors, which often rely on fixed or predetermined filtering strategies that may compromise accuracy or efficiency in dynamic environments. This adaptative decimation filter will be explained in detail in Section 3.

The remainder of this paper is organized as follows: Section 2 discusses the basics of smart temperature basics. Section 3 presents the implementation details of the proposed smart temperature sensor, and Section 4 showcases the performance characteristics and capabilities of the smart temperature sensor through comprehensive pre- and post-layout simulations. Finally, Section 5 draws the conclusions.

2. Smart Temperature Sensor Basics

To obtain a digital temperature reading, a comparison measurement must be performed, comparing a temperature-dependent signal with a reference signal. Although most devices exhibit temperature-dependent characteristics and could ideally be used for such purpose, bipolar transistors are especially well-suited for that [6]. They can produce both a voltage proportional to absolute temperature (PTAT) and a temperature-independent bandgap reference voltage. In CMOS technology, substrate bipolar transistors can fulfil this role effectively.

Figure 1 depicts the operational concept of a temperature sensor. It employs two diode-connected substrate PNP transistors to generate two voltages, V_BE and ∆V_BE. These voltages are then combined to create the necessary PTAT and reference voltages [2]. Subsequently, these voltages are converted into a digital temperature reading through an ADC thus generating a temperature reading in a digital format D_OUT.

The base-emitter voltage of a bipolar transistor in its forward-active region can be described by the following well-known logarithmic equation:

$$V_{BE}\left(T\right)={\displaystyle \frac{kT}{q}}\ln \left({\displaystyle \frac{I_{BIAS}\left(T\right)}{I_S\left(T\right)}}\right)$$

(1)

where k, is the Boltzmann constant, q is the electron charge, T is the absolute temperature, I_S the transistor saturation current, and I_BIAS is its collector current, determined by a bias circuit [2]. It is well known that the bipolar transistor saturation current highly depends on the temperature, hence the base-emitter voltage exhibits a negative temperature coefficient of around −2 mV/°C. And it can also be shown that for two bipolar transistors operating with a collector current ratio of 1:p, the ∆V_BE can be given by the following:

$$\mathsf{\Delta }{V}_{BE}\left(T\right)={\displaystyle \frac{kT}{q}}\ln \left(\mathrm{p}\right)$$

(2)

Hence, ∆V_BE only depends on the ratio of currents p, making it an accurate measure of temperature. A larger current ratio p results in a larger ∆V_BE, but the designer must ensure that the two transistors remain in the same operating region [1]. In this work, a current ratio p of 5 is used, resulting in a temperature coefficient of ~0.14 mV/°C. For the ADC, a 1.2 V bandgap voltage can be used to digitize ∆V_BE. Such reference is generated by adding an amplified version of ∆V_BE to V_BE so as to obtain a temperature-independent voltage V_REF as follows:

$$V_{REF}=\mathsf{\alpha }·\mathsf{\Delta }{V}_{BE}+V_{BE}$$

(3)

In order to obtain a V_REF = 1.2 V, the necessary $\mathsf{\alpha }$ is 14. However, in our design, since we are operating with V_DD = 1.8 V, we have reduced the V_REF to around 0.4 V so that the Σ∆ does not saturate. This was performed by properly designing the number of capacitances in the charge balancing Σ∆. The ADC then converts the ratio of $\mathsf{\alpha }$·∆V_BE and V_REF in order to obtain a digital reading D_OUT as follows:

$$D_{OUT}=A·{\displaystyle \frac{\mathsf{\alpha }·\mathsf{\Delta }{V}_{BE}}{V_{REF}}}-B$$

(4)

where the coefficients A and B are chosen so as to obtain a digital output in degrees Celsius [1]. In our design, these coefficients are chosen to be around 600 and 273, respectively.

3. Proposed Temperature Sensor

Figure 2 shows the block diagram of the sensor. The front-end is constituted by a bias circuit, that generates a PTAT voltage (with an I_BIAS current) and a bipolar core that generates the voltages ∆V_BE and V_BE. These voltages serve as inputs to the Σ∆ modulator, which produces a bitstream bs, which average value is equal to the ratio between α·∆V_BE and V_REF. The converter uses a charge-balancing scheme which will be detailed in Section 3.2. To filter the quantization noise from the bitstream and achieve the required scaling as outlined in Equation (3), a decimation filter is utilized.

3.1. Biasing Circuitry

Figure 3 shows the bias circuit of the front end, used to generate a PTAT current and V_BIASP. While some variance in the absolute value of the bias current can be accepted since it can be trimmed, it is crucial to minimize other sources of error in the bias current, such as fluctuations with the supply voltage and temperature dependence. Typically, bias current is obtained from a bias voltage through a resistor. Opting for a bias voltage derived from the difference in base-emitter voltage is favorable because, as previously mentioned, it relies solely on a current ratio. Additionally, employing such a PTAT bias voltage offers the advantage of reducing the temperature dependency of the bias current, thereby mitigating the curvature of V_BE compared to a constant bias voltage. Furthermore, chopping is also applied to the current source in Figure 3 to remove unwanted offsets.

Figure 4 illustrates the implementation of the complete current source used to generate V_BE and ∆V_BE. One of the most important sources of inaccuracy is the mismatch of the 1:p (1:5 in our design) current ratio depicted in Figure 1, consequently affecting ∆V_BE. In order to improve such a mismatch and achieve the desired level of accuracy, dynamic element matching (DEM) must be employed to mitigate mismatches. Figure 4b illustrates the configuration of the current source when generating ∆V_BE [2].

Six PMOS current sources, each nominally providing 2 µA, replicate the current generated in the bias circuit. Through a set of switches, each current is directed to either Q₁ or Q₂ (in Figure 4b). One of these switches is routed to one transistor, delivering the unit current in the 1:5 ratio, while the remaining currents are routed to the other transistor. The mismatch between the unit current source and the average of the other sources introduces errors in the resulting current ratio. By alternating the unit current source in successive modulator cycles, mismatch errors are averaged out. The integrator of the modulator performs the required averaging. The front-end also allows us to perform current trimming, in order to compensate for variations in the nominal value of the transistor’s saturation current and the spread of the bias current itself. Traditional trimming methods involve adjusting the emitter area or bias current using switchable binary-scaled transistors or bias current sources [2].

However, given the extensive required range, such techniques become complex and demand substantial chip area. Alternatively, in this work, the same six PMOS current sources utilized for generating the 1:5 current ratio are repurposed for generating the trimmed current. This is feasible because ∆V_BE and V_BE are never used simultaneously. Hence, five of these sources facilitate coarse trimming, controlled by the digital input, and the sixth current source enables fine trimming, by using the I_DAC in Figure 4c. Such small 4-bit current DAC is employed to achieve a trimming resolution of 64 nA. With a total trimming range of 2–12 µA, with a 64 nA step, it adequately compensates for practical variations, and it is sufficient to reduce the mismatch to acceptable values. In the implementation, unused current sources are connected to an additional diode-connected transistor (not depicted in Figure 4), effectively limiting switching transients at their outputs.

3.2. Sigma–Delta ADC

The ADC, comprising a Σ∆ modulator and a decimation filter, converts ∆V_BE and V_BE into a digital temperature reading D_OUT. The design of the ΣΔM in smart temperature sensors greatly influences their performance by enhancing or degrading its accuracy, resolution, noise immunity, and conversion speed. ΣΔs enable precise analog-to-digital conversion by oversampling the input signal and employing noise shaping techniques, which significantly reduces quantization noise within the signal bandwidth. This results in more accurate temperature measurements, even in the presence of electronic noise and varying environmental conditions. Additionally, ΣΔs allow for simpler and more cost-effective sensor design by integrating high-resolution digital output and reducing the need for complex analog circuitry, making the overall sensor system more reliable and efficient. Fundamentally, the ΣΔ requirements will depend on two performances, namely conversion time and quantization error. This will impact the choice of topology, order of the modulator, and if the decimator filter can be a simple counter or something more complex. The higher the ΣΔ order, the less cycles it will need to measure the temperature, but it will consume more power, area, and it will be more complex to design as well. The order of the modulator will dictate how many cycles we will need for a temperature reading and therefore is directly related to the conversion speed as well as the decimation filter. In our approach, we target a 14-bit resolution, and the maximum conversion time is set to 10 ms and the operation frequency is 1 MHz. The modulator generates a certain number of bits, which are converted into a single temperature reading by the decimation filter. This mode of operation, termed “incremental”, enables the use of a relatively simple decimation filter of similar order as the modulator. A first-order modulator is utilized, employing a fully differential switched-capacitor implementation. The switched-capacitor implementation of the modulator is depicted in Figure 5. Mismatch between the unit capacitors constrains the accuracy of the integration. Hence, to limit the temperature error resulting from this mismatch to ~0.01 °C, it is imperative that the matching be precise, which cannot be solely achieved through layout precision. Once again, DEM techniques are employed to the C_IN and C_S capacitances to average out mismatch errors by alternating the unit capacitor used in successive modulator cycles. To ensure minimal errors due to finite gain, an operation amplifier with a DC gain of around 120 dB was implemented. The comparator is designed as a dynamic latch preceded by a preamp, which prevents any kickback to the output of the second integrator. The modulator adopts nonoverlapping clocks.

Furthermore, while offset and 1/ƒ noise of the integrator are reduced by the applied correlated double-sampling, charge injection mismatch in the switches still exists, resulting in some offset. The used CMOS switches were designed to minimize this offset, however, an offset of a few tens of µV remains. In order to reduce the offset, the modulator is chopped at the system level. A chopper switch at the input and a switch at the output periodically reverse the polarity of the input signal and the bitstream. To avoid disturbing the operation of the modulator when chopping, its state is also inverted by swapping the integration capacitors of both integrators. The chopping is done at a slow speed to make errors due to charge injection in the chopper switches negligible. Two chopping periods per conversion are used in order to average and cancel the offsets. The C_INT capacitor is chosen as three times the value of the C_S capacitor so as to reduce the effective V_REF seen at the input of the modulator.

3.3. Decimation Filter

The Σ∆ modulator runs for 8192 cycles of 1 µs (4096 cycles times two complete chopping periods) and then feeds such bitstream to the decimation filter to produce a decimated value which is then correlated to a produce a temperature reading. A symmetrical filter function must be used in order to adequately average out the modulated offset and dynamic element matching (DEM) residuals, thereby accurately representing the average temperature during a conversion. However, during the operation of the temperature sensor, the bitstream produces very similar codes for two consecutive temperature readings and therefore, it may happen that the decimator “cuts” the reading before reaching different patterns, and it would then produce an error in the output temperature. When targeting lower accuracies, this effect would not be a problem, but when targeting an accuracy of ±0.15 °C, this is problematic; hence, in this work, we developed a decimation filter in the hardware which solves this issue.

To first illustrate the concern addressed, please consider a mid-range voltage that would result in a bitstream “0101010101…”. Voltages that differ by only one or two LSBs from the mid-range voltage result in an identical bitstream during a very long number of clock cycles before they present a pair of “11” or “00”. If the decimator only considers 512 or 1024 bits of the bitstream, it will output a huge error. This behavior was observed when performing the conversion of temperatures from −40 °C to 125 °C, with steps of 0.1 °C and it was noticed for temperatures around the ones that produce the bitstreams with patterns “1010101…”, “0100100100…”, and “1011011011…”. The corrective measure was to detect these patterns and to change the oversampling ratio to double the number of bits to include in the analyzed bitstream when one of these patterns is present. When a start of conversion occurs, the analog part of the ADC is expected to be powered down. The digital state machine of the ADC has a timer that allows the analog part of the ADC to achieve a steady state. The bitstream is ignored while the digital timer counts and waits for the analog circuitry to power up. However, the most recent four ignored values are stored in a four-bit shift register. When the timer ends the waiting period, the four bits in the shift register are compared with “1010” and “0101” to detect the regular pattern “1010101…”. The four bits are also compared with ”1001”, “0100”, and “0010” to detect the pattern “0100100100…”; and with “0110”, “1011”, and “1101” to detect the pattern “1011011011…”.

To solve this issue, a second-order Σ∆ could be used, or a more complex decimation filter. However, this would impact the power, area, and complexity of the design. Therefore, in order to comply with the accuracy, in this work, an adaptative decimation filter is implemented that is able to recognize such repetitive patterns in the problematic reading areas (such as Σ∆ modulator mid-scale code) and increase the oversampling ratio in order to compensate and avoid high errors in such mid-scale areas. When such patterns are identified, the conversion time is increased; however, the accuracy is maintained at a low cost, both in terms of power and area, since the decimation filter is kept simple.

4. Experimental Results

The temperature sensor was designed in a 65 nm CMOS technology operating with supply voltages of 1.8 V/1.2 V (analog/digital). The decimation filter and the digital control circuitry were all synthesized and implemented on a chip. The chip layout is shown in Figure 6 (only the analog part).

In order to inspect the performances of the temperature sensor, and the impact of the several implemented techniques for error reduction (chopping and DEM) several Monte-Carlo (MC) and PVT simulations were performed and are shown in the following sub-sections.

4.1. Temperature Sensor Accuracy over Monte-Carlo Simulations

Although the benefits of using chopping [9,10,11] and DEM techniques [12,13] are widely known, in this sub-section, several MC simulations were performed to quantify such benefits. Due to the large simulation time of each sample, a total of 30 samples and only pre-layout simulations were considered in order to keep the simulation time manageable.

The simulations shown here were performed at the top level, considering the entire temperature sensor. In order to draw conclusions from the benefits of using DEM and chopping individually, when the intention is to observe the benefits of DEM (Section 4.1.1), the simulation considers chopping; and on the other hand, when the benefits of chopping are to be observed (Section 4.1.2), DEM is applied. All the simulations in this Section were made for the temperature of 30 °C and therefore, the errors shown are for this temperature.

4.1.1. Benefits of Dynamic Element Matching

DEM is a critical technique for reducing mismatch due to process variations. In this temperature sensor, DEM is being applied in the front-end to the current sources (CS) that bias the BJT diodes and in the input capacitances of the Σ∆ modulator. In this sub-section, MC simulations were performed in two situations—with and without DEM. The results are shown in Figure 7 and Figure 8.

It can be concluded that applying DEM is critical for good accuracy. Especially in the case of the CSs biasing the BJT diodes (Figure 7), it can be seen that if DEM was not applied, then errors of more than 1 °C could be obtained. In this example, by applying DEM, the temperature error was reduced from more than 1 °C to less than 0.15 °C (in some samples). Hence, applying DEM on the CS of the front-end is key for achieving good accuracy. Regarding the case of the Σ∆ C_IN, the results are not that critical but are still important to have a system accuracy with less than 0.1 °C error (see Figure 8).

Table 1. Results of the simulation of 30 Monte-Carlo samples showcasing the benefits of DEM in the input capacitors (C_IN) of the Σ∆ modulator.

Temperature Error	No DEM in CIN	No DEM in CS	With Both DEMs
Maximum (°C)	0.16	1.33	0.12
Average (°C)	−0.01	−0.07	−0.01
Minimum (°C)	−0.13	−1.01	−0.09
3σ (°C)	0.18	1.82	0.14

shows a resumption of such simulations including maximum, minimum, average, and 3σ results of the temperature error.

4.1.2. Benefits of Chopping

In order to quantify the benefits of chopping, two different MC experiments were performed as follows: A total of 30 MC samples with chopping ${\varnothing }_1$ active and 30 MC samples in chopping ${\varnothing }_2$ active were tested. In order to see the benefits of chopping, such temperature errors were then averaged. Figure 9 shows the results of such an experiment. It can be seen that the errors are large (>±0.4 °C) in both ${\varnothing }_1$ and ${\varnothing }_2$, but the average error is subsequently reduced to less than 0.1 °C; hence, performing chopping does not have such a large impact as DEM but it is still important to achieve errors of around 0.1 °C.

Table 2. Results of the simulation of 30 Monte-Carlo samples, showing the benefits of chopping with the average of chopping ${\varnothing }_1$ and ${\varnothing }_2$.

Temperature Error	With Ø1	With Ø1	Average Ø1 and Ø2
Maximum (°C)	0.50	0.52	0.12
Average (°C)	0.05	−0.04	−0.01
Minimum (°C)	−0.33	−0.36	−0.09
3σ (°C)	0.62	0.65	0.14

shows a resumption of such simulations including maximum, minimum, average, and 3σ results of the temperature error in order to inspect the benefits of chopping.

4.2. Temperature Sensor Accuracy over PVT Variations

In this sub-section, the results are presented over 64 corners with varying PVT conditions as shown in Figure 10. The supply voltage was considered with a 10% variation, and the temperature range was −40 °C up to 125 °C. These simulations were performed considering both DEM and chopping (average of Ø₁ and Ø₂).

4.3. Post-Layout Results

In this sub-section, the post-layout results are presented. In Figure 10 and Figure 11, it is possible to observe the temperature error for the same PVT (for pre-and post-layout respectively). It is possible to observe that the post-layout results do not differ much from the pre-layout since the layout respected all the necessary constraints in order to maintain accuracy. There is only one corner where the error increased from 0.13 °C to 0.25 °C; however, this is still a very acceptable temperature error. Apart from the corners, it was also important to study how the post-layout parasitics impacted the performance of the Σ∆ modulator. Hence, in order to observe this, several simulations were performed (34 temperature points) and its error was observed for each temperature point at the input and output of the modulator. The objective was to see if there was some degradation due to the Σ∆ modulator. The result of this simulation is shown in Figure 12, where it is possible to observe that there is almost no degradation from the input to the output of the Σ∆ modulator, which means that the post-layout parasitics of the Σ∆ modulator do not impact the performance of the temperature sensor.

Furthermore, it is also interesting to compare the temperature sensor described in this work against the other state-of-the-art sensors.

Table 3. Comparison against state-of-the-art temperature sensors which use bipolar transistors as diodes and a 1st order Σ∆ as a modulator.

Source	Tech. (nm)	Area (mm2)	Trim Points	PP IA (°C)	Min-Max (°C)	RIA 2 (%)	TCONV (ms)	Power. (µW)	Energy (nJ)	Resolu. (K)	R-FOM 3
[14] 1 JSSC‘96	2000	1.5	1	2.0	−40~120	1.3	20	55.0	1100	0.100	11.0
[15] ESSCIRC‘99	700	3	0	3.0	−40~120	1.9	250	300	75,000	0.050	187.50
[16] 1 ISCAS‘01	700	2.8	0	3.0	−50~125	1.7	100	280	28,000	0.125	437.50
[17] ISSCC‘10	65	0.1	1	0.4	−70~125	0.2	455	10.0	4532	0.030	4.079
[18] 1 JSSC‘15	14	0.0087	2	3.3	0~100	3.3	0.02	1111	24	0.500	6.112
[19] 1 ESSCIRC‘15	16	0.0126	0	4.0	−50~150	2.0	0.27	1210	327	0.400	52.272
[19] 1 ESSCIRC‘15	20	0.018	1	5.0	−25~125	3.3	0.16	1100	176	0.400	28.160
[20] Sensors‘16	180	0.198	1	0.4	25~45	2.0	500	1.1	550	0.010	0.055
[21] ISSCC‘17	28	0.0095	0	3.70	−25~125	2.47	8.2	18.8	154	0.150	3.456
[22] 1 TCAS-I‘20	65	0.003	2	2.70	−10~110	2.25	4.10	111.8	458	0.130	7.747
[23] TCAS-II‘19	55	0.0146	0	3.40	−40~125	2.06	32.8	37.0	1214	0.020	0.485
This work1,4	65	0.079	1	0.25	−40~125	0.15	8.53	232	1979	0.039	3.269

¹ Works that have the digital back-end implemented on-chip (including the decimation filter). ² RIA = 100 × PP IA/Specified temperature range. ³ R-FOM: Resolution Figure-of-Merit. ⁴ Post-Layout Results. R-FOM = (Energy/conversion) × (Resolution)².

shows how this temperature sensor fares against similar temperature sensors that are also using bipolars as diodes and a 1st order modulator (in particular, a Σ∆).

Table 3 describes the technology in which the sensors were designed and some performance metrics. Some are self-explanatory, but others need further explanation. For example, the PP IA measure is the worst-case inaccuracy (IA) over a specified temperature range. The values given for each temperature sensor are either max–min or 6σ values. Since inaccuracy is a statistical measure, measurements on a large number of samples (>12) are required to obtain realistic numbers. Inaccuracy is a function of sensor type, readout architecture, process, and the number of trimming points. Due to the presence of non-linearity, a sensor’s spread is usually less than its inaccuracy. In our case, the PP IA was considered to be the worst-case corner in post layout results (0.25 °C) on over 60 corners. The RIA is the relative inaccuracy, which is given as the slope of an imaginary box placed around the sensor’s error vs. temperature curve.

It is possible to conclude that the temperature sensor proposed in this work compares well against the other state-of-the-art sensors. In particular, it has an exceptional PP-IA and RIA and also presents a very good R-FOM. The results can be also seen in Figure 13a for the FOM vs. RIA and in Figure 13b for the Resolution vs. Energy/Conversion performances.

5. Conclusions

In conclusion, this paper presents a significant advancement in the field of temperature sensing with the development of a highly accurate and fast-conversion CMOS smart temperature sensor. This sensor achieves an impressive ±0.15 °C (3σ) inaccuracy over a broad temperature range from −40 °C to 125 °C. These results are possible to achieve since many analog counterparts of the circuit leverage from DEM techniques and the fast conversion times are achieved by innovative adaptive decimation filtering techniques. The circuit has been implemented in 65 nm CMOS technology and the sensor not only attains exceptional accuracy but also maintains a swift 10 ms conversion time. This makes it highly suitable for real-time temperature monitoring applications.

By integrating advanced Dynamic Element Matching (DEM) and chopping methods, the sensor effectively minimizes its inaccuracy, ensuring reliable and precise temperature measurements even in challenging operating conditions. This substantial advancement underscores the potential of CMOS technology in enabling high-performance temperature sensing solutions for a wide range of industrial, medical, and consumer electronics applications. The development of such a sensor highlights the promising future of accurate and rapid temperature sensing technologies.