Improved Design of a SiC MOSFET Gate Drive with Crosstalk Suppression Capability

Abstract

For high-frequency switching applications, silicon carbide (SiC) devices are more suitable than silicon-based devices, which is conducive to improving the efficiency and power density of power electronic equipment. However, as the switching frequency increases, the influence of parasitic parameters on the switching characteristics of devices becomes increasingly apparent. When SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are applied in bridge circuits, the crosstalk problem easily occurs with the complementary conduction of upper and lower transistors, which seriously limits the promotion of SiC MOSFETs. However, the existing crosstalk suppression drive circuit tends to increase the switching loss, switching delay, and control complexity; therefore, a gate drive with crosstalk suppression capability is proposed. In this paper, the gate drive has two features: a negative voltage to shut down the SiC MOSFET; and an adjustment of the gate-source equivalent impedance. To accomplish this goal, the mechanism of crosstalk voltage generation is analyzed. Furthermore, the operation principle of the gate drive is analyzed, and the parameters of the gate drive are designed. Eventually, the proposed gate drive is verified by an LTspice simulation and experimental platform. The results prove that the gate drive can suppress the crosstalk voltage without affecting the switching speed.

1. Introduction

SiC MOSFETs are wide-band gap devices that have revolutionized power electronics technology [1]. SiC MOSFETs offer the excellent characteristics of low gate charge and high speed-switching ability, which makes them more suitable for high-frequency occasions compared with Si-based devices [2]. They facilitate the improvement of the reliability, power density, and efficiency of power electronic converters and have been widely considered by the academic and industrial spheres [3,4]. However, as the switching frequency increases, dv/dt and di/dt also become larger so that parasitic parameters that are not obvious at low frequency generate voltage spikes that can damage the stability and reliability of the system [5,6,7]. In practical applications, the bridge structure is a widely used converter structure. When one switching device turns on and off, especially under the condition of a high switching speed, crosstalk voltage is generated and superimposed between the source and gate of the complementary switching device [8]. SiC MOSFETs have a lower threshold voltage compared with Si devices. Therefore, SiC MOSFETs may be turning on by mistake when the positive crosstalk voltage is generated, and even the bridge arm may pass through. This results in increased switching losses and is likely to burn out the MOSFET. In addition, because the maximum negative voltage that the SiC MOSFET gate source can withstand is very small, the negative voltage peak caused by crosstalk may exceed this value, resulting in the burning of the switching device [9,10,11]. In conclusion, when SiC MOSFETs are used in three-phase inverters, bridge DC–DC converters, and other converters with phase-leg configurations, crosstalk becomes a critical factor to evaluate, and every effort must be made to avoid false triggers and negative voltage over-ranges [12].

At present, the gate drive design for crosstalk suppression mainly includes two approaches.

One approach is to adjust the equivalent impedance between the source and the gate. In [13], crosstalk suppression is achieved by changing the drive resistance and connecting the auxiliary capacitors in parallel or series at the gate -source, but it increases the switching loss and switching delay. Crosstalk voltage can also be suppressed by adding a parallel branch composed of a MOSFET and a capacitor in series at the gate source [14]. This method has low switching losses and delays, but the MOSFET requires an extra drive signal, which can complicate control. In [15], two conduction paths (Miller capacitance and common source inductance) and three typical sources (dv/dt, di/dt, and power loop oscillation) of the crosstalk are analyzed. According to the equivalent model, a crosstalk suppression strategy of a gate parallel high-frequency diode is proposed. However, this strategy only suppresses negative crosstalk voltage. In [16], the authors proposed an improved gate drive, which suppresses the positive crosstalk voltage by actively decreasing the gate resistance and increasing the gate-source capacitance. However, the circuit is complex.

Another approach is to shut down the MOSFET by using negative voltage. In [17], the authors proposed a new RCD level shifter that suppresses crosstalk voltages below the threshold voltage by generating a negative gate voltage. However, the circuit only suppresses the positive crosstalk voltage. In the gate drive proposed in [18], a negative voltage is generated by using a voltage divider circuit and crosstalk voltage spikes are suppressed using a branch circuit consisting of a transistor series capacitor. The gate drive proposed in [8] suppresses the crosstalk voltage by changing the gate voltage and capacitor during switching transients, but the circuit adds a MOSFET, increasing the complexity of the control. In [19], suppression of crosstalk voltage is accomplished through a passive resonant level shifter consisting of a passive level shifter and a resonant tank, but this circuit increases the switching time. Moreover, crosstalk can also be suppressed by eliminating the Miller current [20], but the circuit increases the switching time.

In summary, most of the existing SiC MOSFET crosstalk suppression methods come at the expense of increasing switching losses, switching delays, or increasing control complexity. Aiming at the above problems, this paper proposes a drive circuit that has crosstalk suppression ability without increasing the switching delay. The proposed driver circuit combines negative voltage shutdown with clamp suppression and the use of resistors and capacitors to create negative voltage instead of negative voltage sources. After that, on the basis of negative pressure drive, the equivalent impedance between the gate and the source is adjusted during the switching process of the switch transistor. We analyze the designed driver circuit through a parameter design and simulation based on LTspice and finally verify it by building a synchronous buck test platform. The experimental results prove that the designed driver circuit, compared with the traditional driver circuit, can be better for crosstalk voltage positive peak attenuation below 0 V and can effectively reduce the negative crosstalk voltage while reducing the drain voltage peaks; the circuit can have a safe and stable operation.

2. Analysis of the Production Mechanism of Crosstalk Voltage

The crosstalk mechanism of the bridge circuit is shown in Figure 1. Figure 1a,b show the positive and negative crosstalk voltage generation mechanisms, respectively. The control MOSFET is represented in the circuit by M₁. The synchronous MOSFET is represented in the circuit by M₂. The gate internal resistance of the SiC MOSFET is represented in the circuit by R_gn(in), and R_gn(out) is the drive resistor (where n = L, H). C_dsn, C_gdn, and C_gsn are the drain-source capacitance, gate-drain capacitance, and gate-source capacitance of the SiC MOSFET (where n = L, H), respectively. L_sn(in), L_gn(in), and L_dn(in), are the parasitic inductance of the source, gate, and drain of the SiC MOSFET (where n = L, H). L_sn(out), L_dn(out), and L_gn(out) are the parasitic inductance of the source, drain, and gate line of the SiC MOSFET (where n = L, H). VD_n is the body diode of the SiC MOSFET (where n = L, H). V_DC is the DC power supply. L and C are the output filter inductor and capacitor. R is the load resistance. The parameters related to control MOSFET M₁ are denoted by H in the subscripts. The parameters related to synchronous MOSFET M₂ are denoted by L in the subscripts. In Figure 1, the control signal of S₁ can control the conduction and shutdown of M₁, while the control signal of S₂ can control the conduction and shutdown of M₂.

Before M₁ was turned on, M₂’s body diode VD_L commutates. At the moment M₁ is turning on, M₁’s channel is commutated with VD_L. The drain-source voltage (V_dsH) of M₁ drops rapidly, and the drain-source voltage (V_dsL) of M₂ rises rapidly. The Miller capacitor C_gdL of M₂ starts to charge, and the direction of the arrow is the direction of the charging current C_gdLdV_dsL/dt in Figure 1a. The current flows through the gate of M₂ and then flows through the C_gsL and the drive resistor, which raises M₂’s gate-source voltage (V_gsL). Moreover, the freewheeling current flowing through VD_L reduces sharply, generating the crosstalk voltage on L_sL (L_sL = L_sL(in) + L_sL(out)). Together, they increase V_gsL. If V_gsL exceeds the threshold voltage (V_th) of M₂, it will cause M₂ to be turned on by mistake, causing the bridge circuit to pass through, thereby damaging M₁ and M₂ [21,22,23,24].

The load current flows through M₁’s channel before M₁ is off. When M₁ is off, VD_L and M₁’s channel commutate. V_dsH rapidly rises and V_dsL rapidly declines. C_gdL begins to discharge, and the discharge current is in the C_gdLdV_dsL/dt direction, as shown by the arrow in the Figure 1b. This current generates a left-positive and right-negative voltage drop as it flows through the gate impedance. Moreover, the negative crosstalk voltage is generated on L_sL because the current starts to shift from the channel of M₁ to VD_L. Therefore, they work together to reduce V_gsL. If the voltage peak on V_gsL is more than the voltage that M₂’s gate source can withstand, it is easy to cause damage to M₁ and M₂ [21,22,23,24].

3. Operation Principle of the Improved Crosstalk Suppress Gate Drive

3.1. Improved Gate Drive to Suppress Crosstalk

L_sL is reduced by optimizing the PCB and using the Kelvin connection to lessen the effect of L_sL on crosstalk. In contrast, Miller capacitance is an inherent characteristic of SiC MOSFET [1]. The main problem in this paper is to decrease the crosstalk voltage caused by Miller capacitors. Hence, neglecting the effect of parasitic inductance, Figure 2 shows the improved gate drive for crosstalk suppression proposed in this paper. The upper transistor M₁ is the control transistor, and the lower transistor M₂ is the synchronous transistor.

When M₁ is on, the crosstalk current flows through the driving resistor R_{3_L}, and a voltage is generated across the R_{3_L}. When this voltage reaches 0.7 V, the transistor Q_{1_L} is on. At the moment, the crosstalk current flows through Q_{1_L} and C_{2_L}, which inhibits the forward crosstalk and reduces the impedance of the gate drive loop. After the transistor is turned on, the crosstalk displacement current is absorbed, so that when the voltage of R_{3_L} is less than 0.7 V, Q_{1_L} is off.

When M₁ is off, M₂ remains off. The capacitor C_{1_H} provides a negative voltage for M₁ to turn off M₁. A crosstalk current flows through the channel formed by D_{1_L}-C_{2_L} when a negative crosstalk is generated. This inhibits negative crosstalk by providing a low-impedance loop for crosstalk currents.

3.2. Analysis of Operation Principle of Improved Crosstalk Suppression Gate Drive

Figure 3 shows the waveform of relevant variables in a switching cycle of the improved gate drive for crosstalk suppression. S₁ and S₂ are the driving signals of control transistor M₁ and synchronous transistor M₂ in the synchronous buck circuit. The gate-source voltages of M₁ and M₂ are V_gsH and V_gsL, respectively. The drain-source voltages of M₁ and M₂ are V_dsH and V_dsL, respectively. The driving voltages of M₁ and M₂ are V₁ and V₂, respectively. The Miller voltages for M₁ and M₂ are V_miller. V_th is the threshold voltage of M₁ and M₂.

To analyze the operation principle of the improved gate drive that suppresses crosstalk, the operation of the gate drive in a switching cycle is described in time periods, and the operation mode diagram of different time periods is shown in Figure 4, where no current flow is indicated by hidden symbols.

Mode 1[t₀, t₁]: The operation modal diagram of this stage is shown in Figure 4a. At this period, the control transistor M₁ is completely turned off, and the synchronous transistor M₂ is fully turned on. V₂ charges the gate-source capacitor C_gsL of M₂, and the charging current flows through the divider circuit of C_{1_L}, R_{1_L}, R_{2_L} to charge C_{1_L}. The charge current flows through R_{3_L}, and the auxiliary circuit does not work because the conduction condition of Q_{1_L} is not met.

Mode 2[t₁, t₂]: The operation modal diagram of this stage is shown in Figure 4b. At t₁ moment, M₂ begins to turn off, and the control transistor M₁ is still completely turned off. C_{1_L} provides M₂ with a negative pressure. The channel of M₂ and its body diode commutate.

Mode 3[t₂, t₃]: The operation modal diagram of this stage is shown in Figure 4c. At this period, M₁ and M₂ are in the off state, and the bridge arm is in the dead zone state.

Mode 4[t₃, t₄]: The operation modal diagram of this stage is shown in Figure 4d. At t₃ moment, M₁ begins to turn on. V₁ charges C_gsH, and the charging current flows through the C_{1_H}, R_{1_H}, R_{2_H} divider circuit to charge the capacitor C_{1_H}. At this period, the crosstalk suppression circuit of M₂ begins to work. On the one hand, the capacitor C_{1_L} provides a negative voltage for M₂ to turn off. On the other hand, M₁’s channel and the M₂’s body diode commutate. V_dsH rapidly declines, and V_dsL rapidly rises. C_gdL begins to charge, and the charging current C_gdLdV_dsL/dt flows through R_{3_L} to produce a right-positive and left-negative voltage drop so that Q_{1_L} turns on. Thus, capacitor C_{2_L} is connected to the circuit to absorb the charging current. Together, they suppress the gate-source positive crosstalk voltage of M₂. After the Q_{1_L} is turned on, the charging current is absorbed so that when the voltage across the R_{3_L} is less than 0.7 V. Meanwhile, the Q_{1_L} is turned off.

Mode 5[t₄, t₅]: The operation modal diagram of this stage is shown in Figure 4e. M₁ is fully turned on and M₂ is completely turned off, and the load current flows through M₁’s channel.

Mode 6[t₅, t₆]: The operation modal diagram of this stage is shown in Figure 4f. M₁ begins to turn off. At this period, M₁’s channel and M₂’s body diode commutate. V_dsH rapidly rises, and V_dsL rapidly declines. C_gdL begins to discharge, and the discharge current through the C_{2_L}-D_{1_L} branch, reducing the equivalent impedance of the M₂’s gate-source drive loop, suppressing the M₂’s gate-source negative crosstalk voltage.

Mode 7[t₆, t₇]: The operation modal diagram of this stage is shown in Figure 4g. After the commutation is completed, the load current continues to flow through M₂’s body diode. At this time, M₁ and M₂ are in the off state, and the bridge arm is in the dead zone state.

Mode 8[t₇, t₈]: The operation modal diagram of this stage is shown in Figure 4h. M₂ starts to turn on, M₁ remains in the off state, and M₂’s channel and body diode commutate.

After the commutation, the operation mode changes to operation Mode 1, and the subsequent working mode is similar to the above process, which will not be described here.

In conclusion, the crosstalk suppression circuit proposed in this paper does not require external control signals, which reduces the complexity of the control strategy of the drive circuit and effectively suppresses the crosstalk voltage without affecting the switching speed.

4. Parameter Design of Improved Crosstalk Suppress Gate Drive

In this paper, CREE’s second-generation 1.2 kV SiC MOSFET semiconductor device C2M0080120D is used as an example to study the parameter design of the improved gate drive, and its basic parameters are shown in

Table 1. Basic parameters of the SiC MOSFET.

Parameters	Value
Gate-source capacitance Cgs	1092 pF
Gate-drain capacitance Cgd	8 pF
Drain-source capacitance Cds	92 pF
Threshold voltage Vth	3 V
Max negative gate-source voltage VMAX(neg)	−10 V
Internal gate resistance Rg(in)	$3.8 \mathsf{\Omega }$

. The basic parameter data in Table 1 apply to control transistor M₁ and synchronous transistor M₂.

4.1. Pre-Charging Process

It is essential to pre-charge C_{1_n} to suppress crosstalk voltage before M₁ and M₂ enter the alternate conduction state (where n = L, H). Ensuring a constant voltage of C_{1_n} (where n = L, H) is the purpose of the pre-charging process. The gate circuit should be pre-charged via gate voltage source V₁ (V₂) to ensure that capacitor C_{1_H} (C_{1_L}) receives sufficient energy before the main circuit starts operating. The current direction of the pre-charging process is shown in Figure 5. Both C_{1_n} and C_gsn (where n = L, H) are charged during the pre-charging process.

The pre-charging equivalent circuits of control transistor M₁ and synchronous transistor M₂ are the same. Taking synchronous transistor M₂ as an example, Figure 6 shows the equivalent circuit of M₂’s pre-charging. According to Kirchhoff’s law and the Laplace transform, (1) is obtained:

$$\{\begin{array}{c}{R}_{1\_L}\left[I_{C1L}(s)-I_S\left(s\right)\right]+{\displaystyle \frac{1}{s{C}_{1\_L}}}{I}_{C1L}(s)=0\\ R_{2\_L}\left[I_S\left(s\right)-I_{CgsL}\left(s\right)\right]-R_{1\_L}\left[I_{C1L}(s)-I_S\left(s\right)\right]={\displaystyle \frac{V_2}{s}}\\ \left(R_{3\_L}+R_{gL(in)}+{\displaystyle \frac{1}{s{C}_{gsL}}}\right)I_{CgsL}+R_{2\_L}{I}_{CgsL}=R_{2\_L}{I}_S\left(s\right)\end{array}$$

(1)

Therefore, the current through C_gsL can be expressed as:

$$\begin{array}{l}{I}_{CgsL}={\displaystyle \frac{V_2}{A_{1}s+A_2+\frac{A_3}{1+s{C}_{1\_L}{R}_{1\_L}}}}\\ ={\displaystyle \frac{\left(\frac{1}{A_1}s+\frac{1}{A_1{C}_{1\_L}{R}_{1\_L}}\right)\cdot V_2}{s^2+\left(\frac{1}{C_{1\_L}{R}_{1\_L}}+\frac{A_2}{A_1}\right)s+\frac{A_2+A_3}{A_1{C}_{1\_L}{R}_{1\_L}}}}\end{array}$$

(2)

where

$$\begin{array}{c}{A}_1=R_{3\_L}+R_{gL(in)}\\ A_2={\displaystyle \frac{1}{C_{gsL}}}+{\displaystyle \frac{R_{2\_L}+R_{3\_L}+R_{gL(in)}}{R_{2\_L}{C}_{1\_L}}}\\ A_3={\displaystyle \frac{R_{1\_L}}{R_{2\_L}{C}_{gsL}}}-{\displaystyle \frac{R_{2\_L}+R_{3\_L}+R_{gL(in)}}{R_{2\_L}{C}_{1\_L}}}\end{array}$$

To prevent current oscillations of C_gsL, C_{1_L} and R_{1_L} should be satisfied:

$${\left(A_1+A_2{C}_{1\_L}{R}_{1\_L}\right)}^2={\displaystyle \frac{4A_1{C}_{1\_L}{R}_{1\_L}\left(R_{1\_L}+R_{2\_L}\right)}{C_{gsL}}}$$

(3)

4.2. When the Auxiliary Branch Is Not Connected to the Gate Drive

When M₁ is turned on and M₂ remains off, the auxiliary branch is not connected to the gate drive, and the equivalent simplified circuit of the M₂ drive loop is shown in Figure 7, where $R^{\prime }={\displaystyle \frac{R_{1\_L}\times R_{2\_L}}{R_{1\_L}+R_{2\_L}}}$.

Derived from Kirchhoff’s law:

$$\{\begin{array}{c}{C}_{gsL}{\displaystyle \frac{d{V}_{C_{gsL}}}{dt}}+I_{R3L}=C_{gdL}{\displaystyle \frac{d{V}_{dsL}}{dt}}\\ C_{1\_L}{\displaystyle \frac{d{V}_{C_{1L}}}{dt}}+{\displaystyle \frac{V_{C_{1L}}}{R^{\prime }}}=I_{R3L}\\ I_{R3L}\left(R_{3\_L}+R_{gL(in)}\right)+V_{C_{1L}}=V_{C_{gsL}}\\ V_{dsL}=V_{DC}u(t)\end{array}$$

(4)

The expression for the crosstalk current flowing through resistor R_{3_L} is:

$$\begin{array}{l}{I}_{R3L}={\displaystyle \frac{C_{gdL}{V}_{DC}}{C_{1\_L}{C}_{gsL}{R}^{\prime }(R_{3\_L}+R_{gL(in)})}}\times \\ \left[{\displaystyle \frac{e^{at}-e^{bt}}{a-b}}+{\displaystyle \frac{R^{\prime }{C}_{1\_L}}{a-b}}\left(a{e}^{at}-b{e}^{bt}\right)\right]\end{array}$$

(5)

where

$$\begin{array}{c}a={\displaystyle \frac{1}{2R^{\prime }{C}_{1\_L}{C}_{gsL}\left(R_{3\_L}+R_{gL(in)}\right)}}\times \left\{\begin{array}{l}-\left[C_{gsL}\left(R_{3\_L}+R_{gL(in)}+R^{\prime }\right)+R^{\prime }{C}_{1\_L}\right]+\\ \sqrt{\begin{array}{l}{\left[C_{gsL}\left(R_{3\_L}+R_{gL(in)}+R^{\prime }\right)+R^{\prime }{C}_{1\_L}\right]}^2-\\ 4R^{\prime }{C}_{1\_L}{C}_{gsL}\left(R_{3\_L}+R_{gL(in)}\right)\end{array}}\end{array}\right\}\\ b={\displaystyle \frac{1}{2R^{\prime }{C}_{1\_L}{C}_{gsL}\left(R_{3\_L}+R_{gL(in)}\right)}}\times \left\{\begin{array}{l}-\left[C_{gsL}\left(R_{3\_L}+R_{gL(in)}+R^{\prime }\right)+R^{\prime }{C}_{1\_L}\right]-\\ \sqrt{\begin{array}{l}{\left[C_{gsL}\left(R_{3\_L}+R_{gL(in)}+R^{\prime }\right)+R^{\prime }{C}_{1\_L}\right]}^2-\\ 4R^{\prime }{C}_{1\_L}{C}_{gsL}\left(R_{3\_L}+R_{gL(in)}\right)\end{array}}\end{array}\right\}\end{array}$$

After collation, the following is further obtained:

$$I_{R3L\left(\max \right)}={\displaystyle \frac{C_{gdL}{V}_{DC}}{C_{gsL}(R_{3\_L}+R_{gL\left(in\right)})}}$$

(6)

Therefore, in order to make the voltage in resistor R_{3_L} meet the passive triggering condition of the transistor Q_{1_L}, resistor R_{3_L} should satisfy the following relationship [10]:

$$R_{3\_L}>{\displaystyle \frac{0.7C_{gsL}{R}_{gL\left(in\right)}}{C_{gdL}{V}_{DC}-0.7C_{gsL}}}$$

(7)

4.3. When the Auxiliary Branch Is Connected to the Gate Drive

When M₁ is turned on and M₂ is turned off, the auxiliary branch is connected to the gate drive. The equivalent circuit is shown in Figure 8.

Equation (8) is obtained by Kirchhoff’s law:

$$\{\begin{array}{c}{I}_{c2L}=C_{2\_L}{\displaystyle \frac{d{V}_{C_{2L}}}{dt}}\\ C_{dsL}{\displaystyle \frac{d{V}_{dsL}}{dt}}=I-I_{c2L}-I_g\\ V_{C_{2L}}+R_{gL\left(in\right)}{I}_{c2L}=V_{C_{gsL}}\\ {\displaystyle \frac{I_{c2L}+I_{gL}}{C_{gdL}}}+{\displaystyle \frac{I_{gL}}{C_{gsL}}}={\displaystyle \frac{I-I_{c2L}+I_{gL}}{C_{dsL}}}\end{array}$$

(8)

After collation, the expression of the voltage on capacitor C_{2_L} is:

$$V_{C_{2L}}={\displaystyle \frac{V_{dc}{C}_{gdL}(1-e^{\frac{V_{dc}\left(C_{2\_L}+C_{gsL}+C_{gdL}\right)}{k{R}_{gL\left(in\right)}{C}_{2\_L}\left(C_{gsL}+C_{gdL}\right)}})}{C_{2\_L}+C_{gsL}+C_{gdL}}}$$

(9)

where k = dv/dt, which indicates the switching rate of M₂.

Therefore, in order to ensure the effect of crosstalk suppression, the following relationship needs to be met:

$$\{\begin{array}{c}-V_{C_{1L}}+V_{C_{2L}}+0.7<V_{th}\\ -V_{C_{1L}}-V_{C_{2L}}-0.4>V_{\max (neg)}\end{array}$$

(10)

In short, the basic parameters of the designed gate drive are shown in

Table 2. Gate drive parameters list.

Symbol	Value
C1_n	100 pF
C2_n	100 pF
R1_n	$1000 \mathsf{\Omega }$
R2_n	$4700 \mathsf{\Omega }$
R3_n	$10 \mathsf{\Omega }$

, where n = H, L.

5. Simulation Verification of the Improved Crosstalk Suppression Gate Drive

The simulation of the synchronous buck circuit was based on LTspice. By changing the gate drive, the simulation results are compared and analyzed to verify the proposed gate drive. In actual circuits, the parasitic inductance is an unknown quantity, but the value of the parasitic inductance of the gate and source is usually not greater than 20 nH and has a negligible effect on power loop waveforms. In order to make the experimental conditions consistent, the value of the parasitic inductance of the gate and source is reduced by the rational design of hardware circuits when building the experimental platform, so the 2 nH inductance is added to the gate and source, respectively, to mimic the parasitic inductance in the simulation circuit.

In this study, the C2M0080120D SiC MOSFET produced by CREE was used for simulation, with a switching period of 10 μs. The selected PNP transistor was 2SAR512P, and the regulator diode was Schottky diode 1N5819. The DC side voltage of the synchronous buck circuit in the simulation was 300 V, the filtering inductance L was 500 μH, the filtering capacitance C was 470 μF, the duty cycle of the control MOSFET was 45%, and the dead time was set to 0.3 μs. The simulation models of the no-crosstalk suppression driver circuit, the active clamp drive circuit, and the improved driver circuit are shown in Figure 9, and the improved driver circuit was designed on the basis of the active clamp drive circuit.

In Figure 10, the gate-source voltages of the control switch transistor and synchronous switch transistor with a no-crosstalk suppression drive circuit, active clamp drive circuit, and improved drive circuit are compared when the upper transistor is turning on. Figure 10a shows the gate-source voltage of the control transistors, and Figure 10b shows the gate-source voltage of the synchronous transistor. When using the no-crosstalk suppression drive circuit, the positive crosstalk voltage is 4.81 V, and the negative crosstalk voltage is −4.23 V. When using the active clamp drive circuit, the positive crosstalk voltage is 2.32 V, and the negative crosstalk voltage is −5.83 V; when using the improved drive circuit, the positive crosstalk voltage is −0.05 V, and the negative crosstalk voltage is −1.47 V. As can be seen from Figure 9, active clamp circuit suppresses the positive crosstalk voltage but not the negative crosstalk voltage. The improved drive circuit can suppress both the positive and negative crosstalk voltages. In addition, the drive circuit does not disturb the switching time.

In Figure 11, when the control transistor is turned off, the gate-source voltages of the control switch transistor and synchronous switch transistor are compared in the no-crosstalk suppression drive circuit, the active clamp drive circuit, and the improved drive circuit. Figure 11a shows the gate-source voltage of the control transistors, and Figure 11b shows the gate-source voltage of the synchronous transistor. When using the no-crosstalk suppression drive circuit, the negative crosstalk voltage is −5.98 V. When using the active clamp drive circuit, the negative crosstalk voltage is −5.47 V; When using the improved drive circuit, the negative crosstalk voltage is −1.67 V. It can be concluded that the active clamp circuit suppresses the negative crosstalk voltage. The improved drive circuit can suppress the negative crosstalk voltage better. At the same time, the improved drive circuit also reduces the switching time.

Figure 12 shows the switching loss of the synchronous switch transistor, Figure 12a shows the switching loss of the synchronous transistor when the control transistor is turned on, and Figure 12b shows the switching loss of the synchronous tube when the control tube is turned off. As can be seen from Figure 12, the switching loss of the no-crosstalk suppression drive circuit is 43.67 μJ, the switching loss of the active clamp circuit is 35.14 μJ, and the switching loss of the improved drive circuit is 32.83 μJ.

In summary, the LTspice simulation results show that the crosstalk suppression gate drive designed in this paper suppresses the crosstalk voltage without sacrificing switching speed. In addition, the switching loss of the improved drive circuit is almost the same or even slightly reduced compared with the no-crosstalk suppression drive circuit and the active clamp drive circuit.

6. Experimental Verification of the Improved Crosstalk Suppression Gate Drive

In order to verify the designed improved crosstalk suppression gate drive, a synchronous buck circuit experimental platform based on SiC MOSFET is built, and the experimental scheme diagram is shown in Figure 13.

Figure 14 shows the experimental platform, which includes the driving circuit, synchronous buck converter, power supply, DSP28335, and oscilloscope. The experiment used DSP28335 to set PWM to control the driving circuit. The SiC MOSFET was CREE’s second-generation 1.2 kV SiC MOSFET semiconductor device C2M0080120D. The switching frequency was 100 KHz. The high-voltage side voltage was 300 V.

Figure 15 is the positive crosstalk voltage experimental waveform diagram; Figure 15a is the gate-source voltage waveform diagram of the upper and lower transistors V_gs, the drain-source voltage waveform diagram of the upper transistors V_dsH, and the drain current waveform diagram of the upper transistors i_dH of three gate drives. When using the conventional gate drive, the positive crosstalk voltage is 5.68 V, and the negative crosstalk voltage is −1.73 V. When using the active clamp drive circuit, the positive crosstalk voltage is 2.38 V, and the negative crosstalk voltage is −1.62 V. When using the designed crosstalk suppression circuit, the positive crosstalk voltage is −0.15 V, and the negative crosstalk voltage is −1.14 V. At the same time, the improved drive circuit also reduces the switching time.

Figure 16 is the negative crosstalk voltage experimental waveform diagram; Figure 16a is the gate-source voltage waveform diagram of the upper and lower transistors V_gs, the drain-source voltage waveform diagram of the upper transistors V_dsH, and the drain current waveform diagram of the upper transistors i_dH of three gate drives. When using the traditional gate drive, the positive crosstalk voltage is 2.13 V, the negative crosstalk voltage is −2.87 V, and the drain voltage peak is 411 V. When using the active clamp drive circuit, the positive crosstalk voltage is 0.47 V, the negative crosstalk voltage is −1.53 V, and the drain voltage peak is 392 V. When using the designed crosstalk suppression circuit, the positive crosstalk voltage is −0.05 V, the negative crosstalk voltage is −0.34 V, and the drain voltage peak is 375 V.

In summary, the gate drive designed in this paper has a small crosstalk voltage value that is always negative and has a significantly reduced positive and negative crosstalk voltage compared with the traditional gate drive and active clamp drive circuit.

7. Conclusions

The bridge circuit based on a SiC MOSFET is easily affected by parasitic parameters at high frequency and generates crosstalk voltage at the gate source, which greatly limits the application of the SiC MOSFET. To address this issue, a new gate drive was proposed, and it was verified by simulation and experimental methods. It can be concluded from the experimental results that the designed driver circuit compared with the traditional driver circuit can be better when the crosstalk voltage positive peak attenuation below 0 V, the maximum positive crosstalk voltage in the synchronous buck circuit test platform is −0.15 V and the negative crosstalk voltage is −0.34 V; it effectively reduces the negative crosstalk voltage, shortens the switching time of the SiC MOSFET, and reduces the drain voltage peaks. In addition, the devices used in the designed gate drive are passive devices, so the gate drive is easy to implement and does not require additional control signals; thus, the use of electronic components can be reduced. The device cost is lower than other traditional drive circuit that can be used for production.