1. Introduction
In recent years, due to the rapid growth of portable electronic devices, the demand for low-power and high-speed circuits has taken great attention for integrated circuits. The arithmetic and memory units are fundamental building blocks for most digital designs. Accordingly, the performance parameters of logic gates and circuits are continuously improving to achieve better efficiency.
Many papers have been published in the literature related to full adder and D-latch circuits. The main performance parameters of the integrated logic circuits are power consumption, propagation delay and power-delay product (PDP). Therefore, existing schemes have advantages or disadvantages relative to one another in terms of these performance parameter values. On the other hand, several design techniques are employed in digital logic circuit design, which uses different transistor types, methods and approaches. For example, full adders are based on CMOS logic [
1], transmission gate logic [
2] and other methods [
3,
4,
5,
6]. Additionally, some alternative D-latches use CMOS logic gates, while others use methods such as sense amplifier-based [
7], memristor-based [
8], pass transistor logic-based [
9], optical composite [
10], carbon nanotube field effect transistor (CNTFET)-based [
11], pseudo-NMOS-based [
12], and others. Hence, several different structures for designing arithmetic and memory buildings are currently being developed.
In this research paper, full adder and D-latch designs based on CMOS logic using GNRFETs at 7 nm technology nodes are presented. Firstly, NOT, NOR and NAND gates based on CMOS logic were implemented by using both classical silicon-based FETs and GNRFETs for comparison. Then, full adder and D-latch circuits based on CMOS logic were implemented by using these technologies in a similar manner. When compared to logic gate and circuit structures using MOS transistors, logic circuits using GNRFETs show both lower power consumption and lower propagation delay characteristics compared to the silicon-based counterparts at the 7 nm technology node. Moreover, a deep learning network was developed to model the power consumption and propagation delay of the GNRFET logic inverter. It was demonstrated that the developed deep learning network accurately represents the power consumption and the propagation delay dependent on the channel length. In
Section 2, the GNRFET model used in this study is explained. Then, logic circuit designs utilizing GNRFETs are given together with detailed analyses in
Section 3. The performance parameters of the logic circuits employing classical Si-based MOSFETs and GNRFETs are compared and discussed in
Section 4. The developed deep learning network for modeling the power consumption and the delay of the GNRFET inverter is presented in
Section 5. Finally, the overall results of this study are discussed in
Section 6.
2. Description of the Utilized GNRFET Model
GNRFETs are promising candidates for the post-silicon era nanoelectronics. The peculiar characteristics of GNRFETs stem from the properties of graphene nanoribbons (GNRs). Graphene is a single layer of carbon atoms arranged in a hexagonal lattice, which provides high carrier mobility, electron mobility and mechanical strength. These properties of GNRs make them ideal candidates for post-silicon nanoelectronics devices such as GNRFETs. In GNRFETs, the channel regions of the transistors are made of semiconducting graphene nanoribbons, where the energy level of this channel is modulated by the potential applied to the gate electrode. The high carrier mobility and near ballistic transport in graphene nanoribbon channels provide advantages such as ultra-low power operation and high switching speeds in digital circuits.
One of the important advantages of GNRFETs is their potential for scaling down to atomic dimensions. The nano-sized width of GNRs provide precise control over device dimensions at the nanoscale, enabling the fabrication of transistors with extremely small gate width and length sizes. This scalability opens up new possibilities for ultra large-scale integrated circuits having high performance and reduced energy consumption. A typical GNRFET structure is shown in
Figure 1.
The GNRFET device shown in
Figure 1 employs graphene nanoribbons operating as the channel region of the transistor. There may be one or more GNRs as the channel region, and the number of the GNRs are denoted by nRib. Armchair type GNRs are employed as the channel region of GNRFETs since they have semiconducting behavior. The structure of an armchair GNR is depicted in
Figure 2.
The number of dimer lines along the transport direction is denoted by
N, as shown in
Figure 2. In this case, the width of the armchair GNR is given by Equation (1) [
13].
In Equation (1),
aC-C is the bond distance between the adjacent carbon atoms, which is taken as 1.44 Å [
13]. On the other hand, it has been established in the literature that zigzag GNRs behave as metallic conductors while armchair GNRs behave as semiconductors or metallic conductors depending on the number of dimer lines. If the number of dimer lines is given as
N = 3p or
N = 3p + 1, then the armchair GNR is a high bandgap semiconductor, while for
N = 3p + 2, the armchair GNR behaves as a low bandgap semiconductor [
14,
15,
16].
4. Comparison of the Performances of Silicon-Based CMOS and GNRFET-Based CMOS Logic Blocks
In this section, the classical Si-based and new-generation GNRFET-based logic circuits are simulated, and their performances are compared. Simulation setups and
W-L values of the transistors are summarized in
Table 3. While
VDD = positive input voltage was 0.7 V, and
Vgnd = negative input voltage was 0 V. Operation frequency was 100 MHz. According to 7 nm CMOS process technology, the
Lp = Ln value is 7 nm. Whereas the transconductance of p-type MOS transistors was worse than that of the n-type MOS transistors, it was the same in GNR transistors. Therefore, the transconductance value of the p-type MOS transistor was doubled by increasing its channel region width in accordance with Equation (7).
where
gDS is the transconductance, µ
p is the electron mobility,
Cox is the oxide capacitance,
W is the canal region width,
L is the canal region length,
VGS is the gate-body voltages, and
Vt is the threshold voltage. On the other hand, for both p-type and n-type in GNR transistors,
W values were calculated in accordance with GNR properties given in Equation (8) [
17,
18].
where
N is the number of dimer lines, and
aC-C is the carbon–carbon bond length in nanometers, which is taken as
aC-C = 0.144 [
18,
19]. To equalize W values to 7 nm in GNR transistors, the
N number was 42. As for transistor model, 7 nm PTM transistor model is used for MOS based gates [
19], and a SPICE-compatible model [
20] is used for GNR-based ones.
Input–output signals of the GNR-based gates and circuits are indicated in
Figure 8,
Figure 9 and
Figure 10. Input and output signals of GNR-based NOT gates are displayed in
Figure 8a,b in voltage and time domains, respectively.
Figure 8a shows the voltage transfer characteristic (VTC), indicating that the margins of input logic 0 and logic 1 are equal to each other due to the fact that the midpoint of the graphic is equal to
VDD/2 in the voltage domain. In conclusion, GNR transistor-based gates and circuits generate desired output signals. Additionally, parasitic impulses seen in output signals at logic state transitions occur due to the capacitance effects of the transistor model.
For logic designs, it is important to operate circuits in full swing, which means the closer each output voltage is to the desired logic voltages, the more circuits operate in full swing. For this purpose, output voltages are given in
Table 4. Considering these output voltage values, it is seen that all GNR-based values are closer to the desired logic voltages than all MOS-based values. Thus, it is clear that using GNRFETs instead of MOSFETs makes all the examined structures operate closer to full swing in all input combinations.
Power consumption is an important performance parameter for integrated circuits. For this reason, power consumption values are given in
Table 5, both average and for all input combinations. In input combinations, GNRFET-based structures significantly show less power consumption than MOSFET based ones do. The power consumption advantages of logic circuits using GNRFETs are also given as percentages on
Table 5. When averagely compared to MOSFET-based situations, the usage of GNRFET approximately provided 78.6% greater energy efficiency.
Besides power consumption, propagation delay is also indispensable for performance evaluation. In a similar manner, propagation delay values are given in
Table 6 for both average and different logic transitions. The delay advantages of logic circuits using GNRFETs are also given as percentages in
Table 6. In conclusion, the usage of GNR transistors causes approximately 46% less propagation delay and approximately 53.2% less propagation delay. Moreover, the performances of the considered circuits were also evaluated by using the 7 nm FinFET model, which is another emerging technology [
20,
21,
22]. The HSPICE simulation results employing the 7 nm FinFET model are also given in
Table 4,
Table 5 and
Table 6. It can be observed from these values that the performance of the FinFET technology is between the performances of the Si-based CMOS and the GNRFET technologies for the considered logic circuits.
Most design techniques improving power consumption can affect propagation delay adversely, or vice versa, improving propagation delay can affect power consumption adversely. Accordingly, the PDP parameter is used to compare methods in terms of the balance between power consumption and propagation delay parameters. However, the usage of the GNRFET method provides affirmative results in terms of these parameters in all and average situations, so PDP parameter results are also affirmative in GNR-based structures.
5. A Deep Learning Network Design for Power Consumption and Delay Modeling of GNRFET Logic
The delay and power dissipation of the inverter employing GNRFETs were obtained using HSPICE simulations in the previous section. As can be seen from the computational results, the power and the delay values of the GNRFET inverter have different ranges for the cases of
N = 3p,
N = 3p + 1 and
N = 3p + 2. In this subsection, a deep learning model was developed to model both the power dissipation and the delay of the GNRFET for various values of the channel length. A deep learning multilayer perceptron (MLP) network, as shown in
Figure 11, was developed in this study for this aim [
23,
24]. The MLP-type architecture was selected as the modeling method, considering that these types of machine learning architectures are expected to give accurate results for regression problems involving relatively small size of datasets [
25,
26,
27,
28,
29].
The developed deep learning model consists of three hidden layers, each having 50 neurons, as shown in
Figure 11. The activation functions were chosen as rectified linear unit types where a feedforward architecture was employed. A total of 70% of the available data were used as training data, whereas the remaining 30% of the data were employed as test data. The designed deep learning model was implemented in Python programming language using the MLPRegressor() class of the SciKit-Learn module.
The power dissipation data of the GNRFET inverter were modeled using the developed deep learning network as the first step. The power dissipation data for the chirality cases of
N = 3p,
N = 3p + 1 and
N = 3p + 2 was separately modeled using the deep learning network. The size of the dataset was 21 for each chirality case, totaling 63 values in which the channel length of the transistors has values in the range of
L = 2.850 nm and
L = 11.125 nm. The dataset was directly modeled utilizing the developed deep learning network without any preprocessing. The actual power dissipation data and the deep learning model results are plotted in
Figure 12.
As can be observed from
Figure 12, the developed deep learning network can be used to model the power dissipation data. The performance metrics of the deep learning model results for the power dissipation data are also given in
Table 7, which verifies the accuracy of the developed deep learning model. In
Table 7, R
2 is the coefficient of determination, MAPE is the mean absolute percentage error, MAE is the mean absolute error, and RMSE is the root mean square error. These performance metrics were computed using the standard definitions of these parameters, as shown in Equations (9)–(12).
In addition, the power dissipation data was modeled using polynomial regression in MATLAB 2023b, employing the cftool module to compare the results of the developed deep learning MLP model to the regression fit. The obtained R
2 values for the polynomial regression model were 0.95, 0.84 and 0.91 for
N = 3p,
N = 3p + 1 and
N = 3p + 2 compared with 0.99, 0.99 and 0.94 for the developed deep learning MLP model. This difference is obviously due to the better nonlinear modeling capability of the deep learning network.
In these equations, d is the length of the data, O is the original data, and M is the data obtained from the developed deep learning model.
As the second step, the developed deep learning network was utilized to model the delay of the GNRFET inverter. The delay of the GNRFET inverter was modeled using the deep learning network separately for the cases of
N = 3p,
N = 3p + 1 and
N = 3p + 2. The actual delay data and the data obtained from the deep learning model are plotted in
Figure 13.
The deep learning network can also be used to model the delay data, as can be seen in
Figure 13. The performance metrics of the deep learning model for the delay data are given in
Table 8. Similar to the power dissipation modeling case, the delay data is also modeled using polynomial regression in MATLAB to compare the results of the deep learning MLP model and the polynomial regression. The obtained R
2 values for the regression model are 0.76, 0.89 and 0.72 for
N = 3p,
N = 3p + 1 and
N = 3p + 2 compared to 0.86, 0.96 and 0.92 for the deep learning model. The differences between the R
2 of the regression models and the deep learning model were higher for the delay modeling since the delay characteristics had stronger nonlinearity compared with the power dissipation characteristics, as can be observed from
Figure 12 and
Figure 13.
In summary, the developed deep learning model can be used to model both the power dissipation and the delay data of the GNRFET inverter, while the accuracy for the delay data was slightly lower compared with the power dissipation case due to the irregularities in the delay data.
As can be observed from the HSPICE simulations and the corresponding deep learning network models, the GNRFET logic circuits display clear advantages from both power consumption and delay points of view. The average power dissipation advantage of the considered logic circuits employing GNRFETs was 78.6%, while the delay advantage was calculated to be 53.2%, which shows that the logic circuits employing GNRFETs are advantageous compared with their classical Si-based counterparts. Considering that practical digital integrated circuits employ millions of basic logic circuits, the delay and the power consumption advantages of the GNRFET logic circuits show that the GNRFET integrated circuit technology is worth the investment.
The developed deep learning network for the modeling of the power consumption and the delay is useful for cases where the power consumption and the delay of logic circuits employing millions of GNRFETs need to be estimated without performing time-consuming full HSPICE simulations. Moreover, it can be observed from the coefficient of determination values presented in
Table 7 and
Table 8 that the developed MLP deep learning model provides the required accuracy for modeling the power dissipation and the delay of the considered logic circuits. In addition, to generalize the developed deep learning models to other technology nodes, transfer learning can be used where the pre-trained model is fine-tuned on a new dataset regarding other technology nodes. Increasing the diversity of the training dataset also enhances generalization by exposing the model to a wider range of nodes. Moreover, techniques like data augmentation and regularization can be used to prevent overfitting and improve the model’s adaptability to new datasets.