Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology

Abstract

The interest in alternative logic technologies is continuously increasing for short nanometer designs. From this viewpoint, logic gates, full adder and D-latch designs based on graphene nanoribbon field effect transistors (GNRFETs) at 7 nm technology nodes were presented, considering that these structures are core elements for digital integrated circuits. Firstly, NOT, NOR and NAND gates were implemented using GNRFETs. Then, 28T full adder and 18T D-latch circuits based on CMOS logic were designed using GNRFETs. As the first result of this work, it was shown through HSPICE simulations that the average power consumption of the considered logic circuits employing GNRFETs was 78.6% lower than those built using classical Si-based MOSFETs. Similarly, the delay advantage of the logic circuits employing GNRFETs was calculated to be 53.2% lower than those using Si-based MOSFET counterparts. In addition, a deep learning model was developed to model both the power consumption and the propagation delay of GNRFET-based logic inverters. As the second result, it was demonstrated that the developed deep learning model could accurately represent the power consumption and delay of GNRFET-based logic circuits with the coefficient of determination (R²) values in the range of 0.86 and 0.99.

1. Introduction

In recent years, due to the rapid growth of portable electronic devices, the demand for low-power and high-speed circuits has taken great attention for integrated circuits. The arithmetic and memory units are fundamental building blocks for most digital designs. Accordingly, the performance parameters of logic gates and circuits are continuously improving to achieve better efficiency.

Many papers have been published in the literature related to full adder and D-latch circuits. The main performance parameters of the integrated logic circuits are power consumption, propagation delay and power-delay product (PDP). Therefore, existing schemes have advantages or disadvantages relative to one another in terms of these performance parameter values. On the other hand, several design techniques are employed in digital logic circuit design, which uses different transistor types, methods and approaches. For example, full adders are based on CMOS logic [1], transmission gate logic [2] and other methods [3,4,5,6]. Additionally, some alternative D-latches use CMOS logic gates, while others use methods such as sense amplifier-based [7], memristor-based [8], pass transistor logic-based [9], optical composite [10], carbon nanotube field effect transistor (CNTFET)-based [11], pseudo-NMOS-based [12], and others. Hence, several different structures for designing arithmetic and memory buildings are currently being developed.

In this research paper, full adder and D-latch designs based on CMOS logic using GNRFETs at 7 nm technology nodes are presented. Firstly, NOT, NOR and NAND gates based on CMOS logic were implemented by using both classical silicon-based FETs and GNRFETs for comparison. Then, full adder and D-latch circuits based on CMOS logic were implemented by using these technologies in a similar manner. When compared to logic gate and circuit structures using MOS transistors, logic circuits using GNRFETs show both lower power consumption and lower propagation delay characteristics compared to the silicon-based counterparts at the 7 nm technology node. Moreover, a deep learning network was developed to model the power consumption and propagation delay of the GNRFET logic inverter. It was demonstrated that the developed deep learning network accurately represents the power consumption and the propagation delay dependent on the channel length. In Section 2, the GNRFET model used in this study is explained. Then, logic circuit designs utilizing GNRFETs are given together with detailed analyses in Section 3. The performance parameters of the logic circuits employing classical Si-based MOSFETs and GNRFETs are compared and discussed in Section 4. The developed deep learning network for modeling the power consumption and the delay of the GNRFET inverter is presented in Section 5. Finally, the overall results of this study are discussed in Section 6.

2. Description of the Utilized GNRFET Model

GNRFETs are promising candidates for the post-silicon era nanoelectronics. The peculiar characteristics of GNRFETs stem from the properties of graphene nanoribbons (GNRs). Graphene is a single layer of carbon atoms arranged in a hexagonal lattice, which provides high carrier mobility, electron mobility and mechanical strength. These properties of GNRs make them ideal candidates for post-silicon nanoelectronics devices such as GNRFETs. In GNRFETs, the channel regions of the transistors are made of semiconducting graphene nanoribbons, where the energy level of this channel is modulated by the potential applied to the gate electrode. The high carrier mobility and near ballistic transport in graphene nanoribbon channels provide advantages such as ultra-low power operation and high switching speeds in digital circuits.

One of the important advantages of GNRFETs is their potential for scaling down to atomic dimensions. The nano-sized width of GNRs provide precise control over device dimensions at the nanoscale, enabling the fabrication of transistors with extremely small gate width and length sizes. This scalability opens up new possibilities for ultra large-scale integrated circuits having high performance and reduced energy consumption. A typical GNRFET structure is shown in Figure 1.

The GNRFET device shown in Figure 1 employs graphene nanoribbons operating as the channel region of the transistor. There may be one or more GNRs as the channel region, and the number of the GNRs are denoted by nRib. Armchair type GNRs are employed as the channel region of GNRFETs since they have semiconducting behavior. The structure of an armchair GNR is depicted in Figure 2.

The number of dimer lines along the transport direction is denoted by N, as shown in Figure 2. In this case, the width of the armchair GNR is given by Equation (1) [13].

$$W={\displaystyle \frac{\sqrt{3}}{2}}(N-1)a_{C-C}$$

(1)

In Equation (1), a_C-C is the bond distance between the adjacent carbon atoms, which is taken as 1.44 Å [13]. On the other hand, it has been established in the literature that zigzag GNRs behave as metallic conductors while armchair GNRs behave as semiconductors or metallic conductors depending on the number of dimer lines. If the number of dimer lines is given as N = 3p or N = 3p + 1, then the armchair GNR is a high bandgap semiconductor, while for N = 3p + 2, the armchair GNR behaves as a low bandgap semiconductor [14,15,16].

3. Logic Design Employing GNRFETs

3.1. NOT, NOR and NAND Gates

NOT, NOR and NAND are basic gates of CMOS logic; therefore, it is useful to examine these circuits before the design of more complex circuits. Input–output relations of the NOT, NOR and NAND gates are defined in Equations (2)–(4). The NOT generates complementary input, NOR generates complementary logic sum of inputs, and NAND generates complementary logic multiply of inputs.

$$NOT=\overline{A}$$

(2)

$$NOR=\overline{A+B}$$

(3)

$$NAND=\overline{AB}$$

(4)

Many papers have been published pertaining to the NOT, NOR and NAND gates in the literature, and they have still been in the process of development. These gates can be obtained in various forms. One and most common of them is CMOS technology using MOS transistors, which are shown in Figure 3. As seen in this figure, while NOT comprises two transistors, NOR and NAND comprise four MOS transistors.

3.2. Full Adder

Full adder circuits are fundamental building blocks of many digital designs in integrated circuit technology. The input–output relations of full adder circuits are defined in Equations (5) and (6). A full adder circuit has at least three inputs: two of them will be added, and the other one from the previous digit will also be added. Furthermore, it has two outputs: the carry to the next digit and the sum.

$$Co=A(B ⨁ Ci)+Ci\left(\overline{B ⨁ Ci}\right)$$

(5)

$$Sum=(A ⨁ B) ⨁ Ci$$

(6)

Circuit block representation and logic states of a basic full adder are shown in Figure 4 and

Table 1. Logic states of full adder.

Ci	A	B	Co	Sum	Result
0	0	0	0	0	(0)10
0	0	1	0	1	(1)10
0	1	0	0	1	(1)10
0	1	1	1	0	(2)10
1	0	0	0	1	(1)10
1	0	1	1	0	(2)10
1	1	0	1	0	(2)10
1	1	1	1	1	(3)10

, respectively.

A common full adder has three inputs, so eight logic combination states are included for three inputs.

A common full adder circuit can be designed by using multiple methods. One well-known example is shown in Figure 5, which shows the CMOS logic method comprising p-type and n-type transistors. This design employs 28 transistors, where half of them are p-type and the rest are n-type.

3.3. D-Latch

Latch circuits are fundamental building blocks of many digital designs used to compose VLSI. Symbol and logic states of a D-latch are indicated in Figure 6 and

Table 2. Logic states of D-latch.

D	Clk	Qn	Qn′
0	0	Qc	Qc’
0	1	0	1
1	0	Qc	Qc′
1	1	1	0

Q_c = Q_current → state before Clk. Q_n = Q_next → state after Clk.

, respectively.

This latch structure has two inputs and two outputs. D (data) and Clk (clock) are inputs, and Q and Q′, complementary of each other, are outputs. This memory circuit can be designed using multiple methods. As one of the simplest and well-known, Figure 7 shows a method of D-latch circuit design comprising four NAND gates and one NOT gate. This design method has 18 transistors: half of them are of the p-type, and the rest are n-type, as in the full adder.

4. Comparison of the Performances of Silicon-Based CMOS and GNRFET-Based CMOS Logic Blocks

In this section, the classical Si-based and new-generation GNRFET-based logic circuits are simulated, and their performances are compared. Simulation setups and W-L values of the transistors are summarized in

Table 3. Simulation setups.

Parame	Design	Unit	Value
Vdd = Vi+	Both	V	0.7
Vgnd = Vi−	Both	V	0
Input wave	Both	-	Square
Input frequency	Both	MHz	100
R (load)	Both	MΩ	1000
Wp/Wn	MOS	nm	14/7
Wp = Wn	GNR	nm	7/7
Lp = Ln	Both	nm	7/7
Np = Nn	GNR	-	42

. While V_DD = positive input voltage was 0.7 V, and V_gnd = negative input voltage was 0 V. Operation frequency was 100 MHz. According to 7 nm CMOS process technology, the L_p = L_n value is 7 nm. Whereas the transconductance of p-type MOS transistors was worse than that of the n-type MOS transistors, it was the same in GNR transistors. Therefore, the transconductance value of the p-type MOS transistor was doubled by increasing its channel region width in accordance with Equation (7).

$$g_{DS}={[\mu }_p{C}_{ox}({\displaystyle \frac{W}{L}})(V_{GS}-{|V}_t|)],$$

(7)

where g_DS is the transconductance, µ_p is the electron mobility, C_ox is the oxide capacitance, W is the canal region width, L is the canal region length, V_GS is the gate-body voltages, and V_t is the threshold voltage. On the other hand, for both p-type and n-type in GNR transistors, W values were calculated in accordance with GNR properties given in Equation (8) [17,18].

$$W=\left(N-1\right)\sqrt{3}\left({\displaystyle \frac{a_{C-C}}{2}}\right),$$

(8)

where N is the number of dimer lines, and a_C-C is the carbon–carbon bond length in nanometers, which is taken as a_C-C = 0.144 [18,19]. To equalize W values to 7 nm in GNR transistors, the N number was 42. As for transistor model, 7 nm PTM transistor model is used for MOS based gates [19], and a SPICE-compatible model [20] is used for GNR-based ones.

Input–output signals of the GNR-based gates and circuits are indicated in Figure 8, Figure 9 and Figure 10. Input and output signals of GNR-based NOT gates are displayed in Figure 8a,b in voltage and time domains, respectively. Figure 8a shows the voltage transfer characteristic (VTC), indicating that the margins of input logic 0 and logic 1 are equal to each other due to the fact that the midpoint of the graphic is equal to V_DD/2 in the voltage domain. In conclusion, GNR transistor-based gates and circuits generate desired output signals. Additionally, parasitic impulses seen in output signals at logic state transitions occur due to the capacitance effects of the transistor model.

For logic designs, it is important to operate circuits in full swing, which means the closer each output voltage is to the desired logic voltages, the more circuits operate in full swing. For this purpose, output voltages are given in

Table 4. Logic voltages (mV) at f = 100 MHz.

Circuit/Input	111	110	101	100	011	010	001	000
NOT-MOS	-	-	-	-	-	-	9.41	692.52
NOT-Fin	-	-	-	-	-	-	0.45	699.27
NOT-GNR	-	-	-	-	-	-	1.61	698.38
NOR-MOS	-	-	-	-	0.14	4.46	7.68	672.52
NOR-Fin	-	-	-	-	0.00	0.32	0.43	697.09
NOR-GNR	-	-	-	-	0.14	1.43	1.52	693.58
NAND-MOS	-	-	-	-	33.36	695.70	693.38	699.82
NAND-Fin	-	-	-	-	1.78	699.39	699.28	699.95
NAND-GNR	-	-	-	-	6.39	698.57	698.48	699.86
FA-Co-MOS	692.44	688.27	689.14	11.77	690.32	12.63	13.28	9.51
FA-Co-Fin	699.27	699.24	699.24	0.48	699.25	0.48	0.49	0.45
FA-Co-GNR	698.35	698.03	698.04	1.97	698.03	1.95	1.96	1.64
FA-Sum-MOS	687.72	13.88	14.13	688.52	13.25	687.52	688.06	14.52
FA-Sum-Fin	699.22	0.50	0.47	699.24	0.50	699.24	699.24	0.52
FA-Sum-GNR	697.58	1.99	2.01	698.00	2.00	697.99	698.00	2.41
DL-Q-MOS	-	-	-	-	699.64	37.05	34.99	692.59
DL-Q-Fin	-	-	-	-	699.95	1.81	1.80	699.37
DL-Q-GNR	-	-	-	-	699.82	6.77	6.59	698.22

. Considering these output voltage values, it is seen that all GNR-based values are closer to the desired logic voltages than all MOS-based values. Thus, it is clear that using GNRFETs instead of MOSFETs makes all the examined structures operate closer to full swing in all input combinations.

Power consumption is an important performance parameter for integrated circuits. For this reason, power consumption values are given in

Table 5. Power consumption (nW) at f = 100 MHz.

Circuit/Input	Avg. Power (nW)	PGNR /PMOS	111	110	101	100	011	010	001	000
NOT-MOS	1250.60	18.50%	-	-	-	-	-	-	1514.80	986.45
NOT-Fin	625.72		-	-	-	-	-	-	580.42	671.03
NOT-GNR	231.40		-	-	-	-	-	-	226.28	236.52
NOR-MOS	945.39	24.56%	-	-	-	-	44.56	735.30	1241.40	1760.30
NOR-Fin	583.61		-	-	-	-	28.84	404.76	567.89	1332.0
NOR-GNR	232.19		-	-	-	-	41.22	204.02	218.75	464.77
NAND-MOS	1025.00	22.94%	-	-	-	-	2602.50	574.06	876.26	47.21
NAND-Fin	610.88		-	-	-	-	1153.80	552.27	660.92	76.50
NAND-GNR	235.11		-	-	-	-	475.08	206.99	217.65	40.73
FA-MOS	6570.30	21.38%	4335.20	7731.60	7387.50	6518.90	6222.60	7505.90	7561.40	5299.20
FA-Fin	3378.30		2555.40	3700.10	3637.00	3428.30	3305.90	3711.50	3667.90	3019.80
FA-GNR	1404.90		1270.50	1437.60	1458.50	1447.40	1445.70	1446.10	1470.20	1263.30
DL-MOS	6790.60	19.50%	-	-	-	-	7564.20	6465.20	7410.10	5722.60
DL-Fin	3382.10		-	-	-	-	3539.00	3080.10	3746.70	3162.50
DL-GNR	1324.30		-	-	-	-	1413.00	1217.30	1443.90	1223.00

, both average and for all input combinations. In input combinations, GNRFET-based structures significantly show less power consumption than MOSFET based ones do. The power consumption advantages of logic circuits using GNRFETs are also given as percentages on Table 5. When averagely compared to MOSFET-based situations, the usage of GNRFET approximately provided 78.6% greater energy efficiency.

Besides power consumption, propagation delay is also indispensable for performance evaluation. In a similar manner, propagation delay values are given in

Table 6. Propagation delay (ps) at f = 100 MHz.

Circuit/Delay	Average Delay	Delay Ratio (MOS/GNR)	td4	td3	td2	td1
NOT-MOS	1.15	43.48%	-	-	0.87	1.44
NOT-Fin	1.19		-	-	0.59	1.79
NOT-GNR	0.50		-	-	0.45	0.55
NOR-MOS	1.84	65.67%	-	-	none	3.67
NOR-Fin	1.77		-	-	none	3.54
NOR-GNR	1.21		-	-	none	2.41
NAND-MOS	0.88	77.14%	-	-	1.75	none
NAND-Fin	0.92		-	-	1.84	none
NAND-GNR	0.68		-	-	1.35	none
FA-Co-MOS	4.09	34.47%	5.05	2.69	5.12	3.49
FA-Co-Fin	3.07		3.82	1.62	3.84	2.97
FA-Co-GNR	1.06		1.86	none	0.79	1.59
FA-Sum-MOS	6.73	18.57%	14.07	8.90	3.63	0.30
FA-Sum-Fin	6.15		13.60	7.78	3.22	none
FA-Sum-GNR	0.31		none	1.25	none	none
DL-MOS	5.79	40.93%	-	-	4.05	7.52
DL-Fin	5.19		-	-	3.68	6.71
DL-GNR	2.37		-	-	1.99	2.75

for both average and different logic transitions. The delay advantages of logic circuits using GNRFETs are also given as percentages in Table 6. In conclusion, the usage of GNR transistors causes approximately 46% less propagation delay and approximately 53.2% less propagation delay. Moreover, the performances of the considered circuits were also evaluated by using the 7 nm FinFET model, which is another emerging technology [20,21,22]. The HSPICE simulation results employing the 7 nm FinFET model are also given in Table 4, Table 5 and Table 6. It can be observed from these values that the performance of the FinFET technology is between the performances of the Si-based CMOS and the GNRFET technologies for the considered logic circuits.

Most design techniques improving power consumption can affect propagation delay adversely, or vice versa, improving propagation delay can affect power consumption adversely. Accordingly, the PDP parameter is used to compare methods in terms of the balance between power consumption and propagation delay parameters. However, the usage of the GNRFET method provides affirmative results in terms of these parameters in all and average situations, so PDP parameter results are also affirmative in GNR-based structures.

5. A Deep Learning Network Design for Power Consumption and Delay Modeling of GNRFET Logic

The delay and power dissipation of the inverter employing GNRFETs were obtained using HSPICE simulations in the previous section. As can be seen from the computational results, the power and the delay values of the GNRFET inverter have different ranges for the cases of N = 3p, N = 3p + 1 and N = 3p + 2. In this subsection, a deep learning model was developed to model both the power dissipation and the delay of the GNRFET for various values of the channel length. A deep learning multilayer perceptron (MLP) network, as shown in Figure 11, was developed in this study for this aim [23,24]. The MLP-type architecture was selected as the modeling method, considering that these types of machine learning architectures are expected to give accurate results for regression problems involving relatively small size of datasets [25,26,27,28,29].

The developed deep learning model consists of three hidden layers, each having 50 neurons, as shown in Figure 11. The activation functions were chosen as rectified linear unit types where a feedforward architecture was employed. A total of 70% of the available data were used as training data, whereas the remaining 30% of the data were employed as test data. The designed deep learning model was implemented in Python programming language using the MLPRegressor() class of the SciKit-Learn module.

The power dissipation data of the GNRFET inverter were modeled using the developed deep learning network as the first step. The power dissipation data for the chirality cases of N = 3p, N = 3p + 1 and N = 3p + 2 was separately modeled using the deep learning network. The size of the dataset was 21 for each chirality case, totaling 63 values in which the channel length of the transistors has values in the range of L = 2.850 nm and L = 11.125 nm. The dataset was directly modeled utilizing the developed deep learning network without any preprocessing. The actual power dissipation data and the deep learning model results are plotted in Figure 12.

As can be observed from Figure 12, the developed deep learning network can be used to model the power dissipation data. The performance metrics of the deep learning model results for the power dissipation data are also given in

Table 7. Performance metrics of the developed deep learning model for the power dissipation data.

Power Dissipation	R2	MAPE	MAE	RMSE
for N = 3p	0.99	0.04	1.42	1.85
for N = 3p + 1	0.99	0.15	1.61	2.90
for N = 3p + 2	0.94	0.03	3.74	8.23

, which verifies the accuracy of the developed deep learning model. In Table 7, R² is the coefficient of determination, MAPE is the mean absolute percentage error, MAE is the mean absolute error, and RMSE is the root mean square error. These performance metrics were computed using the standard definitions of these parameters, as shown in Equations (9)–(12).

In addition, the power dissipation data was modeled using polynomial regression in MATLAB 2023b, employing the cftool module to compare the results of the developed deep learning MLP model to the regression fit. The obtained R² values for the polynomial regression model were 0.95, 0.84 and 0.91 for N = 3p, N = 3p + 1 and N = 3p + 2 compared with 0.99, 0.99 and 0.94 for the developed deep learning MLP model. This difference is obviously due to the better nonlinear modeling capability of the deep learning network.

$$R^2={\displaystyle \frac{{\sum }_1^d{\left(O-avg\left(O\right)\right)}^2-{\sum }_1^d{\left(O-M\right)}^2}{{\sum }_1^d{\left(O-avg\left(O\right)\right)}^2}}$$

(9)

$$MAPE={\displaystyle \frac{100}{d}}{\sum }_1^d\left|{\displaystyle \frac{O-M}{M}}\right|$$

(10)

$$MAE={\displaystyle \frac{{\sum }_1^d\left|O-M\right|}{d}}$$

(11)

$$RMSE=\sqrt{{\displaystyle \frac{{\sum }_1^d{\left(O-M\right)}^2}{d}}}$$

(12)

In these equations, d is the length of the data, O is the original data, and M is the data obtained from the developed deep learning model.

As the second step, the developed deep learning network was utilized to model the delay of the GNRFET inverter. The delay of the GNRFET inverter was modeled using the deep learning network separately for the cases of N = 3p, N = 3p + 1 and N = 3p + 2. The actual delay data and the data obtained from the deep learning model are plotted in Figure 13.

The deep learning network can also be used to model the delay data, as can be seen in Figure 13. The performance metrics of the deep learning model for the delay data are given in

Table 8. Performance metrics of the developed deep learning model for the delay data.

Delay	R2	MAPE	MAE	RMSE
for N = 3p	0.86	0.14	0.05	0.07
for N = 3p + 1	0.96	0.31	0.07	0.13
for N = 3p + 2	0.92	0.27	0.02	0.03

. Similar to the power dissipation modeling case, the delay data is also modeled using polynomial regression in MATLAB to compare the results of the deep learning MLP model and the polynomial regression. The obtained R² values for the regression model are 0.76, 0.89 and 0.72 for N = 3p, N = 3p + 1 and N = 3p + 2 compared to 0.86, 0.96 and 0.92 for the deep learning model. The differences between the R² of the regression models and the deep learning model were higher for the delay modeling since the delay characteristics had stronger nonlinearity compared with the power dissipation characteristics, as can be observed from Figure 12 and Figure 13.

In summary, the developed deep learning model can be used to model both the power dissipation and the delay data of the GNRFET inverter, while the accuracy for the delay data was slightly lower compared with the power dissipation case due to the irregularities in the delay data.

As can be observed from the HSPICE simulations and the corresponding deep learning network models, the GNRFET logic circuits display clear advantages from both power consumption and delay points of view. The average power dissipation advantage of the considered logic circuits employing GNRFETs was 78.6%, while the delay advantage was calculated to be 53.2%, which shows that the logic circuits employing GNRFETs are advantageous compared with their classical Si-based counterparts. Considering that practical digital integrated circuits employ millions of basic logic circuits, the delay and the power consumption advantages of the GNRFET logic circuits show that the GNRFET integrated circuit technology is worth the investment.

The developed deep learning network for the modeling of the power consumption and the delay is useful for cases where the power consumption and the delay of logic circuits employing millions of GNRFETs need to be estimated without performing time-consuming full HSPICE simulations. Moreover, it can be observed from the coefficient of determination values presented in Table 7 and Table 8 that the developed MLP deep learning model provides the required accuracy for modeling the power dissipation and the delay of the considered logic circuits. In addition, to generalize the developed deep learning models to other technology nodes, transfer learning can be used where the pre-trained model is fine-tuned on a new dataset regarding other technology nodes. Increasing the diversity of the training dataset also enhances generalization by exposing the model to a wider range of nodes. Moreover, techniques like data augmentation and regularization can be used to prevent overfitting and improve the model’s adaptability to new datasets.

6. Conclusions

In this work, a 7 nm GNRFET technology was employed to design NOT, NOR, and NAND gates, full adder, and D-latch circuits based on CMOS logic at 0.7 V supply voltage. The first contribution of this work was the comparison of the 7 nm GNRFET logic performance to the equivalent silicon-based CMOS logic circuits. The power consumption and propagation delay parameters of the GNRFET and conventional silicon-based logic circuits were obtained using industry-standard HSPICE computations. Considering the simulation results, the GNRFET-based logic circuits show lower power consumption and propagation delay than their silicon-based counterparts. Obtaining lower values for both the power consumption and the propagation delay is crucial since most classical designs have a trade-off between these performance parameters, while GNRFET technology enables the improvement of both parameters together. The second contribution of this work is the development of a deep-learning MLP network, which enables the model of the power consumption and the propagation delay of GNRFET logic circuits accurately. The developed deep learning model has a coefficient of determination values in the range of 0.86 and 0.92 for the modeling of the power consumption and the propagation delay dependent on the channel length, implying the accuracy of the model for representing the power consumption and delay of GNRFET logic circuits. The developed model is supposed to be useful for nanometer-scale integrated circuit designers in practice for simulating the delays and the power dissipations of logic circuits having a vast number of inverters and other basic building blocks employing GNRFETs.