Optimization Method of SiC MOSFET Switching Trajectory Based on Variable Current Drive

Abstract

Silicon carbide (SiC) MOSFETs exhibit superior performance compared to traditional silicon (Si) MOSFETs, characterized by faster switching speeds, lower on-resistance, higher breakdown voltage, and greater operational temperature tolerance. These attributes make SiC MOSFETs highly suitable for applications in electric vehicles, charging stations, and mobile devices. However, their rapid switching speed can intensify current and voltage overshoot and oscillations during device switching, leading to increased device losses or potential damage. To address this issue, this paper proposes a current-type active gate drive (AGD) circuit. The circuit first detects the rate of change in the drain current and drain-source voltage. Subsequently, it employs an analog amplifier circuit and adjustable drive resistors to decelerate the rate of change in the drain-source voltage and drain current. As a result, overshoot and oscillation in the drain-source voltage and drain current are mitigated. Experimental results demonstrate that the proposed AGD circuit can reduce drain current overshoot by 60%, drain-source voltage overshoot by 15.38%, and waveform oscillations. Additionally, the AGD circuit decreases conduction and turn-off losses by 24% and effectively mitigates electromagnetic interference (EMI) issues within the frequency range of 0.1 to 3 MHz.

1. Introduction

Power devices are the cornerstone of power electronics technology, playing a pivotal role in their advancement towards higher frequencies and greater power densities [1,2,3]. Recently, SiC power devices, emblematic of wide-bandgap materials, have experienced rapid development. These devices boast superior bandwidth, critical breakdown electric field strength, and thermal conductivity, making them ideal for high-frequency, high-voltage, high-temperature, and high-current applications [4,5,6]. Consequently, they address the performance limitations of silicon-based devices. However, excessive rates of change in drain current (dI_d/dt) and drain-source voltage (dV_ds/dt) can induce switching overshoots and oscillations. These phenomena not only increase switching losses and exacerbate electromagnetic interference but may also cause device malfunction and compromise reliability [7,8].

Conventional resistor–capacitor–diode (RCD) snubber circuits effectively reduce voltage spikes and oscillations, but they cannot be dynamically adjusted. In contrast, active gate drive (AGD) circuits can more precisely control the switching device’s on and off processes to adapt to varying load conditions and switching states. This allows for the delivery of more drive current when needed, facilitating quicker changes in the gate state of charge, resulting in reduced switching times and lower voltage spikes and oscillations. Active drive circuits optimize switching times, reduce switching losses, and improve overall system efficiency. Unlike traditional RCD snubber circuits, which continuously dissipate energy as heat, active drive circuits provide electrical isolation that maintains stable gate voltage and avoid voltage fluctuations even during fast switching transients [9]. It is crucial for ensuring the reliability of metal–oxide–semiconductor field-effect transistors (MOSFETs) and preventing avalanche breakdown.

The conventional gate driver (CGD) circuit can reduce the switching speed of the power device by adjusting the gate drive voltage or resistance, thereby mitigating current and voltage overshoot. However, this method impacts the entire switching process of the SiC metal–oxide–semiconductor field-effect transistor (MOSFET), leading to increased additional loss. In contrast, AGDs not only effectively reduce this additional loss while controlling switching speed but also allow for adjustments in gate voltage or current during voltage and current spikes in the SiC MOSFET switching process. Various active gate driver techniques for controlling the dv/dt and di/dt of Si insulated-gate bipolar transistors (IGBTs) are reported in references [10,11]. A two-stage digital gate driving method for arresting ringing in power devices is presented in references [12,13]. Reference [14] integrates both CGD and AGD methods to minimize losses and voltage fluctuations. References [15,16,17,18] employ multi-stage drive voltages and resistors to achieve gate drive current adaptability, reducing the drive current during the switching stage when voltage oscillations need to be suppressed and increasing it in other stages to reduce switching losses. Reference [19] utilizes complex programmable logic devices to achieve multilevel control of the switching process, effectively suppressing the turn-off voltage overshoot of SiC MOSFETs, though the complex circuitry increases the design difficulty and cost of the gate driver. Reference [20] proposed a current injection active driver circuit that effectively suppresses current and voltage overshoots by detecting the di/dt of SiC MOSFETs and injecting currents into the gate at specific stages. However, it cannot suppress current and voltage oscillations during the switching process of SiC MOSFETs. The current source active gate drive (ACGD) circuit as described in reference [21] employs the triode amplification principle to inject current into the gate. This approach effectively reduces turn-off voltage spikes and turn-on current spikes in SiC MOSFETs but it does not significantly suppress oscillations in these devices.

To address the aforementioned issues, this paper first analyzes the SiC MOSFET switching process in stages. The parameter changes in each stage are described in detail, and the generation mechanisms of turn-on current overshoot and turn-off voltage overshoot are examined. Additionally, the oscillation generation mechanism of the SiC MOSFET switching process is analyzed through double pulse experimental circuit modeling. Based on these mechanisms, an active driver circuit is designed. This circuit detects the SiC MOSFET drain current and drain-source voltage during the current spike and voltage spike phases. During these phases, the gate drive current is reduced, and the gate drive resistance is increased to effectively mitigate current and voltage spikes and oscillations. Finally, PSpice simulation experiments and physical verification experiments are conducted.

2. Overshoot Analysis of SiC MOSFET Switching Process

Figure 1 illustrates a double pulse test circuit used to analyze the switching process of SiC MOSFETs and measure their switching characteristics [22]. The components in the circuit include U_in (DC input voltage), C_in (energy storage capacitance), L_p (bus parasitic inductance), L_load (load inductance), Q₁ (SiC MOSFET under test), Q₂ (SiC MOSFET under test), L_d (SiC MOSFET drain parasitic inductance), L_s (SiC MOSFET source parasitic inductance), and L_g (SiC MOSFET gate parasitic inductance). R_g is the gate drive resistor. D_f is the SiC MOSFET parasitic diode. C_gs is the SiC MOSFET gate-source parasitic capacitance. C_gd is the SiC MOSFET gate-drain parasitic capacitance and C_ds is the SiC MOSFET drain-source parasitic capacitance.

A typical SiC MOSFET turn-on transient waveform is shown in Figure 2. V_CC represents the positive driving voltage and V_EE represents the negative driving voltage of the SiC MOSFET. V_gs denotes the gate-source voltage, while I_g indicates the driving current. V_miller refers to the Miller plateau and V_th is the turn-on threshold voltage of the SiC MOSFET. V_ds is the voltage across the drain-source terminals and I_d is the drain current. I_rr represents the drain current overshoot and I_L is the load current. The turn-on process of the SiC MOSFET is divided into five stages, which are as follows:

Stage 1 [t₁~t₂]: Driving voltage rise stage. V_gs increases from V_EE to V_th. During this stage, the SiC MOSFET remains in the pinch-off region and does not conduct.

Stage 2 [t₂~t₃]: Drain current rise stage. At t₂, the device transitions from the pinch-off region to the constant current region. V_gs increases from V_th to the Miller platform V_miller, and I_d begins to rise.

Stage 3 [t₃~t₄]: Drain current overshoot stage. The drain current overshoot is caused by the charging of the junction capacitance of the continuity diode. The charging current I_rr is superimposed with the current of the load inductance, resulting in a continuous increase in the SiC MOSFET drain current I_d. This current reaches its peak I_dpeak at t₄. The peak drain current I_dpeak can be calculated using Equation (1):

$$I_{\mathrm{dpeak}}=I_{\mathrm{L}}+I_{\mathrm{rr}}$$

(1)

The peak drain current is influenced by I_rr, which is directly proportional to the I_d conversion rate, as expressed in Equation (2).

$$I_{\mathrm{rr}}=\sqrt{Q_{\mathrm{rr}}{\displaystyle \frac{d{I}_d}{dt}}}$$

(2)

The value of Q_rr representing the reverse recovery charge of the diode’s junction capacitance can be found in the SiC MOSFET datasheet. The conversion rate of the SiC MOSFET drain current can be calculated using Equation (3).

$${\displaystyle \frac{d{I}_d}{dt}}={\displaystyle \frac{g_{\mathrm{fs}}{I}_{\mathrm{g}}}{C_{\mathrm{iss}}}}$$

(3)

The input capacitance of the SiC MOSFET, denoted as C_iss, is the sum of C_gs and C_gd. The transconductance g_fs of the SiC MOSFET is calculated as follows:

$$g_{\mathrm{fs}}={\displaystyle \frac{d{I}_d/dt}{d{V}_{gs}/dt}}$$

(4)

Substituting Equations (3) and (4) into Equation (2) yields I_rr as a function of I_g:

$$I_{\mathrm{rr}}=\sqrt{{\displaystyle \frac{g_{\mathrm{fs}}{Q}_{\mathrm{rr}}{I}_{\mathrm{g}}}{C_{\mathrm{iss}}}}}$$

(5)

The current overshoot I_rr is directly proportional to the gate current I_g according to Equation (5). To reduce the current overshoot of SiC MOSFETs, it is essential to decrease the gate drive current I_g during the t₃~t₄ stage. This adjustment will enhance the overall performance and reliability of the SiC MOSFET.

Stage 4 [t₄~ t₅]: During the drain-source voltage drop stage, V_ds rapidly decreases to zero, while V_gs is maintained at V_miller. The drain current also decreases from its peak to the bus current I_L.

Stage 5 [t₅~ t₆]: The device transitions into the full conduction phase, during which V_gs surpasses V_miller and rapidly increases to V_CC. V_ds remains close to zero, with I_d equal to I_L.

The transient waveform of the SiC MOSFET turn-off is depicted in Figure 3, with all physical quantities in the waveform consistent with the turn-on phase.

Stage 6 [t₇~t₈]: In the gate drive voltage drop stage, V_gs starts to drop and continues to decrease to V_miller.

Stage 7 [t₈~t₉]: The drain-source voltage rise stage begins, with V_ds starting to increase while V_gs remains at V_miller at t₈. The input capacitor C_iss continues to discharge through R_g, and I_d remains constant.

Stage 8 [t₉~t₁₀]: During the drain-source voltage overshoot stage, I_d starts to decrease, causing a large induced voltage on the parasitic inductance of the power loop due to the rapidly decreasing I_d. This induced voltage, combined with the bus voltage, leads to the formation of the voltage overshoot phenomenon during the shutdown stage. The voltage overshoot spike V_dspeak occurs after this combination. V_gs gradually decreases from V_miller to V_th.

The voltage overshoot spike can be calculated from Equation (6):

$$V_{\mathrm{dspeak}}=U_{\mathrm{in}}-L_{\mathrm{loop}}{\displaystyle \frac{d{I}_{\mathrm{d}}}{dt}}$$

(6)

The total power loop inductance (L_oop) is the sum of the bus circuit inductance, drain inductance, and source inductance of the SiC MOSFET device. When the power loop remains constant, the total power loop inductance (L_oop) also remains constant.

The rate of change of the drain current when the device drain-source voltage reaches a spike can be calculated using Equation (7):

$${\displaystyle \frac{d{I}_d}{dt}}{|}_{V_{\mathrm{ds}}=V_{\mathrm{dspeak}}}={\displaystyle \frac{g_{\mathrm{fs}}{I}_{\mathrm{g}}}{C_{\mathrm{iss}}}}$$

(7)

From Equations (4) and (7), it is evident that the rate of change of the drain current can be reduced by lowering V_gs or decreasing Ig, thereby reducing the voltage spike generated during the device’s turn-off process.

Stage 9 [t₁₀~t₁₁]: Drain-source voltage stabilization. At t₁₀, the device transitions from the constant current region to the pinch-off region. V_ds stops increasing, exhibits oscillations, and then stabilizes. I_d continues to decrease to zero and Vgs continues to fall.

Stage 10 [t₁₁~t₁₂]: Complete device turn-off. V_gs drops to V_EE, V_ds remains constant, and I_d also remains constant.

3. Oscillation Analysis of SiC MOSFET Switching Process

Figure 4 shows the equivalent circuit for the turn-on of the SiC MOSFET, considering the device’s on-resistance R_ds(on) [23,24,25]. The parasitic diode Q₁ is in reverse cutoff and the drain-source capacitance C_ds1 of Q₁ is charged.

The gate drive circuit is a series RLC resonant circuit, and its impedance can be expressed by Equation (8) as follows:

$$Z_{\mathrm{g}}=R_{\mathrm{g}}+j{w}_{\mathrm{on}}{L}_{\mathrm{g}}+{\displaystyle \frac{1}{j{w}_{\mathrm{on}}{C}_{\mathrm{iss}}}}$$

(8)

where w_on is the resonant angular frequency. The entire turn-on equivalent circuit is also a series RLC resonant circuit, with inductive reactance equal to the capacitive reactance. The resonant angular frequency can be calculated from Equation (9):

$$w_{\mathrm{on}}=\sqrt{{\displaystyle \frac{1}{\left(L_{\mathrm{p}}+L_{\mathrm{d}}+L_{\mathrm{s}}\right)C_{\mathrm{ds}1}}}}$$

(9)

The circuit shown below features a parallel connection of two impedances at node a, as illustrated in the Equation (10) below:

$$Z_{\mathrm{a}}={\displaystyle \frac{Z_{\mathrm{g}}\times j{w}_{\mathrm{on}}{L}_{\mathrm{s}}}{Z_{\mathrm{g}}+j{w}_{\mathrm{on}}{L}_{\mathrm{s}}}}$$

(10)

The SiC MOSFET switching oscillations are underdamped and require increased damping to mitigate them. By combining Equations (8) and (10), the impedance at node a can be adjusted by varying the gate drive resistance. Higher gate resistance results in higher impedance and reduced oscillations [26].

The equivalent circuit of the SiC MOSFET during shutdown is depicted on the left side of Figure 5. Here, Q₂ is disconnected and C_ds2 is charging. The parasitic diode of Q₁ is conducting forward, bypassing C_ds1 of Q₁. On the right side of Figure 5, the parasitic capacitor of Q₂, originally in a triangular configuration, is converted to a star configuration.

The impedance of the gate drive circuit at this point is represented by Equation (11):

$$Z_{\mathrm{g}}=R_{\mathrm{g}}+j{w}_{\mathrm{on}}{L}_{\mathrm{g}}+{\displaystyle \frac{1}{j{w}_{\mathrm{on}}{C}_{\mathrm{G}}}}$$

(11)

w_on can be calculated by Equation (12):

$$w_{\mathrm{on}}=\sqrt{{\displaystyle \frac{1}{\left(L_{\mathrm{p}}+L_{\mathrm{d}}+L_{\mathrm{s}}\right)\left(C_{\mathrm{D}}+C_{\mathrm{S}}\right)}}}$$

(12)

The impedance of the source branch is as follows:

$$Z_{\mathrm{s}}=j{w}_{\mathrm{on}}{L}_{\mathrm{s}}+{\displaystyle \frac{1}{j{w}_{\mathrm{on}}{C}_{\mathrm{S}}}}$$

(13)

The circuit impedance below node a is the parallel connection of two impedances; see Equation (14) below:

$$Z_{\mathrm{a}}={\displaystyle \frac{Z_{\mathrm{g}}\times Z_{\mathrm{s}}}{Z_{\mathrm{g}}+Z_{\mathrm{s}}}}$$

(14)

By combining Equation (11) with Equation (14), it is evident that reducing oscillation requires increasing the impedance below node a to stabilize the system. Since the parasitic inductance and parasitic capacitance of the SiC MOSFET are constants, the impedance below node a can only be modified by adjusting the gate drive resistance. A higher gate resistance results in higher impedance and, consequently, lower oscillation.

4. Active Gate Driver Circuit Analysis

Based on the above analysis, it is essential to reduce the gate drive current during the t₃–t₄ and t₉–t₁₀ stages to lower the di/dt, thereby minimizing turn-on transient current overshoot and turn-off transient voltage overshoot [27,28,29]. By examining the oscillation in the switching process of SiC MOSFETs, it is evident that increasing the gate drive resistance can effectively reduce drain current and drain-source voltage oscillation during the switching process.

Figure 6 illustrates the current overshoot suppression circuit. Before Q₂ conducts, the gate current is denoted as i_g. The gate drive resistor is formed by connecting R₁ and R_gon in parallel. The detection circuit utilizes the voltage V_Ls generated by the source inductor to monitor the conduction state of Q₂. The ground of the AGD circuit is defined as SGND. Using this reference point, the source inductor senses the voltage V_Ls, which can be determined by Equation (15). When V_Ls reaches a certain value, the instant of Q₂ conduction can be identified [30]. Upon detecting Q₂ conduction, if the difference between the base voltage V_ref of transistor Q₃ and the source inductor voltage V_Ls exceeds 0.7 V, the transistor begins to conduct, initiating the shunt circuit. The gate current i_g is then divided into two parts, one of which is i_go; thus, the actual gate current is i_g1 = i_g − i_go, reducing the gate drive current. Meanwhile, the operational amplifier AMP functions as a comparator when Q₂ is on. If the source inductor voltage V_Ls exceeds the reference voltage V_ref2, the operational amplifier AMP outputs a low level to turn off Q_on. At this point, the gate drive resistance is only R_gon, thereby increasing the gate resistance. Consequently, the reduction in gate current and increase in gate resistance are achieved, mitigating turn-on current overshoots and oscillations. The V_ref1 settings can be adjusted according to the working conditions. When V_Ls is smaller, it can be set to a higher value. To simplify the circuit, this paper sets V_ref1 to 0 V. To prevent false triggering of the comparator due to circuit noise, V_ref2 cannot be set to 0 V. Therefore, this paper sets V_ref2 to 1.2 V.

$$V_{L_{\mathrm{s}}}=-L_{\mathrm{s}}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{d}}}{dt}}$$

(15)

The transistor Q₃ begins to conduct when V_ref − V_Ls exceeds 0.7 V. The current i_go is diverted from the gate main circuit and can be calculated using Equation (16). At this point, the actual gate drive current i_g1 is determined by Equation (17):

$$i_{\mathrm{go}}={\displaystyle \frac{V_{\mathrm{ref}1}-V_{BE}-V_{L_s}}{R_2}}$$

(16)

$$i_{\mathrm{g}1}=i_{\mathrm{g}}-i_{\mathrm{go}}$$

(17)

The collector-emitter voltage drop of the transistor denoted as V_BE, is generally 0.7 V. From Equation (17), it is evident that the shunt current i_go increases when V_ref − V_Ls is larger, resulting in a decrease in the actual gate drive current i_g1. Equation (5) indicates that the turn-on current overshoot can be mitigated by reducing the gate drive current. A lower rate of change in the drain current of the SiC MOSFET leads to a lower current overshoot during turn-on.

As illustrated in Figure 7, the voltage overshoot suppression circuit is shown. Prior to disconnecting Q₂, the gate current is represented as i_g. The gate drive resistor consists of R₂ and R_goff in parallel. The detection circuit monitors the rate of change of the Q₂ drain-source voltage, and the transistor Q₄ begins to conduct when the Q₂ drain-source voltage changes significantly. At this time, V_ref3 injects current i_gin into the gate drive circuit. If the positive drive current is considered as the positive direction, the gate current is actually |i_g|−|i_gin|, thus reducing the gate drive current. Conversely, when V_f exceeds the reference voltage V_ref4, the comparator COM outputs a low level to turn off Q_off. At this time, the gate drive resistance is only R_goff, thereby increasing the gate resistance. In this way, the gate current decreases and the gate resistance increases, achieving the purpose of reducing the turn-off voltage overshoot and oscillation. V_ref3 can be set to a larger value as the injection voltage source; for simplicity, this paper sets V_ref3 to +5 V. The V_ref4 setting is determined according to the working conditions; considering the high value of V_f, it is set to 5 V in this paper.

The detection circuit samples the drain voltage using an RC differential circuit. V_f represents the sampled voltage, R_f is the sampling resistor, and C_f is the sampling capacitance [31]. As shown in Equation (18), V_f characterizes the rate of change of the drain voltage:

$$V_{\mathrm{f}}=R_5{C}_{\mathrm{f}}{\displaystyle \frac{d{V}_{\mathrm{ds}}}{dt}}$$

(18)

The current direction at the turn-on moment is defined as positive. To reduce the gate drive current at the turn-off moment, it is necessary to inject current. At this point, the gate drive current can be calculated using Equation (19):

$$i_{\mathrm{g}2}=i_{\mathrm{g}}+i_{\mathrm{gin}}$$

(19)

The injected current magnitude can be determined from the circuit diagram using Equation (20). By decreasing the values of R₄ and R₃, the injection current can be increased, which in turn increases the reverse gate drive current and reduces the drain-source voltage overshoot.

$$i_{\mathrm{gin}}={\displaystyle \frac{V_{\mathrm{ref}3}}{R_4}}+{\displaystyle \frac{V_{\mathrm{f}}}{R_3}}$$

(20)

5. Experimental Analysis

Based on the working principle and design results detailed in Section 4, we conducted PSpice double pulse simulation experiments. We utilized a silicon carbide device provided by Wolfspeed (model C3M0015065K). The hardware platform depicted in Figure 8 was assembled to validate the proposed circuits experimentally. Experiments were performed using an STM32F103C8T6 core control board to generate double pulses. The current probe model used was ETA5520A, and the high-voltage active differential probe was ETA5010. The oscilloscope model employed was DS2102E.

5.1. Experiments With Different Gate Resistors

The simulated test waveforms shown in Figure 9 illustrate the impact of different gate resistances on the turn-on current. When comparing the turn-on current waveforms of SiC MOSFETs with gate driving resistances of 10 Ω, 20 Ω, 30 Ω, 40 Ω, and 50 Ω, it is evident that larger gate resistances extend the time required for the MOSFET to transition from the cutoff state to the saturated conduction state. This results in a slower rise of I_d, reduced I_d overshoot, and minimized oscillations. The turn-on time increases with higher gate drive resistance because a larger resistance limits the gate drive current, leading to an increase in the gate capacitor’s charging and discharging times. This delay impacts both the turn-on and turn-off processes of the SiC MOSFET.

Figure 10 illustrates the simulated waveforms depicting the impact of various gate resistors on the turn-off voltage of SiC MOSFETs. We compared the turn-off voltage waveforms for gate drive resistances of 10 Ω, 20 Ω, 30 Ω, 40 Ω, and 50 Ω. An increase in drive resistance extends the discharge time required for the gate voltage to transition from the on state to the off state, resulting in a longer turn-off delay time for the MOSFET. Higher gate drive resistance decelerates the discharge of the gate charge, prolonging the entire turn-off process and increasing turn-off losses. A larger gate resistor helps to reduce di/dt, effectively minimizing V_ds overshoots and oscillations. However, the reverse recovery time of the body diode may increase due to the slower turn-off speed, raising the risk of V_ds overshoot caused by parasitic inductance.

5.2. Comparison of the Effects of AGD and CGD Circuits under Various Operational Conditions

Figure 11 presents the comparison of AGD and CGD effects under four different load currents (20 A, 40 A, 60 A, 80 A). The current overshoot is reduced by 44.73% at 20 A, as shown in Figure 11a; 52.38% at 40 A, as shown in Figure 11b; 56.52% at 60 A, as shown in Figure 11c; and 58.33% at 80 A, as shown in Figure 11d. It is evident that the higher the load current, the higher the parasitic inductor voltage at the source of the SiC MOSFET. Consequently, the current overshoot suppression circuit draws more current from the gate, significantly reducing the turn-on current overshoot.

As shown in Figure 12, a comparison of the effects of AGD and CGD at four different bus voltages is recorded for 100 V, 200 V, 300 V, and 400 V. The voltage overshoot is reduced by 37.50% at a bus voltage of 100 V, as shown in Figure 12a. At 200 V, the voltage overshoot is reduced by 38.46%, as shown in Figure 12b. At 300 V, the voltage overshoot is reduced by 39.13%, as shown in Figure 12c. At 400 V, the voltage overshoot is reduced by 40.74%, as shown in Figure 12d. The higher the bus voltage, the greater the drain-source voltage change rate of the SiC MOSFET. Consequently, more current is injected into the gate by the voltage overshoot suppression circuit, leading to a greater reduction in the turn-off voltage overshoot.

5.3. Comparison of AGD Circuit and CGD Circuit Effects

The hardware experimental conditions for the AGD and CGD drain current experiments were set with a bus voltage of 50 V and a load inductance of 500 µH. The driver resistor used for the experiment was 15 Ω. As shown in Figure 13, the experimental comparison of AGD and CGD drain currents indicates that the drain current overshoot is 2.5 A for CGD and 1 A for AGD. AGD reduces the drain current overshoot by 60% compared to CGD, and significantly diminishes the magnitude and duration of drain current waveform oscillations.

Figure 14 presents an experimental comparison of AGD and CGD drain-source voltages. The drain-source voltage overshoot is 180 V with CGD and 160 V with AGD. AGD lowers the drain-source voltage overshoot by 15.38% compared to CGD and considerably reduces the magnitude and duration of the drain-source voltage waveform oscillations. These results demonstrate that the proposed AGD circuit effectively suppresses the turn-on current, turn-off voltage overshoot, and oscillations of SiC MOSFETs.

Table 1. Comparison of overshoot and loss of SiC MOSFETs with AGD and CGD.

Stage	Programmatic	Overshoot	Switching Loss
Opening stage	CGD	15 A	1.859 mJ
	AGD	13.5 A	1.448 mJ
Closing stage	CGD	180 V	1.969 mJ
	AGD	160 V	1.366 mJ

compares the overshoot and loss characteristics of SiC MOSFETs for both AGD and CGD circuits. It is evident from the table that the AGD circuit significantly reduces turn-on current overshoot and turn-off voltage overshoot. Additionally, the turn-on and turn-off losses of the AGD circuit are reduced by an average of 24%.

In practical applications of SiC MOSFETs, high di/dt and high dv/dt are key factors causing EMI problems. To analyze the EMI of SiC MOSFETs using the AGD circuit, the drain current (I_d) and drain-source voltage (Vdc) of the AGD and CGD circuits were analyzed using fast Fourier transforms (FFTs), as shown in Figure 15. The AGD circuit proposed in this paper was observed to not have a negative impact on EMI compared to CGD. In the spectrogram of the drain current circuit in Figure 15a, the AGD driver circuit does not cause EMI problems in the 0.1–6 MHz band relative to the CGD driver circuit. It even improves the EMI issue in the 0.5–2 MHz band. In the drain-source voltage spectrum in Figure 15b, the AGD driver circuit improves the EMI problem in the 0.1–10 MHz band compared to the CGD driver circuit.

In summary, the AGD circuit proposed in this paper enhances switching speed while significantly reducing current and voltage overshoot, as well as losses. Additionally, this AGD circuit does not negatively impact EMI and even improves EMI issues in certain frequency bands.

5.4. Comparison of AGD Circuit and RCD Snubber Circuit Effects

The schematic diagram of the RCD snubber circuit is shown in Figure 16. When the SiC MOSFET is on, the current in the circuit mainly flows through the main circuit, and the RCD snubber does not work at this time. At the instant the SiC MOSFET turns off, the current in the circuit charges the capacitor C_SNB through the diode D_SNB of the RCD snubber circuit. Since the voltage across C_SNB cannot change abruptly, the rate of rise of the switching voltage of the switching tube is reduced. This reduces the turn-off voltage overshoot and transfers the turn-off power loss from the switching tube to the R_SNB.

Figure 17 presents a comparison of the waveforms of the three circuits at a bus voltage of 200 V. The overshoot of the CGD circuit is 14.5%, the RCD snubber circuit is 10.75%, and the AGD circuit is 7%. Regarding oscillations, both the AGD circuit and the RCD snubber circuit effectively reduce voltage oscillations. However, the AGD circuit is more effective with an oscillation time of only 14 ns.

Figure 18 shows a comparison of the waveforms of the three circuits at a load current of 40 A. The peak current of the CGD circuit is 61 A, the RCD snubber circuit is 60 A, and the AGD circuit is 48 A. It is evident that the RCD snubber circuit does not significantly reduce the turn-on current spike of the SiC MOSFET. In terms of oscillation, the AGD circuit demonstrates the most significant reduction.

Therefore, the AGD circuit outperforms the RCD snubber circuit in reducing the turn-on current, the turn-off voltage overshoot, and oscillations of the SiC MOSFET.

6. Conclusions

This paper began with a detailed stage-by-stage analysis of the switching transient process of SiC MOSFETs. The fundamental causes of turn-on transient current overshoot and turn-off voltage overshoot were examined, along with a thorough analysis of the oscillation phenomena that accompany the switching action. Based on these findings, a triode with a dynamic switching strategy was designed as an active driver circuit. This circuit separates and injects control current into the gate during the current and voltage spike phases of the SiC MOSFET, complemented by a targeted drive resistor configuration. This effectively reduces peak turn-on transient current and suppresses turn-off voltage overshoot, simultaneously minimizing switching oscillations.

Compared to the CGD circuit and RCD snubber circuit, this design performs better in suppressing overshoot and oscillation. Among most active drive technologies, the primary advantage of this solution lies in its clean and simple structural design and ease of implementation. It demonstrates good adaptability and excellent suppression performance under various operating conditions, showcasing a high degree of versatility. Future research will focus on further improving overall performance, particularly in areas such as precise detection of hardware parameters and optimization of key parameter combinations.