An Adaptive High-Efficiency LED Backlight Driver

Abstract

An adaptive high-efficiency light-emitting Diode (LED) backlight driver scheme has been proposed to address the issue of additional power loss caused by LED forward voltage variation. In this scheme, the peak current and the duty cycle of each LED channel are adjusted separately through an adaptive control algorithm to minimize the voltage drop on the linear current regulator (LCR) of each LED channel to reduce the excessive power loss in each LED channel and enhance the total power efficiency. A linear current regulator, suitable for adaptive control, is designed on a 0.18 μm 5V complementary metal-oxide-semiconductor (CMOS) process. Simulation results demonstrate that the linear current regulator can achieve a linearly adjustable channel current ranging from 0 to 48 mA with a current resolution of 0.2 mA. Across different process corners and temperatures, the maximum error for the full current range is less than 0.1%. The core area of chip layout is about 0.1 mm². The complete driver prototype comprises the LCR chips, external power MOS transistors, digital module, and LED chains. The test results show that the power loss of the linear current regulator has been significantly reduced, and the power efficiency of each LED channel has been measured at around 98.1%.

1. Introduction

Light-emitting diodes (LEDs) have been widely adopted as backlight sources for liquid crystal display (LCD) devices and other applications. Compared to traditional light sources, LEDs offer significant advantages such as high efficiency, excellent color stability, high reliability, long lifespan, compact size, and environmental safety [1,2,3,4]. Since the brightness of LED is proportional to its current, an efficient and accurate driver circuit is essential in LED backlight applications to achieve precise brightness control. Additionally, parallel LED channels (LED chains) are always employed to ensure sufficient coverage [5,6]. A traditional LED backlight driver is primarily composed of a boost converter, parallel LED channels, and corresponding linear current regulators (LCRs). The boost converter provides sufficient voltage to turn on all LEDs in each channel, and the LCR regulates the current for each channel to control brightness [7,8,9]. As an important area of power management application, the design of LED backlight drivers has always been a popular research focus for numerous universities and research institutions worldwide. The objective is to optimize system performance through innovative circuit designs and system architectures, with an emphasis on metrics such as system efficiency [10,11,12,13,14,15], dimming ratio [16,17,18,19,20], and current accuracy [21,22,23,24,25].

Due to process variations, aging effects, and temperature changes, LEDs of the same type can exhibit different forward voltage, resulting in significant voltage discrepancies across different LED channels. Consequently, it is necessary to introduce a certain amount of voltage headroom to ensure correct functionality under various working conditions. However, this also leads to increased power loss and deteriorated power efficiency [26,27]. A digital control mechanism based on an R-DAC was proposed in [28] to address the problem of increased power loss due to excessive voltage. A comparison between the voltage on the LCR and a pre-set reference voltage is conducted, which drives the adjustment of the feedback voltage of the DC–DC boost converter via a digital-to-analog converter (DAC). The boost converter’s output is then adjusted to maintain the LCR voltage at a fixed level. In [29], an adaptive reference tracking technique was proposed, using a “Minimum Voltage” circuit and a 3-bit adjustable resistor as a feedback resistor to adjust the output of the boost converter. The accuracy of the output voltage is influenced by the precision and adjustment range of the resistor. In [30,31,32,33,34], through “Minimum Voltage Selector” or “Lowest channel selector”, the minimum LCR voltage among channels is detected and used to dynamically adjust the duty cycle of the boost converter’s switch signal and change the boost converter’s output. In [35,36], diodes are used to select the minimum LCR voltage, a method that is not easily implemented in standard CMOS processes. In [2], the advantages and disadvantages of various LED driver topologies were analyzed, and future research directions were identified.

In general, for most existing solutions, the main strategy is to adjust the boost converter’s output voltage to reduce the excessive voltage on the LCR, thereby reducing losses and improving efficiency. However, for multi-channel configuration, due to the inter-channel differences, it is more effective to optimize each channel separately to further reduce loss and enhance efficiency. In this paper, we propose an adaptive high-efficiency LED backlight driving scheme that addresses the issue of inter-channel differences. Both linear current regulation and pulse width modulation (PWM) are employed for each channel. Through linear current regulation, the channel current is adjusted, and the voltage on the LCR in each channel is minimized to a predefined fixed value. Subsequently, through pulse width modulation, the duty cycle of channel current is adjusted, calibrating the average current of each channel to the same level. This strategy ensures that each LED channel operates with minimal loss, thereby maximizing efficiency.

The structure of the remaining parts of this article is as follows: Section 2 elaborates on the adaptive control technology designed in this paper. Section 3 discusses and analyzes the simulation results and test results of the proposed adaptive high-efficiency LED backlight driver. Section 4 concludes the paper.

2. Adaptive Control Technique

2.1. Principle of Adaptive Control

Figure 1 illustrates the structure of the proposed adaptive high-efficiency LED backlight driver, which comprises a brightness controller, a boost converter, and several LED channels. Each LED channel consists of an LED chain, an LCR, and a high-voltage MOS transistor acting as a switch for duty cycle control. The brightness controller includes a 9-bit R-DAC to produce V_C, which serves as a voltage reference and determines the output of the boost converter V_boost. The SENSE signal indicates whether the LCR is on the right status. The brightness controller monitors SENSE of each channel and generates V_C, PWM, and CM_SW signals following a specific algorithm and steps. CM_SW and PWM are multi-bit digital signals that control the peak current and the duty cycle of the channel, respectively. This process ensures that each LED channel operates at a high-efficiency state.

From the figure, for channel n, there exists a voltage relationship as

$${\mathrm{V}}_{\mathrm{b}\mathrm{o}\mathrm{o}\mathrm{s}\mathrm{t}}={\mathrm{V}}_{\mathrm{L}\mathrm{E}\mathrm{D},\mathrm{n}}+{\mathrm{V}}_{\mathrm{M}\mathrm{P},\mathrm{n}}+{\mathrm{V}}_{\mathrm{L}\mathrm{C}\mathrm{R},\mathrm{n}}$$

(1)

where V_LED is the voltage across the LED chain or the summation of the forward voltage of each LED. V_MP is the source-drain voltage of the high-voltage MOS transistor MP, and V_LCR denotes the LCR voltage. The “n” in subscript indicates channel n, which applies to all symbols in this paper. If the adaptive control is disabled and the LED channel is not in the optimal state, there will be an excessive portion in the LCR voltage, which can be expressed as follows:

$${\mathrm{V}}_{\mathrm{LCR},\mathrm{n}}={\mathrm{V}}_{\mathrm{LCR}\_\min }+{\mathrm{V}}_{\mathrm{LCR}\_\mathrm{exc},\mathrm{n}}$$

(2)

where V_{LCR_min} is the minimum required LCR voltage to ensure proper operation, that is to say, the output transistor in the LCR works properly and maintains accurate output current. V_{LCR_exc} represents the excessive portion of the LCR voltage. For one channel, the power loss can be calculated by

$${\mathrm{P}}_{\mathrm{loss},\mathrm{n}}={\mathrm{I}}_{\mathrm{ave},\mathrm{n}}\times {\mathrm{V}}_{\mathrm{loss},\mathrm{n}}={\mathrm{I}}_{\mathrm{ave},\mathrm{n}}\times \left({\mathrm{V}}_{\mathrm{LCR},\mathrm{n}}+{\mathrm{V}}_{\mathrm{MP},\mathrm{n}}\right)$$

(3)

where I_ave,n is the average current, which is determined by the peak current I_peak,n and the current duty cycle δ_n. V_loss,n is the summation of V_LCR,n and V_MP,n. If the on-resistances of the high-voltage MOS transistors are low enough, V_MP has limited impact on P_loss. Because V_MP and V_{LCR_min} are prerequisite to maintain the MOS and LCR operate appropriately, the excessive power loss is defined as

$${\mathrm{P}}_{\mathrm{loss}\_\mathrm{exc},\mathrm{n}}={\mathrm{I}}_{\mathrm{ave},\mathrm{n}}\times {\mathrm{V}}_{\mathrm{LCR}\_\mathrm{exc},\mathrm{n}}$$

(4)

2.2. Adaptive Control Process

An adaptive control process suitable for multi-channel LED drivers is designed to reduce excessive power loss caused by the excessive voltage. At system startup, the brightness controller initiates an initialization process, during which the peak current and duty cycle of each LED channel are individually set to achieve uniform brightness and simultaneously minimize excessive power loss. After the initialization phase, the brightness controller transitions into the tracking phase, where it continuously monitors the status of the LCR. The peak current and duty cycle settings are then adjusted accordingly to accommodate fluctuations in power supply, temperature, and other factors.

Figure 2 shows the flowchart of the initialization phase. Firstly, the brightness input data, including the nominal peak current I_set and the duty cycle δ_set, are loaded into the brightness controller. Subsequently, the LCR current of each channel is set to I_set via the CM_SW signal. The brightness controller then begins to increase V_C, causing V_boost to decrease accordingly. Meanwhile, the brightness controller simultaneously monitors the status signal SENSE from each channel. Once all SENSE signals change from 0 to 1, the increase in V_C stops. At this point, the peak currents of all channels have reached the preset value of I_set, and there is always one channel, assumed to be channel k, whose SENSE signal is the last to change.

Next, a peak current adjustment step is carried out sequentially on all channels except channel k. The brightness controller attempts to increase the channel current by providing a new CM_SW setting. If SENSE remains at 1, the brightness controller continues this process. However, if SENSE changes from 1 to 0, the brightness controller reverts to the previous CM_SW setting, concluding the adjustment process for that channel. The corresponding channel then has a new peak current. The brightness controller proceeds to conduct the adjustment process for the subsequent channel. Once all current adjustments are completed, the voltage on each LCR approaches V_{LCR_min}, and the excess component has been minimized.

Finally, in order to ensure the same brightness, each LED channel needs to have the same average current. Therefore, the duty cycle of channel n (δ_n) is adjusted by the brightness controller as follows:

$${\mathsf{\delta }}_{\mathrm{n}}={\mathsf{\delta }}_{\mathrm{s}\mathrm{e}\mathrm{t}}\times {\displaystyle \frac{{\mathrm{I}}_{\mathrm{s}\mathrm{e}\mathrm{t}}}{{\mathrm{I}}_{\mathrm{peak},\mathrm{n}}}}$$

(5)

where I_peak,n is the peak current of n-th LED channel after adjustment process as described above. δ_set and I_set represent the initial duty cycle and peak current, respectively. It is worth noting that, according to Equation (4), the average current remains unchanged.

Through the aforementioned process, the peak current I_peak,n and duty cycle δ_n for each LED channel are adjusted, thereby minimizing additional power consumption resulting from excessive voltage. The adjusted average current closely aligns with the initially set average current. Given that the brightness output of LEDs correlates directly with their current, the adaptive control method ensures that the brightness levels across all LED channels remain consistent. Upon entering the tracking phase, the main principle resembles that of the initialization phase. Both of them combine the adjustment of peak current and duty cycle and will not be described in detail in this article.

2.3. Linear Current Regulator

Because LED brightness is directly influenced by its current, precise brightness control necessitates accurate current regulation. In many LED backlight driver solutions, an LCR is typically employed for generating and controlling the LED current. Figure 3 illustrates two typical LCR circuit configurations [37]. A key design objective for LCR circuits is achieving high current accuracy. In Figure 3a, the operational amplifier and the transistor M1 form a negative feedback, ensuring that V_S equals to V_REF. Consequently, the output current I_LED is V_REF/R_S. Clearly, the accuracy of R_S directly affects I_LED’s precision. It is important to note that the driving currents for backlight LEDs are generally substantial. In this paper, the maximum driving current is designed to be 48 mA. Additionally, to minimize power loss, V_S or V_REF should be kept as low as possible, necessitating a small R_S to achieve high currents. However, excessively small R_S can significantly enhance the negative impact of circuit parasitics on output current accuracy.

Figure 3b depicts another type of LCR. In this configuration, the output current I_LED is not directly generated as in Figure 3a, but through current mirroring. In this structure, I_LED is determined by B × I_REF, where I_REF is a reference current and B is the current mirror ratio, which is defined by the size ratio of transistor M1 to M0. The operational amplifier (OP) plays a crucial role by ensuring that transistors M1 and M0 have the same V_DS, thereby guaranteeing accurate current mirroring.

Actually, M0 and M1 can work in the linear region instead of the saturation region by lowing V_B, thereby reducing V_DS, which helps to lower V_LCR and reduce excessive power [38]. The classic drain current expression for MOS transistors working in the linear region is

$${\mathrm{I}}_{\mathrm{D}}={\displaystyle \frac{1}{2}}\mathsf{\mu }{\mathrm{C}}_{\mathrm{OX}}({\displaystyle \frac{\mathrm{W}}{\mathrm{L}}})[2({\mathrm{V}}_{\mathrm{GS}}-{\mathrm{V}}_{\mathrm{TH}})-{\mathrm{V}}_{\mathrm{DS}}]{\mathrm{V}}_{\mathrm{DS}}$$

(6)

The transistor can now be approximately equivalent to a linear resistor. As mentioned above, due to the effect of OP, the V_DS of M0 and M1 are kept at the same. Then the drain current of M0 and M1 has a relationship as

$${\displaystyle \frac{{\mathrm{I}}_{\mathrm{D},\mathrm{M}0}}{{\mathrm{I}}_{\mathrm{D},\mathrm{M}1}}}={\displaystyle \frac{{(\mathrm{W}/\mathrm{L})}_{\mathrm{M}0}}{{(\mathrm{W}/\mathrm{L})}_{\mathrm{M}1}}}={\displaystyle \frac{1}{\mathrm{B}}}$$

(7)

Clearly, accurate current mirroring is guaranteed.

Based on the circuit structure shown in Figure 3b, an improved LCR for adaptive control was designed as depicted in Figure 4. The main difference from the circuit in Figure 3b is the introduction of operational amplifier OP2. OP2, in conjunction with transistor M0, forms a negative feedback loop ensuring that the source-drain voltage V_DS of M0, denoted as V_A in the figure, remains equal to V_REF. By adjusting V_REF, the source-drain voltage V_DS of M0 can be precisely controlled. The advantage of the design is that it mitigates the impact of process variations and facilitates accurate parameter control. When V_REF is low, transistor M0 operates in the linear region. Transistors M1, M2, …, MN serve as current mirror transistors corresponding to M0, each having the same size. The decoder determines whether each mirror transistor is activated or deactivated based on the binary control word CM_SW, thereby adjusting the total output current. When a mirror transistor’s gate is connected to V_COM, it turns on; when connected to ground, it turns off. OP1 functions similarly to OP in Figure 3b, ensuring that the voltage at node D (denoted as V_D) matches V_A, thereby maintaining accurate current mirroring. The comparator COMP works as a simple circuit state detector with V_COM set to 2.5 V in this design. OP1 is a high-gain operational amplifier with a gain-boosting output structure [39], while OP2 is an operational amplifier with a rail-to-tail class-AB output stage [40].

When V_boost is sufficiently high, even after accounting for the voltage drop across the LED chain, there remains enough V_LCR to ensure the proper operation of the LCR, allowing I_LED to reach or maintain its set value. At this condition, the gate voltage of the transistor MR is approximately 1.86 V (V_GS,MR + V_REF) according to the simulation results at the typical process corner, and SENSE stays at 1. If V_boost decreases or if I_LED increases and makes the forward voltage of the LED chain increase, V_LCR will correspondingly decrease. However, as long as transistor MR remains effective, the LCR can continue to function normally. If V_LCR decreases further and pushes transistor MR into deep linear region, V_G must be increased to counteract the impacts of the decreasing V_LCR. When V_G exceeds V_COM, the output of the comparator changes state, and SENSE switches to 0. This indicates that the LCR may no longer be able to maintain or achieve the set I_LED.

All mirror transistors have the same size, and each transistor has a size ratio of B:1 with M0. The LED current can be determined by the following equation:

$${\mathrm{I}}_{\mathrm{LED}}=\mathrm{N}\times \mathrm{B}\times {\mathrm{I}}_{\mathrm{REF}}$$

(8)

where N is the number of activated mirror transistors and determined by CM_SW. I_REF is the reference current generated by the external bias circuit. It should be noted that the output current I_LED of the LCR actually forms the aforementioned peak current I_peak.

Even on the same chip, there is a certain degree of process variation, which primarily affects the device size and characteristic parameters, leading to inaccuracies or mismatches in the current mirroring. Considering the influence of the width-to-length ratio (W/L) and the threshold voltage (V_th), the current change caused by process variation can be expressed as follows:

$$\Delta \mathrm{I}={\displaystyle \frac{\partial \mathrm{I}}{\partial (\mathrm{W}/\mathrm{L})}}\Delta (\mathrm{W}/\mathrm{L})+{\displaystyle \frac{\partial \mathrm{I}}{\partial {\mathrm{V}}_{\mathrm{t}\mathrm{h}}}}\Delta {\mathrm{V}}_{\mathrm{t}\mathrm{h}}$$

(9)

The current mismatch is usually defined as the rate of change of current. Assuming no correlation between different influencing factors, it can be expressed as:

$$\left|{\displaystyle \frac{\Delta \mathrm{I}}{\mathrm{I}}}\right|={\displaystyle \frac{1}{\mathrm{I}}}\left(\left|{\displaystyle \frac{\partial \mathrm{I}}{\partial (\mathrm{W}/\mathrm{L})}}\Delta (\mathrm{W}/\mathrm{L})\right|+\left|{\displaystyle \frac{\partial \mathrm{I}}{\partial {\mathrm{V}}_{\mathrm{t}\mathrm{h}}}}\Delta {\mathrm{V}}_{\mathrm{t}\mathrm{h}}\right|\right)$$

(10)

If the transistor operates in the saturation region, according to the corresponding drain current formula, the current mismatch is

$$\left|{\displaystyle \frac{\Delta \mathrm{I}}{\mathrm{I}}}\right|=\left|{\displaystyle \frac{\Delta (\mathrm{W}/\mathrm{L})}{(\mathrm{W}/\mathrm{L})}}\right|+\left|{\displaystyle \frac{2\Delta {\mathrm{V}}_{\mathrm{t}\mathrm{h}}}{({\mathrm{V}}_{\mathrm{GS}}-{\mathrm{V}}_{\mathrm{t}\mathrm{h}})}}\right|$$

(11)

While if the transistor operates in the linear region, according to the corresponding drain current formula, the current mismatch becomes

$$\left|{\displaystyle \frac{\Delta \mathrm{I}}{\mathrm{I}}}\right|=\left|{\displaystyle \frac{\Delta (\mathrm{W}/\mathrm{L})}{(\mathrm{W}/\mathrm{L})}}\right|+\left|{\displaystyle \frac{2\Delta {\mathrm{V}}_{\mathrm{t}\mathrm{h}}}{2({\mathrm{V}}_{\mathrm{GS}}-{\mathrm{V}}_{\mathrm{t}\mathrm{h}})-{\mathrm{V}}_{\mathrm{DS}}}}\right|$$

(12)

Comparing the two formulas above, it can be seen that the impact of size variation on current mismatch is the same in both the linear and the saturation regions. However, the impact of threshold voltage variation is smaller in the linear region, indicating that it is possible to achieve lower current mismatch in the linear region.

3. Simulation and Measurement Results

3.1. System and Chip Design

Based on Figure 2, this paper constructs and validates a three-channel adaptive LED driver, with each channel comprising 6 LEDs. A boost converter chip, specifically the TPS61046 from Texas Instruments, is used. The LCR is designed using a 0.18 μm complementary metal-oxide-semiconductor (CMOS) 5 V process. Since this process does not support high-voltage devices, external MP transistors are employed. Ideally, if a BCD process is available, these MP transistors could be integrated directly onto the chip. Additionally, further integration of the brightness controller is envisioned for achieving a monolithic integrated driver chip, which is a planned future work. In circuit simulation, PSPICE models are employed for the boost converter, LEDs, and MP transistors. The on-voltage parameter in the PSPICE model for LED is intentionally adjusted to introduce differences between channels. Specifically, for channel 3, the LED on-voltage is set to 3.20 V, representing a typical value. For channels 1 and 2, the parameters are adjusted to 2.73 V and 2.76 V, respectively. As described earlier, the minimum value of V_boost is dictated by the V_LED of channel 3. The brightness controller is implemented using Verilog HDL and runs at the frequency of 100 MHz. The frequency of the PWM signal is 10 KHz. The entire circuit runs in a mixed-signal simulation mode to verify the adaptive control process and assess the performance of the LCR.

In consideration of current control range and resolution, the size of M0 in the LCR is chosen to be 1 μm/1 μm, and its ratio to the mirror transistor is set to be 1:4. There are 240 current mirror transistors in total. The reference current I_REF is set to be 50 μA, resulting in a unit output current of 200 μA and a maximum output current of 48 mA. The size of MR is chosen to be 40 μm/2 μm × 50. The overall layout of the LCR circuit is shown in Figure 5. All mirror transistors and their corresponding control switches are arranged in the form of a 15 × 16 array. The core area is only 325 μm × 310 μm, while the entire area, including pads, is 700 μm × 720 μm. The key transistor sizes are also summarized in Figure 5.

3.2. Simulation Results

Figure 6 depicts the simulated output characteristics of the LCR under different process corners and temperatures. It can be seen that when the output current LCR ranges from 0 mA to 48 mA, it demonstrates good linearity under different operating conditions. Specifically, at an output current setting of 20 mA, the maximum current deviation is 13 μA, resulting in a current error of less than 0.1%. Overall, the LCR exhibits good current linearity and accuracy within the specified current range.

Figure 7 depicts the voltage waveform at several essential nodes during the adaptive process. SENSE₁, SENSE₂ and SENSE₃ represent the SENSE signals of the corresponding channels. T₀ denotes the soft start phase of the boost converter. Upon power-on, the output of the boost converter V_boost gradually reaches a preset value after a period of time. This preset value is the minimum voltage for the circuit to operate properly under various working conditions and is set to 25.19 V in this design. As V_boost increases, the SENSE signals of each channel sequentially transition to 0. T₁ marks the V_boost adjustment phase. During this time, the brightness controller gradually increases V_C, leading to a corresponding decrease in V_boost. It can be seen that when V_boost reaches 21.52 V, SENSE₃ transitions to 1, indicating a change in the status of channel 3. Finally, V_C stays at 0.33 V, and V_boost is stabilized at 21.62 V. T₂ marks the current regulation phase, during which the current of channel 1 (channel 2) increases. When SENSE₁ (SENSE₂) transitions to 1, it indicates that the status of channel 1 (channel 2) has changed. The current regulation of channel 1 (channel 2) is ceased, and the duty cycle of channel 1 (channel 2) is set according to Equation (4). T₃ represents the normal working phase, which is also called the continuous tracking phase, and SENSE signals are dynamically kept at 0.

Figure 8 illustrates the current waveform in each channel. Initially, the peak current value of each channel is set to 20 mA, with a default duty cycle of 100%. During the early stage of T₀, V_boost has not been fully established, and all LEDs are in the off state, resulting in zero current in each channel. Because the LEDs in channel 3 have the largest forward voltage, the current in channel 3 is the last rising to the set value, consistent with the timing of SENSE signals in Figure 7. Following the completion of the V_boost adjustment phase, the current regulation phase starts. It can be seen that the peak currents in channel 1 and channel 2 are increased to 24.2 mA and 23.2 mA, respectively, with the corresponding duty cycles adjusted to 82.6% and 86.2%, ensuring uniform average currents across the three channels. When the normal working phase begins, the brightness controller will continuously monitor the state of the LCR. If the state changes, that is to say SENSE becomes 1, the peak current and the duty cycle will be updated accordingly to “pull” SENSE back to 0. Based on the simulated current waveform, the maximum rise time and fall time are 173 ns and 74 ns, respectively, without noticeable current overshoot.

Figure 9 compares the power loss differences between the fixed peak current control method and the adaptive control method proposed in this paper. In the fixed peak current method, only the V_boost adjustment step is executed, while the peak current and the duty cycle remain unchanged. As described earlier, under the fixed peak current method, channel 3 experiences the least power loss, while channel 1 and channel 2 suffer greater power losses due to excessive voltage. The figure illustrates the power loss of the three channels under the fixed peak current method. In contrast, with the adaptive control method, both the peak current and the duty cycle are adjusted, effectively eliminating excessive voltage in channel 1 and channel 2, thereby significantly reducing power losses. As depicted in the figure, when the nominal channel current is set to 20 mA, the adaptive control method reduces power loss by 74%.

3.3. Measurement Results

Figure 10 displays a microphotograph of the fabricated chip with bonding wires, along with the chip test setup. The chip is housed in a chip-on-board (COB) package and mounted on the test board. The reference current I_REF is supplied by the test board. An STM32F407 MCU (from ST Microelectronics) development board serves as the brightness controller, and the integrated DAC in the MCU is used to generate V_C. A multi-channel ammeter is connected in series between each LED chain and the drain of the high-voltage MOS transistor to measure the average current of the LED channels. This ammeter supports real-time data recording via a serial port. Voltage waveforms at circuit nodes are captured using a digital oscilloscope, specifically the RTB2004 from Rohde & Schwarz. For simplicity in testing, only two LED channels are implemented, each comprising 6 LEDs. It is noteworthy that the LEDs are intentionally selected to create a difference of approximately 500 mV in the forward voltage across the LED chain between the two channels. Channel 2 has the smaller forward voltage. This deliberate difference enhances the demonstration of the circuit’s effectiveness.

The indoor temperature was maintained at around 27 °C. Figure 11 illustrates the measured voltage waveforms of V_PWM and V_loss for channel 2 after the initial adaptive control process. The channel current setting I_set is 20 mA. The four figures correspond to the case when V_REF is set to 1 V, 0.6 V, 0.4 V, and 0.3 V, respectively. The duty cycle of V_PWM in each case is recorded as 68.57%, 68.86%, 68.43%, and 68.53%, respectively. When V_PWM is high, the channel is turned on, and V_loss in each case is measured at 1.06 V, 0.69 V, 0.49 V, and 0.36 V, respectively. When V_PWM transitions low, the channel is closed, and the increase in V_loss attributes mainly to the influence of leakage current effects. It can be inferred from the figures that despite V_REF decreasing from 1 V to 0.3 V, which may cause the current mirror transistors in the LCR to enter the linear region, the accuracy of the output current can still be maintained, and the duty cycle of V_PWM remains consistent across these settings.

Figure 12 shows the difference in V_loss and power efficiency of channel 2 under both the fixed peak current control method and the adaptive control method. From Figure 12a, it is very obvious that there is an excessive voltage of about 500 mV in channel 2. With the adaptive control method, this excessive voltage is effectively mitigated through adjustments in I_LED, resulting in a substantial improvement in power efficiency. Specifically, when V_REF is set to 300 mV, the power efficiency can reach 98.1% at an I_LED of 20 mA. In principle, it is possible to further improve the power efficiency by reducing V_REF even further, with the upper limit constrained by V_COM, which is up to the power supply.

Table 1. Performance parameters comparison.

Ref	[17]	[41]	[42]	[43]	This work
Process	0.35 μm BCD	0.5 μm CMOS	40 nm CMOS	40 nm CMOS	0.18 μm CMOS
Core area (mm2)	N/A +	N/A +	N/A +	N/A +	0.1
Power supply (V)	6–27	3–4.2	3.2–4.2	3.2–4.2	5
Maximum ILED (mA)	30	20	25	25	48
LED chain config.	8	2	6	6	6
Vboost (V)	26.41	5.36	22.5	20	18.96 *
Vloss (mV)	~400	~300	~675	~480	360 *
Power Efficiency	98.4%	94.4%	97%	97.6%	98.1% *
Vboost adjustment	Yes	Yes	Yes	Yes	Yes
Channel-by-channel adjustment	No	No	No	No	Yes

* Measured at I_set = 20 mA, δ_set = 100%. ⁺ Not available.

compares various parameters and performance metrics between the proposed adaptive driver and other existing references. The proposed design demonstrates advantages such as a wide output current range and high power efficiency. In fact, Table 1 only reveals the efficiency of a single channel. However, more importantly, the proposed adaptive method aims to improve the efficiency of each channel in a multi-channel LED driver. It effectively compensates for excessive voltage on the LCR through adaptive control with moderate implementation complexity.

4. Summary

In this paper, an adaptive high-efficiency LED backlight driver is designed to address the issue of excessive power loss caused by variations in the forward voltage of LEDs. By adjusting the peak current, the consistency in the forward voltage of the LED chain within each channel is achieved. This minimizes the voltage on the LCR in each channel, thereby optimizing the excessive power loss in each channel and the total power efficiency. Furthermore, adjusting the duty cycle ensures brightness consistency across each channel. Based on the 0.18 μm 1P4M CMOS process, an LCR circuit suitable for adaptive control was designed and fabricated. The circuit utilizes a current mirror structure and MOS transistors operating in the linear region to ensure current accuracy and power efficiency. The designed LCR circuit supports an output current range of 0–48 mA. To verify the effectiveness of the adaptive control circuit, an experimental two-channel LED backlight driver was constructed using the designed LCR chips. Each channel consists of 6 LEDs, and the forward voltage difference between channels is intentionally expanded to approximately 500 mV. The test results demonstrate that the presented adaptive control circuit eliminates this forward voltage difference and reduces the excessive power loss. When the reference voltage is set to 300 mV, a power efficiency of 98.1% is achieved at 20 mA. In fact, the experimental two-channel driver can be extended to multi-channel implementation. While only an LCR chip is designed and fabricated in this study, the MP transistors and the brightness controller can both be integrated to realize a monolithic integrated driver chip using BCD processes.