Variable-Frequency Control for Totem-Pole Bridgeless Power Factor Correction Converter to Achieve Zero-Voltage Switching Without Zero-Crossing Detection Circuits

Abstract

The totem-pole bridgeless power factor correction (PFC) converter, known for its advantages including simple topology, capability for zero-voltage switching (ZVS), and low common mode interference, presents an opportunity to enhance the efficiency and environmental friendliness of power systems. However, these converters have issues such as ZVS, requiring zero-crossing detection (ZCD) under circuits’ critical continuous mode (CRM) or additional auxiliary resonant circuits, resulting in increased circuit costs and control complexity. Therefore, this paper proposes a variable switching frequency digital control method to achieve ZVS under a wide operating range without ZCD circuits. At the same time, under the premise of ZVS, an interleaved parallel scheme is adopted to further minimize the current ripple and enhance the quality of the current waveform. Finally, an experimental 2 kW two-phase interleaved totem-pole bridgeless PFC converter prototype is designed to verify that the proposed method is correct and effective. The experimental prototype can reach an efficiency of 97.78%.

1. Introduction

A high power factor (PF) and low total harmonic distortion (THD) can save energy and reduce interference with other electronic devices [1,2,3]. Consequently, power factor correction (PFC) converters are beneficial in power supplies to meet the required power quality standards [4,5]. Figure 1 shows the topology of the bridge boost PFC [6,7], where the rectifier bridge shapes the input voltage into a forward full wave while passing through a classic boost converter to obtain the DC voltage. To achieve power factor correction, sinusoidal pulse width modulation (PWM) is used to synchronize the inductance current with the input voltage. Regardless of whether the power transistor is turned on or off, the current will flow through two slow recovery diodes, so the conduction loss of the bridge PFC is higher, especially at low-voltage input applications [8,9,10].

A great deal of research has been conducted on various bridgeless PFC converters to reduce the conduction losses of bridge diodes [11,12]. The totem-pole bridgeless PFC has a simple structure [13], as shown in Figure 2. It has the advantages of low common mode interference, low conduction loss, and the ability to achieve zero-voltage switching (ZVS) of switches in critical continuous mode (CRM). Therefore, it has been widely applied in power supplies, energy storage systems, telecom infrastructure, electric vehicle battery chargers, etc. [14,15]. Meanwhile, with the development and application of wide-bandgap devices, the totem-pole bridgeless PFC has received significant attention due to the possibility of achieving ZVS for switches operated at high switching frequencies.

To further reduce the conduction loss of the totem-pole bridgeless PFC converter, the two diodes in Figure 2 can be replaced with active switches, as shown in Figure 3. Meanwhile, by adopting proper PWM logic, it can also achieve bidirectional power transfer, which is a solution suited to applications that require battery charging/discharging.

As shown in Figure 3, the totem-pole bridgeless PFC converters feature a simple structure, low component counts, and bidirectional power flow capability, attracting widespread attention [15]. With the development of switches, especially wide-bandgap switches, increasing the switching frequency can help to increase the power density of the system and reduce the size of passive components. However, increasing the switching frequency can lead to dominant switching loss due to the influence of various parasitic parameters of the switches. Likewise, research has been conducted on achieving soft switching in totem-pole bridgeless PFC circuits. The application of this technology can reduce the switching loss generated by the switches during high-frequency operation [16]. It is common to achieve ZVS by operating in CRM [16,17,18,19] or by adding additional auxiliary circuits [20,21,22,23]. Compared to adding auxiliary circuits, operating in CRM requires less auxiliary hardware and does not modify the main electrical circuit. In the CRM operation of totem-pole boost converters, zero-current detection (ZCD) circuits are typically incorporated to detect inductor current zero crossings and minimize switching loss [16,17,18,19]. In [16], optimal switching frequency variation range control is employed to optimize the switching frequency range, where the generation of the ZCD signal involves comparing the current sensing signal with a zero reference point. In [17], auxiliary winding is added to assist in obtaining a ZCD signal, and a simple analog-based accurate variable on-time control is proposed to achieve full-load ZVS and power factor correction. In [18], the body diode conduction of the active switch is detected to adjust the synchronous rectification turn-off time to achieve ZVS with minimum turn-on current and reduce the circulating current. However, several challenges arise for these methods relying on ZCD circuits, particularly at high switch frequencies. These include the inaccurate detection of zero-crossing points due to susceptibility to noise from high dv/dt and di/dt operations and the need for additional detecting circuits and PWM logic generation units [18,19].

On the other hand, auxiliary circuits can be added to achieve ZVS without using ZCD circuits. The authors in [20] propose the use of surge-current-limiting circuits to achieve soft switching of a totem-pole bridgeless PFC converter. Additionally, the authors in [21] combine interleaved totem-pole bridgeless PFC with a post-stage dual-active-bridge converter to form a single-stage structure, achieving partial ZVS. In [22], another switch bridge leg and an auxiliary inductor are used in a totem-pole bridgeless PFC rectifier to achieve ZVS of the main switches. In [23], an auxiliary soft-switching cell composed of two inductors, a capacitor, and an FET is added to achieve ZVS. Nevertheless, for these approaches without ZCD circuits, an additional circuit is added to the main circuit, which can increase the converter components and even complicate the working modes, thereby increasing the control complexity.

Consequently, aiming at ZVS over a wide range without the need for ZCD circuits or other additional components, this paper introduces a digital control strategy with variable-frequency control. This strategy incorporates an additional conduction time compensation mechanism that, by dynamically adjusting the switching frequency, allows the current to build up sufficiently before the corresponding switch is turned on. This effectively discharges the switch junction capacitor and allows ZVS to be implemented. This approach not only eliminates the complexity of ZCD circuits but also enhances the performance and reliability of the converter. In addition, the proposed control strategy is adopted in a two-phase interleaved parallel structure to further reduce the current ripple.

This paper is organized as follows: In Section 2, the ZVS models are analyzed with the consideration of switch junction capacitors. The derivation of the conditions and range are of ZVS given in detail. The variable-frequency control method without ZCD circuits and the increased conduction time are analyzed in Section 3. Subsequently, the totem-pole bridgeless PFC converter with two-phase interleaved connections with the proposed control method is analyzed in Section 4. Section 5 presents the experimental results from a 2000 W prototype that verifies the theoretical analysis and proposed modulation schemes. Finally, Section 6 presents the conclusion.

2. ZVS Analysis Considering Switch Junction Capacitors

Achieving ZVS not only reduces switching loss but also EMI noise. This section establishes ZVS models considering switch junction capacitances, derives the necessary ZVS conditions, and defines the ZVS range. This fundamental analysis is employed for the development of a control method to achieve efficient ZVS.

2.1. ZVS Model Analysis with Junction Capacitors

The diodes in the totem-pole bridgeless PFC, as illustrated in Figure 2, are replaced with two Si MOSFETs (S₃ and S₄), as shown in Figure 4. Combined with corresponding PWM logic, the converter operates in CRM to achieve soft switching. To further reduce switching losses at high frequency, SiC MOSFETs can be used for S₁ and S₂.

Due to the similar working mode of the SiC totem-pole bridgeless PFC converter in the positive and negative half cycles of AC voltage input, the analysis conducted here is based only on the input voltage in the positive half cycle. The main waveforms of the totem-pole bridgeless PFC rectifier operating in CRM are shown in Figure 5 and can be divided into six stages. v_gs1 and v_gs2 are the drive signals of S₂ and S₁, respectively. v_S2 is the drain–source voltage of S₂. i_S1 and i_S2 are the currents of S₁ and S₂, respectively. During the positive half cycle, S₄ stays on, S₃ stays off, and S₂ and S₁ are the main switches operating with high switching frequency.

Stage 1 [t₀–t₁] is shown in Figure 6a. At t₀, S₂ is turned off, and the inductor current i_L charges the junction capacitor C₂ of S₂ while discharging the junction capacitor C₁ of S₁. The duration of stage l is relatively short since i_L is at its peak at t₀ and thus the charging process will be over in a short time. At t₁, S₁ is turned on. After this stage, the current that previously flowed through S₂ continues to flow through S₁. The voltage v_c2 of C₂ can be expressed as

$$v_{c2}(t)=i_L(t_0)t/(2C_{oss})$$

(1)

where C_oss is the junction capacitor of S₁ and S₂, with C_oss = C₁ = C₂.

Stage 2 [t₁–t₂] is shown in Figure 6b. In this stage, at t₁, the voltage v_ds2 of S₂ increases to the bus voltage V_dc. Meanwhile, the voltage v_ds1 of S₁ decreases to 0, and the diode D_S1 of S₁ conducts. S₁ achieves ZVS, and the voltage of L is equal to V_dc − v_ac(t). The inductor current i_L linearly decreases, and i_L decreases to 0 at t₂. In this stage, the inductor current i_L can be expressed as

$$i_L(t)=i_L(t_1)-(V_{dc}-v_{ac}(t))t/L$$

(2)

Stage 3 [t₂–t₃] is shown in Figure 6c. At t₂, S₁ is turned off, and the diode D_S1 of S₁ continues to conduct due to reverse recovery. Moreover, i_L is reversed and continues to decrease, and can be expressed as

$$i_L(t)=-(V_{dc}-v_{ac}(t))t/L$$

(3)

Stage 4 [t₃–t₄] is shown in Figure 6d. At t₃, the diode D_S1 of S₁ is cut off, and C₁, C₂, and L begin to resonate. The voltage v_ds2 of S₂ begins to decrease, and the drain–source voltage v_ds1 of S₁ begins to rise. v_ds2 decreases to the minimum value at t₄, and this stage ends. During this stage, the relationship can be shown as

$$i_L(t)=-(V_{dc}-v_{ac}(t))\sin {\omega }_{0}t/Z+i_L(t_3)\cos {\omega }_{0}t$$

(4)

And the drain–source voltage of S₂ can be expressed as

$$v_{ds2}(t)=v_{ac}(t)+(V_{dc}-v_{ac}(t))\cos {\omega }_{0}t+i_L(t_3)Z\sin {\omega }_{0}t$$

(5)

Here, $Z=\sqrt{L/2C_{oss}}$, ${\omega }_0=1/\sqrt{2C_{oss}L}$.

Stage 5 [t₄–t₅] is shown in Figure 6e. At t = t₄, the drain–source voltage of S₂ decreases to zero, and the diode D_S2 of S₂ conducts. During this stage, i_L rises from a negative state to 0, which can be expressed as

$$i_L(t)=-i_L(t_4)+v_{ac}(t)t/L$$

(6)

Stage 6 [t₅–t₆] is shown in Figure 6f. At t₅, S₂ is turned on by the gate drive signal. If V_ds2 is zero, the turn-on of ZVS will be achieved. Subsequently, i_L increases linearly until t = t₆, and S₂ turns off and repeatedly enters the next cycle. The expression for i_L is

$$i_L(t)=v_{ac}(t)(t-t_5)/L$$

(7)

2.2. ZVS Condition and Region

In stage 4, the totem-pole bridgeless PFC achieves turn-on of the ZVS or valley through the resonance between the inductor current and the junction capacitor of the high-frequency switch. In the traditional CRM, from (5), if I_L(t₃) = 0, the valley value of the voltage v_c2 of C₂ is deduced as v_c2 = 2v_ac(t) − V_dc and the voltage v_c1 of C₁ is v_c1 = v_dc − v_c2(t) = 2v_dc − 2v_ac(t). Therefore, the condition for achieving ZVS in S₂ is

$$v_{c2}(t)=2v_{ac}(t)-V_{dc}\le 0\Rightarrow v_{ac}(t)\le V_{dc}/2$$

(8)

Thus, when the input voltage v_ac ≤ v_dc/2 during its positive half cycle, S₂ can achieve ZVS turn-on. However, it cannot when v_ac > v_dc/2. Under this condition, C₂ needs to be discharged with an additional charge current or energy. The additional charge Q_e needs to meet the following:

$$Q_e\ge C_{s2}(2v_{ac}(t)-V_{dc})+C_{s1}(V_{dc}-(2V_{dc}-2v_{ac}(t)))=2C_{oss}(2v_{ac}(t)-V_{dc})$$

(9)

After normalization, Q_e^* can be obtained:

$${Q_e}^{*}\triangleq Q_e/(2C_{oss}{V}_o)\ge 2v_{in}(t)/V_o-1=2k-1$$

(10)

where k = v_ac(t)/V_dc and Q_e^* is proportional to k.

Equations (9) and (10) yield the ZVS region, which is also shown in Figure 7, illustrating the Q_e^* charge required to achieve ZVS across different instant input voltages, where k is the voltage conversion gain. The graph reveals two regions: the “A-Natural ZVS” region, where ZVS can be achieved without extra charge energy under the case k ≤ 0.5, and the “B-ZVS Expansion” region, denoting ZVS performance under k > 0.5. Notably, for k > 0.5, the inductor current must cross zero to provide an extra charge Q_e* to achieve ZVS. Consequently, in CRM, the charge energy becomes ineffective under k > 0.5 when the inductor current stays at zero, resulting in the absence of soft switching, as observed in traditional CRM.

In real applications, Q_e^* can be generated by adding extended conduction time for the active power switches. However, this extension must be implemented after the zero-crossing point of the inductor current. In conventional control strategies dependent on ZCD, it is insufficient to merely detect the zero-crossing point. The system needs to compensate for the delay and guarantee adequate negative current for the achievement of ZVS. This requires complex calculations and compensations based on the power conditions and the precise timing of the zero-crossing event.

3. Variable-Frequency Control without ZCD Circuits to Achieve ZVS Considering Switch Junction Capacitors

In this section, an eliminating ZCD circuit control method with variable frequency is proposed to achieve the full-range ZVS of totem-pole bridgeless PFC. The circuit model is established with consideration of the switch junction capacitors. Based on this model, the minimum charging current of the inductor is derived, and thus, the additional compensated turn-on time for the switches is obtained. Further, the control to extend the turn-on time is combined with the variable-frequency control in the DSP implementation.

3.1. Conventional Method with ZCD and the Concept Diagram without ZCD

The conventional methods for achieving ZVS typically rely on ZCD circuits, as exemplified in [24]. The corresponding control block diagram is illustrated in Figure 8. As shown, a double loop control is adopted to generate the peak current reference for the hysteresis comparator to compare with the inductor current i_L to control the peak value of the inductor. Meanwhile, a ZCD unit is adopted to control the valley point of i_L. It should be noted that the energy is not sufficienct to discharge the junction capacitor of the switches if the turn-off current is strictly equal to zero, as discussed in Section 2.2. Thus, an adaptive SR time controller is needed to slightly adjust the turn-off time instant. This involves intricate calculations and compensations based on the power conditions and the precise timing of the zero-crossing event. Consequently, the control strategies with ZCD circuits still involve complexity, especially at high switching frequencies utilizing SiC MOSFETs, where accurate timing is critical and delay or noises can affect performance.

Actually, to achieve ZVS for the switches of totem-pole bridgeless PFC converters, the key concept is to ensure that the switch turn-off current stays near zero (the energy is not sufficient to discharge the junction capacitor of the switches if the turn-off current is strictly equal to zero). Essentially, the inductor current value is related to the switching frequency, duty cycle, input voltage, output voltage, etc. So, the desired switch turn-off instant current can be controlled by controlling the switching frequency. Consequently, a concept diagram of the proposed control is shown in Figure 9. As can be seen, a variable frequency control unit is adopted rather than using a ZCD and adaptive SR time controller in Figure 8. Similar to conventional digital control of PFC, the voltage and current loops generate the signal for the PWM unit, and the modulation frequency is controlled through a variable frequency unit (the detailed derivation for the variable frequency will be analyzed in Section 3.2). This direct variable frequency control can respond more precisely, avoiding the possible delay and complexity brought by the ZCD circuit.

3.2. Working Principal Analysis and Variable Frequency Derivation without ZCD to Achieve ZVS

As in a previous discussion, the variable frequency unit is the key controller for the proposed concept. Thus, based on the working principal analysis, illustrating the relationship between the switch turn-off current and the switching frequency and then deriving the frequency control law to achieve ZVS are important. It is also important to investigate how real-time adjustments to the switching frequency function and ensure ZVS without relying on ZCD for zero-crossing detection.

Figure 10 illustrates the operational waveforms of the converter in CRM during the positive half cycle of the AC voltage. During the period in which S₂ is turned on and S₁ is turned off, the voltage across the inductor L is fixed, causing a linear rise in i_L. Concurrently, the input voltage v_ac(t) during this interval is expressed as

$$v_{ac}(t)=V_m\sin (\omega t)=L{i}_{pk}(t)/T_{on}(t)$$

(11)

Here, for S₁, T_on is the turn-on time. Subsequently, i_L linearly decreases when S₁ is turned on, and v_ac(t) is calculated as

$$v_{ac}(t)=V_m\sin (\omega t)=-L{i}_{pk}(t)/T_{off}(t)+V_{dc}$$

(12)

Here, T_off denotes the turn-off time.

With CRM, the envelope of the peak value of i_L(t) is denoted as i_pk(t) = 2i_avg(t). Moreover, throughout a half cycle, i_avg(t) equals the AC current. Therefore, the expression for the peak value of i_L(t) is obtained as

$$i_{pk}(t)=2I_m\sin (\omega t)$$

(13)

Furthermore, the T_on and T_off of the SiC switches can be determined by applying the volt-second area balance principle of the inductor.

$$T_{on}(t)=L{i}_{pk}(t)/v_{ac}(t)=2L{i}_{avg}(t)/v_{ac}(t)$$

(14)

$$T_{off}(t)=L{i}_{pk}(t)/(V_{dc}-v_{ac}(t))=2L{i}_{avg}(t)/(V_{dc}-v_{ac}(t))$$

(15)

Combining (13)–(15), the frequency condition to achieve CRM operation can be derived.

$$f_s(t)=1/(T_{on}(t)+T_{off}(t))=v_{ac}(t)(V_{dc}-v_{ac}(t))/(2L{i}_{avg}(t)V_{dc})$$

(16)

Equation (16) represents the frequency expression in CRM. In digital control, the frequency can be used to update the cycle count value in DSP. Based on (16), the variation trend of f_s within half a cycle is plotted as an example case in Figure 11. As shown, f_s is the lowest at π/2, which is the peak/valley value of the input sine voltage. When v_ac(t) approaches zero, the switching frequency is the highest.

The previous analysis in Section 2.2 shows that in the CRM operation, the totem-pole bridgeless PFC can only naturally achieve ZVS when the input AC voltage is less than half of the output DC voltage.

Figure 12 illustrates the waveform when adding the additional conduction time within the descending phase of the inductor current, where t_e = t₃ − t₂ represents the additional conduction time. Because the two stages of [t₀–t₁] and [t₁–t₂] are the same as the traditional CRM control, which has been analyzed in Section 2.1, they will not be discussed here. Compared to the mode analysis in Section 2.1, an additional mode has been added, which is the additional conduction mode from t₂ to t₃, as shown in Figure 13. The specific analysis for modes from t₂–t₆ is discussed as follows.

Stage 1 [t₂–t₃]: At t₂, the inductor current i_L crosses 0, and the driving signal for S₁ continues to conduct instead of turning off, causing i_L to reverse and continue to decrease. The expression of i_L in this mode is the same as (3). At t₃, i_L decreases to the bias current (or valley point) i_Lzvs to provide energy to charge the switch junction capacitors. The bias current is used to charge and discharge the junction capacitor of the high-frequency switches, which can be expressed as

$$i_{Lzvs}(t)=-(V_{dc}-v_{ac}(t))(t_3-t_2)/L$$

(17)

Stage 2 [t₃–t₄]: At t₃, S₁ is turned off, and the body diode of S₁ undergoes reverse recovery. i_L continues to decrease in reverse, and the duration of this stage is very short.

Stage 3 [t₄–t₅]: At t₄, the body diode of S₁ is cut off, and L, C₁, and C₂ begin to oscillate. At t₅, the voltage of S₂ drops to 0.

Stage 4 [t₅–t₆]: During this mode, the body diode of S₂ is on, and L is charged through S₂. When t = t₅, i_L is reversed. At this stage, the drain–source voltage of S₂ continues to be 0, which means S₂ can achieve ZVS.

Based on the above analysis, the additional conduction time of S₃ and S₄ can be controlled to reverse the charge and store energy for the inductor current, which can be used for the energy charging of the junction capacitor of the switches in the high-frequency bridge arm to achieve ZVS. The analysis of the negative bias current required for the inductor current to achieve ZVS is as follows:

In the resonance stage of inductor L and capacitors C₁ and C₂ (refer to Figure 6 d for the circuit stage), the following formula can be obtained based on the relationship between capacitor current and inductor voltage:

$$C_1{\displaystyle \frac{d{v}_{c1}}{dt}}=i_L+C_2{\displaystyle \frac{d{v}_{c2}}{dt}}$$

(18)

$$L{\displaystyle \frac{d{i}_L}{dt}}+v_{ac}-V_{dc}+v_{c1}=0$$

(19)

$$v_{c1}=V_{dc}-v_{c2}$$

(20)

Taking C₁ = C₂ = C_oss and substituting (20) into (18), the following is deduced:

$$C_{oss}{\displaystyle \frac{d{v}_{c1}}{dt}}=i_L+C_{oss}{\displaystyle \frac{d(V_{dc}-v_{c1})}{dt}}=i_L-C_{oss}{\displaystyle \frac{d{v}_{c1}}{dt}}\Rightarrow 2C_{oss}{\displaystyle \frac{d{v}_{c1}}{dt}}=i_L$$

(21)

Based on (1) and (21), the equivalent circuit displayed in Figure 14 can be illustrated.

From the above equivalent circuit, based on energy conservation, (22) can be obtained, where i_Lzvs is the bias current to achieve the turn-on of ZVS in the main switch.

$$0.5L{i}_{Lzvs}^2\ge {\displaystyle \int (v_{ac}-V_{dc})i_{L}dt+0.5\cdot 2C_1{v}_{c1}^2}$$

(22)

Substituting (21) into (22) yields the i_Lzvs conditions that need to be met to achieve the main switch ZVS.

$$i_{Lzvs}(t)\ge \sqrt{2[2C_{oss}{V}_{dc}(v_{ac}(t)-V)(v_{ac}(t)-V_{dc})]/L+C_{oss}{V}_{dc}^2}$$

(23)

Therefore, by substituting the relevant circuit parameters into (23), the bias current required for the main switch to achieve ZVS can be plotted as an example to show the inductor current required to achieve ZVS under different instant input voltages, as shown in Figure 15. As shown, when the grid voltage is relatively low, ZVS can be achieved without the need for additional negative current. When the grid voltage is higher, the switches need an additional negative bias current to achieve ZVS.

Consequently, through substitution of the required inductor current into (16), the frequency condition to achieve full-working-range ZVS can be calculated as

$$f_{s\_full}(t)=v_{ac}(t)(V_{dc}-v_{ac}(t))/[2L(i_{avg}(t)+i_{Lzvs}(t))V_{dc}]$$

(24)

4. Current Ripple Reduction and Digital Implementation of the Proposed Control Method

As previously mentioned, achieving ZVS in CRM reduces switching turn-on losses, but the peak-to-peak inductor current, nearly double the average current, can increase high-frequency ripple at the AC input. To mitigate this issue, the proposed control method can be applied to a totem-pole bridgeless PFC converter with two-phase interleaved connections [25]. This section provides current ripple models to demonstrate the effectiveness of the interleaved structure and analyzes how the proposed control method is implemented in this configuration.

4.1. Current Ripple Reduction with Two-Phase Interleaving for Totem-Pole Bridgeless PFC Converter

Two-phase interleaving refers to adding a set of high-frequency bridge arms and inductors to the original single-phase totem-pole bridgeless PFC topology and multiplexing the power frequency bridge arms for parallel connection. It is worth noting that each phase in an interleaved structure can be regarded as operating independently. The interleaving structure does not alter the fundamental working principle of each phase. The topology is shown in Figure 16. High-frequency switches S₁ and S₂ and inductor L₁ form the main phase; high-frequency switches S₅ and S₆ and inductor L₂ form the secondary phase; and S₃ and S₄ are multiplexed as the main and secondary phases.

4.2. Analysis of Current Ripple Reduction with Two-Phase Interleaving

The duty cycles d of the two main switches S₂ and S₆ are the same, while the driving phase for them is 180° phase-shifted, causing the inductor current of the main and secondary phases to differ in phase by 180°. The synchronous rectifiers S₁ and S₅ complement the main switches S₂ and S₆ in conduction. Due to the on-and-off states of S₂ and S₆, the converter consists of four different stages based on the analysis of the input voltage during the positive half cycle. When the interleaved converter operates in CRM, they have different current waveforms at duty cycles d ≤ 0.5 and d > 0.5. Figure 17a shows the main waveform of the inductor current with d ≤ 0.5, and Figure 17b shows the main waveform of the inductor current with d > 0.5. The following is an analysis of the current ripple under these two cases.

(1)

d ≤ 0.5

From Figure 17a, the inductor currents i_L1 and i_L2 of the two phases both linearly decrease in the [t₁–t₂] and [t₃–t₄] stages, indicating that the above converter operates in Mode 4. Based on the equivalent circuit of Mode 4, it can be concluded that

$$\{\begin{array}{l}{L}_1\Delta i_{L1}/\Delta t=V_{dc}-v_{ac}\\ L_2\Delta i_{L2}/\Delta t=V_{dc}-v_{ac}\end{array}$$

(25)

At steady state, the expression for the duty cycle d is

$$d(t)=1-|v_{ac}(t)|/V_{dc}$$

(26)

Assuming that the two inductors are the same, there are

$$\{\begin{array}{l}{L}_1=L_2=L\\ \Delta t=(1/2-d)T\\ \Delta i_{in}=\Delta i_{L1}+\Delta i_{L2}\end{array}$$

(27)

Substituting (26) and (27) into (25), the total input current ripple can be obtained as

$$\Delta i_{in}=d(1-2d)v_{ac}/[(1-d)L{f}_s]$$

(28)

(2)

d > 0.5

In the stages of [t₀–t₁] and [t₂–t₃], the inductor currents i_L1 and i_L2 of both phases increase linearly, corresponding to operating Mode 1 of the converter mentioned above. Therefore, according to the corresponding equivalent circuit, it can be obtained as

$$\{\begin{array}{l}{L}_1\Delta i_{L1}/\Delta t=v_{ac}\\ L_2\Delta i_{L2}/\Delta t=v_{ac}\end{array}$$

(29)

Similarly, there are

$$\{\begin{array}{l}{L}_1=L_2=L\\ \Delta t=(d-1/2)T\\ \Delta i_{in}=\Delta i_{L1}+\Delta i_{L2}\end{array}$$

(30)

Substituting (26) and (30) into (29), the total input current ripple can be obtained as

$$\Delta i_{in}=(2d-1)v_{ac}/(L{f}_s)$$

(31)

Based on the volt–ampere relationship of the inductor current, it can be obtained by combining (28) and (31) that the input current ripple expression of the interleaved converter in CRM can be obtained as

$$\Delta i_{in}=\{\begin{array}{l}d(1-2d)v_{ac}/[(1-d)L{f}_s] d<0.5\\ (2d-1)v_{ac}/(L{f}_s) d\ge 0.5\end{array}$$

(32)

The ripple current of a single inductor is

$$L\Delta i_L/\Delta t=v_{ac}\Rightarrow \Delta i_L=v_{ac}\Delta t/L=d{v}_{ac}/(L{f}_s)$$

(33)

The ratio of the total input current ripple to the current ripple of a single inductor is defined as α = ΔI_in/ΔI_L. Substituting (32) into (33) yields

$$\alpha =\{\begin{array}{l}(1-2d)/(1-d) d<0.5\\ (2d-1)/d d\ge 0.5\end{array}$$

(34)

According to (34), the relationship between the current ripple ratio α and the duty cycle d is shown in Figure 18. According to Figure 18, the ripple current is always smaller than the single ripple current (ripple ratio α < 1) after interleaving. And when d is around 0.5, the current ripple after interleaving is canceled. Therefore, adopting the interleaved parallel scheme has advantages in reducing the current ripple of the converter in CRM.

4.3. Digital Implementation of the Proposed Control Method for Two-Phase Interleaved Parallel Totem-Pole Bridgeless PFC

The control methods of interleaving are mainly divided into open-loop interleaving based on the ZCD circuit and closed-loop interleaving based on a phase-locked loop. Open-loop interleaved parallel connection divides each phase circuit into one main phase and multiple secondary phases, where the main phase circuit works independently like a single-phase PFC converter. It can work in current mode or voltage mode, and the driving signals of each secondary phase are obtained based on the driving signals of the main phase after a certain delay. It can be divided into four categories based on the working mode of the circuit and the synchronization time of each phase: voltage mode on-time synchronization, current mode on-time synchronization, current mode off-time synchronization, and voltage mode off-time synchronization. Closed-loop interleaving adjusts the turning-off time of the secondary phase based on phase error, thereby achieving an interleaving parallel connection. The above two methods require a ZCD circuit on both the primary and secondary phases, increasing the complexity of the circuit.

According to the previously discussed variable-frequency control method without the use of ZCD circuits, the proposed digital control strategy for a two-phase interleaved parallel totem-pole bridgeless PFC is illustrated in Figure 19. As illustrated, this integration enables the control method to achieve ZVS without the need for supplementary sensors, auxiliary circuits, or ZCD circuits, thereby enhancing noise immunity and ensuring precise control. The output voltage of the rectifier is sampled as the feedback of the output voltage loop, and the output of the voltage loop is multiplied with the grid phase to generate the reference of the inner current loop, in which the phase of the current is obtained through a digital PLL unit. The frequency calculation unit calculates the on-time frequency based on the equation shown in (24) and updates the timer in the DSP in each switching cycle. The duty cycle of each switch is calculated based on the output of the inner current loop with a feedforward of the AC voltage.

5. Experimental Verification

To validate the effectiveness of the proposed control method for the totem-pole bridgeless PFC converter, a 2000 W experimental prototype was designed for practical verification. The experimental prototype is shown in Figure 20. The main parameters of the experimental prototype are provided in

Table 1. Main parameters of the prototype.

Parameters	Value	Parameters	Value
AC voltage (vac)	110 V, 50 Hz	DC bus capacitor (Cdc)	2000 μF
DC voltage (Vdc)	280 V–370 V	AC inductance (L1, L2)	56 μH
Rated power (Pdc)	2000 W	Operating frequency (fs)	40–200 kHz

.

Utilizing the variable-frequency control method, Figure 21 illustrates the forward and reverse power operation waveforms of a single-phase full load (1000 W) under the proposed control method. The output bus voltage on the DC side is 280 V and 370 V in Figure 21a,c and Figure 21b,d, respectively, which show two operation cases for k > 0.5 and k < 0.5. As seen, the inductor current i_L1 has a small current bias instead of staying at zero in both positive and negative half cycles for all the waveforms, indicating the effectiveness of the current value control near the zero-crossing point. It can be observed that the inductor current can be negative, which is a crucial characteristic of the additional conduction time.

Comprehensive simulations were conducted to further validate the effectiveness of the proposed variable switching frequency with additional conduction time. As shown in Figure 22a, when the additional conduction time is injected based on (24), the inductor current is negative before S₂ turns on. This negative current plays a crucial role in discharging the switch junction capacitor of S₂, thereby facilitating the achievement of ZVS. In contrast, as depicted in Figure 22b, when the variable-frequency control is implemented without the additional conduction time based on (16), i_L is nearly zero before S₂ turns on, resulting in hard switching.

Figure 23 shows the performance of the current ripple reduction adopting the interleaved structure under different load conditions. As can be seen, after interleaving, the current ripple of the sum of the two inductor currents (i_L1 + i_L2) becomes much smaller compared with the one for each single phase (i_L1 or i_L2). Additionally, the expanded waveforms for the three currents are also shown, which demonstrate the effectiveness of the current ripple reduction.

Figure 24 shows the ZVS achievement of the two switches S₁ and S₂ on the single-phase full load (1000 W) in the traditional CRM control method. As seen in Figure 24c, S₂ cannot achieve ZVS when k > 0.5, indicating that the ZVS region is limited when the converter only operates in CRM and that ZVS cannot be achieved over a wide voltage range.

Figure 25 shows the ZVS performance in the main switch with a single-phase full load (1000 W) under the proposed variable-frequency control method for the converter at different DC side output voltages. As shown in Figure 25a,c, if the DC bus voltage is greater than the AC voltage and the negative bias current is increased, both at V_dc = 280 V and V_dc = 370 V, when the input voltage is in the positive half cycle, S₂ achieves ZVS turn-on. Similarly, within the negative half cycle, S₁ can also achieve ZVS. Therefore, it is verified that the variable-frequency control without ZCD circuits proposed in this paper can achieve ZVS in the totem-pole bridgeless PFC converter under different output voltages.

Figure 26 shows the ZVS implementation for the single-phase half load (500 W) output of the converter under the proposed variable-frequency soft-switching control method. As shown in Figure 26a,b, the main switch S₂ achieved ZVS at different input voltage values and under different voltage conditions during the positive half cycle.

Figure 27 shows the power loss breakdown under different loads, including half load (1000 W) and full load (2000 W). These losses can be categorized into three main areas: conduction losses of switches (P_con), switching losses (P_sw), and core and iron losses of inductors (P_ind). Due to the achievement of ZVS, the switching turn-on loss theoretically approaches zero, resulting in a relatively lower P_sw. On the other hand, P_con emerges as the dominant factor in the overall loss distribution. Meanwhile, P_ind increases as the transferred power increases.

The efficiency curve of the two-phase interleaving of the converter is given in Figure 28. With an input AC voltage of 110 V, the efficiency at rated power is 97.72%. The converter can obtain a peak efficiency of 97.78% with the proposed full-range ZVS control strategy.

Table 2. Comparisons of the proposed method and existing methods.

Article	Number of Switches	Number of Inductor	Number of Diode	Rated Power	Voltage Stress	Peak Efficiency	THD
[2]	4	3	2	1600	Vdc	98.2%	6.83%
[19]	6	2	0	2000	Vdc	99%	3%
[20]	4	2	2	800	Vdc	97.8%	—
[26]	4	3	2	1000	Vdc	97%	7%
Proposed	6	2	0	2000	Vdc	97.72%	11.39%

shows comparisons of the proposed converter and other totem-pole bridgeless PFC converters in the literature. The converters in [2,20,26] are limited to unidirectional power flow applications, with [2,26] requiring additional magnetic components. In addition, a ZCD circuit is needed in [19]. In conclusion, the main advantages of our proposed converter include its control simplicity, the absence of ZCD circuits, and the soft-switching capabilities suitable for bidirectional power flow applications.

6. Conclusions

This paper proposes a variable-frequency control method without the need for ZCD circuits to address issues in existing totem-pole bridgeless PFC converters, such as high circuit cost and complex circuit control due to the use of the ZCD circuit or auxiliary resonant circuit to achieve ZVS. Through a detailed analysis of the ZVS model considering switch junction capacitors, it can be found that, in traditional CRM, when k > 0.5, the energy is insufficient to fully charge/discharge the junction capacitors, resulting in the loss of ZVS. After introducing an additional conduction time, the current when the switch is turned on can be increased, providing enough energy to maintain ZVS. Consequently, a variable-frequency control scheme is proposed to provide this additional conduction time. Additionally, an interleaved parallel connection method is adopted to reduce the inductor current ripple. A digital control block diagram based on this variable-frequency method for the interleaved totem-pole bridgeless PFC converter is given. The experimental results demonstrate the effectiveness of the proposed approach, showing that a wide range of ZVS can be achieved and the current ripple can be reduced.