Designing a Scalable and Area-Efficient Hardware Accelerator Supporting Multiple PQC Schemes
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Jung, H.; Oh, H. Designing a Scalable and Area-Efficient Hardware Accelerator Supporting Multiple PQC Schemes. Electronics 2024, 13, 3360. https://doi.org/10.3390/electronics13173360
Jung H, Oh H. Designing a Scalable and Area-Efficient Hardware Accelerator Supporting Multiple PQC Schemes. Electronics. 2024; 13(17):3360. https://doi.org/10.3390/electronics13173360
Chicago/Turabian StyleJung, Heonhui, and Hyunyoung Oh. 2024. "Designing a Scalable and Area-Efficient Hardware Accelerator Supporting Multiple PQC Schemes" Electronics 13, no. 17: 3360. https://doi.org/10.3390/electronics13173360