Isolated Gate Driver for Medium Voltage Applications Using a Single Structure

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

Dear authors kindly find the following comments and questions:

1.      Please include your results in the abstract section clearly and shortly.

2.      In the introduction section, the nobilities of the study and the new method employed must be introduced properly. The blocks of figure 2 needs further explanation.

3.      The result in figures 11 is not clear. The method/ a clear procedures are not followed, the tool/tools used for simulation is not mentioned, the physical model is not explained, the data used for simulation also not mentioned. Additionally, the figure quality is very poor.

4.What are the contributions of this study?

Author Response

Dear Reviewer,

We greatly appreciate your comments. They have been addressed according to your suggestions. We are attaching the revised paper, which includes the following changes (highlighted in blue).

1. Please include your results in the abstract section clearly and shortly.

Some results were included in the abstract as per your suggestion.

1. In the introduction section, the nobilities of the study and the new method employed must be introduced properly. The blocks of figure 2 needs further explanation.

The introduction now includes your suggestions, and Figures 1 and 2 were also modified for better comprehension.

1. The result in figures 11 is not clear. The method/ a clear procedures are not followed, the tool/tools used for simulation is not mentioned, the physical model is not explained, the data used for simulation also not mentioned. Additionally, the figure quality is very poor.

The design example section has been revised to incorporate your suggestion for clarity. Figure 11 now has improved quality.

1. What are the contributions of this study?

The article introduces a power switch gate driver for MV applications, where very high isolation capabilities are needed. Commonly, gate drivers are implemented using two blocks: one dedicated to power and the other to the gate signal. In this article, we propose a gate driver that uses a single block. This is achieved by modulating the power switch gate signal into the control signal of an isolated resonant converter that uses air as the isolating barrier. The proposed driver was implemented, and the experimental results show excellent performance.

We appreciate your comments very much, they improve the article. The updated version we are sending also includes suggestions of the reviewers 2 and 3.

Best regards.

The Authors

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

Dear authors, I have the following suggestions for paper improvements:

 

1.       The Abstract. You may want to suggest the possible application of the middle voltage power converters, the power range and the switching frequency range. This will better introduce the reader to the research that has been developed.

 

2.       At the end of part 1. You may want to clarify your research aim and novelty better. The benefits you aim at could be better stated.  

 

3.       Part 2. The proposed driver topology is well-presented. However, you may want to add a table with the driver's main parameters, such as maximum frequency, propagation delay, etc.

 

4.       Part 3. The central part of the power stage is the input MOSFET bridge (Q1-Q4). You may want to clarify how these transistors in a full bridge are connected to the control system. For example, it is not clear whether they need gate drivers themselves. In this case, the topology in Fig. 1 could have been integrated into the proposed topology in Fig. 3. If so, this could minimise the advantages you initially suggested.

 

5.       Parts 2 and 3. You may want to clarify the differences in the suggested driver topology and its operation if applied to Si (MOSFETs and IGBTs) and SiC MOSFETs.

 

6.       Part 4. You may want to extend the gate driver design example. Considering the input design parameters, can you specify the requirements for the transistors Q1-Q4 and diodes D1-D4 selection? Nothing is given about how the semiconductors were calculated and selected.

 

7.       Part 5. The experimental verification is well presented. However, you may want to better systemise the advantages and disadvantages (part 5.4 Discussion) by comparing the obtained results to the conventional solutions.

 

 

Thank you for the interesting paper.

 

 

Author Response

Dear Reviewer,

we appreciate very much comments. We are attaching the paper which includes the changes (written in blue).

 

1. The Abstract. You may want to suggest the possible application of the middle voltage power converters, the power range and the switching frequency range. This will better introduce the reader to the research that has been developed.

Your suggestion has been included.

 

2. At the end of part 1. You may want to clarify your research aim and novelty better. The benefits you aim at could be better stated.  

Your suggestion has been included.

 

3. Part 2. The proposed driver topology is well-presented. However, you may want to add a table with the driver's main parameters, such as maximum frequency, propagation delay, etc.

Now there are not commercially gate driver for high-voltage power switches, so a customized isolated gate driver must be developed. The main parameters are target voltage insolation and power required based on the capacitance to be driver. This information is the star point given in the gate driver design section. The main idea of part 2 is to describe the proposed gate driver.

 

4. Part 3. The central part of the power stage is the input MOSFET bridge (Q1-Q4). You may want to clarify how these transistors in a full bridge are connected to the control system. For example, it is not clear whether they need gate drivers themselves. In this case, the topology in Fig. 1 could have been integrated into the proposed topology in Fig. 3. If so, this could minimise the advantages you initially suggested.

In MV applications, the power switches are connected in a string configuration (Figure 1). Each floating switches must have its own isolated gate driver. The upper switch must have the highest isolation capability. The proposed topology (as shown in Figure 2) must be integrated into Figure 1. This is not a disadvantage; this must be implemented in this mode.  

 

5. Parts 2 and 3. You may want to clarify the differences in the suggested driver topology and its operation if applied to Si (MOSFETs and IGBTs) and SiC MOSFETs.

 In MV application, the power switches which are being used are SiC, IGBTs or MOSFETs. Particularly because its higher blocking voltage, reducing the number of power switches used in the string. In the paper, we refer to the specifications of a SiC MOSFET which have, currently commercially available, the highest blocking voltage.

 

6. Part 4. You may want to extend the gate driver design example. Considering the input design parameters, can you specify the requirements for the transistors Q1-Q4 and diodes D1-D4 selection? Nothing is given about how the semiconductors were calculated and selected.

The current on the MOSFETs is calculated from the simplified circuit shown in Figure 9. At resonant frequency (Xcrp = Xequiv), so, the maximum current MOSFET is (at maximum transmitted duty cycle):

I_MOSFETs= V_in / R_equiv = 14.2 Amps.

R_equiv is equation (8) in the article.

 

(Voltage and current waveforms simulation at 100% of the transmitted duty cycle)

 The voltage stress is the input voltage (12volts). We use an available laboratory MOSFET, it was the IRFB20N50K (500 Volts, 20 Amps, 0.21 Ω, 25°C). The  maximum voltage is ridiculous regarding the necessary, but it was the available MOSFET in our laboratory. A similar situation was about the diodes. We use the same output diodes in the power resonant stage than in the demodulator circuit. They must support a very low voltage and current, but with very fast recovery time. That was the main reason we decide not to include that information.

 

7. Part 5. The experimental verification is well presented. However, you may want to better systemise the advantages and disadvantages (part 5.4 Discussion) by comparing the obtained results to the conventional solutions.

Your suggestion has been included in an extra table.

 

We appreciate very much your comments, they improve the article.

The authors.

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

I have read your manuscript and please consider some aspects that I think should be corrected or improved. I will present them below in the order of their appearance.

1.      In Figures 3, 6 and 10 you have to use the standard IEC electrical symbol for DC ideal voltage generator.

2.      In (7) replace Img with Im

3.      Table 1, in the Description column , try to write one line per item(if necessary you can enlarge the length of table on horizontal). The same situation for Table 3.

4.      In (10) and other equations, you have to write Greek symbols non-ityalic both in text of the manuscript and equations.

5.      On row 210, equation isn’t numbered. Also, you have to use only ” × ” symbol for multiplication, remove “ * ”symbol.

6.      In Table 4, in the “Air gap” line, use 25mm instead of 2.5cm.

7.      In Figures 15,17,19 – please add a dot after “vs”

8.      In Table 5, please write 10.4μs instead of 10.4us.

 

9.      You have to add more references, as recently as possible - the existing ones are quite old. 

Author Response

Dear Reviewer,

we appreciate very much comments. They were attended acording your suggestions. We are attaching the paper which includes the following changes.

1. In Figures 3, 6 and 10 you have to use the standard IEC electrical symbol for DC ideal voltage generator. OK
2. In (7) replace Img with Im. OK
3. Table 1, in the Description column , try to write one line per item(if necessary you can enlarge the length of table on horizontal). The same situation for Table 3. OK
4. In (10) and other equations, you have to write Greek symbols non-ityalic both in text of the manuscript and equations. OK
5. On row 210, equation isn’t numbered. Also, you have to use only ” × ” symbol for multiplication, remove “ * ”symbol. OK
6. In Table 4, in the “Air gap” line, use 25mm instead of 2.5cm. OK
7. In Figures 15,17,19 – please add a dot after “vs” OK
8. In Table 5, please write 10.4μs instead of 10.4us. OK
9. You have to add more references, as recently as possible - the existing ones are quite old. Some references were added or updated.

Best regards.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

well done!

Reviewer 2 Report

Comments and Suggestions for Authors

My questions were competently answered.

I would recommend that the paper be accepted into the journal.

Thank you.