High-Speed Signal Optimization at Differential VIAs in Multilayer Printed Circuit Boards

Abstract

The number of Printed Circuit Board (PCB) layers is continually increasing with the increase in data transmission rates, and the Signal Integrity (SI) of high-speed digital systems cannot be ignored. Introducing Vertical Interconnect Accesses (VIAs) in PCBs can realize the electrical connection between the top layer and the inner layers, however, VIAs represent one of the most important reasons for discontinuity between the PCBs and package. In this paper, a new optimization scheme for a differential VIA stub is proposed, with 3D full-wave numerical simulation used for modeling and simulation. Results show that this scheme optimizes the return loss and insertion loss while making the signal eye diagram more ideal, which can improve the transmission effect of high-speed signals.

1. Introduction

Nowadays, the data rate of high-speed digital systems has expanded from a few Gbps to tens or even hundreds of Gbps. Electrical modeling of high-speed channels is very important for digital system design [1,2,3]. VIAs are essential structures in high speed multilayer PCB design, and the introduction of a VIA structure can realize signal layering and packaging link [4]. In this way, signal transmission between each device on the PCB and the inner layers is realized. At present, many studies exist on different parameters of VIA structures in high-speed PCBs. Because differential transmission produces strong anti-interference, most high-speed signals are transmitted using differential transmission systems [5].

VIAs are special structures composed of a hollow cylinder, pads, and anti-pads. Unfortunately, the introduction of VIAs leads to discontinuity of the signal transmission line, causing the signal to reflect [6]. To date, many studies have been carried out on VIAs. The literature [7] explores the effect of the distance between differential VIAs on signal transmission. It has been proven that when the distance between VIAs exceeds 140 mil, the crosstalk will be greater than 20 dB. In addition, increasing the surrounding Ground Return VIAs (GRVs) can reduce this crosstalk; the more ground VIAs, the more obvious this effect. The same study describes the relationship between GRV placement and data rate as well as the effects on insertion loss, VIA impedance, and crosstalk. The literature [8] has continued to explore GRVs on the basis presented in [7]. The effect of different numbers of GRVs on the signal at the differential VIAs has been verified by experiments, with the results the same as those reported in [7]. More GRVs have a greater optimization effect on the S-parameter. However, as PCB designs may not have enough space to place all GRVs, the tradeoff between performance and the number of GRVs has to be considered. In [9], the authors extended the work and concepts presented in [8] to include the Differential Signal VIA (DSV) and the GRV surrounding it, proving that in many cases increasing the number of GRVs increases crosstalk rather than reducing it, which is counterintuitive after years of a ‘more is better’ design approach. In this paper, two GRVs are designed for locations on both sides of the differential VIAs.

A high-speed differential VIA model was developed in [10]. The authors analyzed the differential VIA spacing and the distance between the GND VIAs and differential VIA through analysis of different S-parameter values obtained by simulation. Notably, the insertion loss and the return loss of the differential VIA can decrease for a larger VIA pitch above 30 GHz. However, for frequencies below 20 GHz a larger VIA pitch can result in increased differential return loss. On the other hand, smaller the spacing between the GND VIAs and the differential VIA results in smaller insertion loss.

In [11], the authors proposed new optimization methods for VIA structures which have good performance in GHz digital systems. Several key factors affecting the performance of differential VIAs were analyzed, including stubs, nonfunctional pads, and ground VIAs. Simulation results showed that the stubs make the signal resonate and that shortening the stub can gradually eliminate the resonance. In addition, removing nonfunctional pads and adding additional ground VIAs can help to improve the high frequency performance of the system.

In this paper, a pair of differential VIA model in a 12-layer PCB is constructed and a new optimization scheme of the VIA structure is proposed. Numerical results from 3D full-wave simulations show that the optimization scheme proposed in this paper reduces the influence of resonance on signal transmission and has a significant optimization effect on both the insertion loss and return loss. In addition, this scheme can provide a useful reference scheme for engineers involved in PCB design.

2. Theoretical Analysis of Resonance

Resonance, a major problem for SI, refers to the resonance cavity effect formed when the energy is sandwiched between two parallel plates. This occurs because the original signal is in phase with its reflected signal [12]. At low to medium frequencies, the ground–power plane pair can be regarded as an ideal capacitor with small Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL) [13]. When the frequency reaches a higher frequency range, the ground–power plane pair forms a resonant cavity equivalent to an RLC series parallel circuit. Near the resonant frequency point, the impedance of the plane with respect to the ground becomes very large, resulting in SI problems [14].

On a multilayer PCB, the parallel plane and the dielectric material (such as the ground–power plane pair and the medium material between them) can be regarded as a rectangular microwave resonator [15]. Under these conditions, certain electromagnetic fields of specific frequencies form standing waves, and these frequencies become resonant frequencies [16,17]. When the signal is transmitted from the top layer to the inner layers and passes through the resonator, if the frequency of the input signal is sufficiently close to a certain anti-resonant frequency, then the input signal will be equivalent to the excitation source of the parallel plate resonator inside the PCBs. At this time, the parallel plate resonator formed by the ground–power plane pair becomes excited and electromagnetic field accumulates in the resonator, resulting in resonance.

Resonance can cause many SI-related problems on PCBs. For example, the resonant frequencies may be the same as the operating frequencies of the devices on the boards, which causes resonance and affects the working performance of these devices. On the other hand, the power planes show high impedance behavior at the resonant frequencies, which prevents most of the noise and energy from finding a return path in the Power Distribution System (PDS). This results in large voltage amplitude changes at the standing wave belly, which becomes a significant source of noise and generates serious electromagnetic radiation at the edge of the PCB [18]. This also causes substantial signal loss, as reflected in the return loss and insertion loss curves, as the signal amplitude decreases at the resonant frequencies and forms a sharp peak [19,20,21]. In either case, the performance of the board will decline and the design may even fail, resulting in a prolonged design cycle and increased costs.

At present, the resonance problems in PCB design are mainly solved in two ways: installing decoupling capacitors, or optimizing the PCB stack design, PCB layout, and routing [22,23,24]. When the operating frequency of the high-speed system is less than 400 MHz, it is helpful to install appropriate decoupling capacitors in appropriate positions in order to reduce SI problems. When the system rate is higher, the effect of decoupling capacitances is reduced, and only optimization of the PCB stack design and layout, reducing the power plane voltage, and impedance matching can reduce SI problems. In this paper, the simulated frequency reaches as high as 30 GHz; although decoupling the capacitances is necessary at such high frequencies, the stack design of the PCB should also be optimized in order to reduce SI problems on the circuit boards.

Figure 1 shows the rectangular parallel plate resonator model. The upper and lower identical planes and the medium between the two plates can be regarded as a parallel plate metal resonator. According to the cavity mode resonance method, it is possible to calculate the frequency when there is high resistance according to the physical parameters of the PCB and the parameters of the dielectric material. The resonant frequency of the resonant cavity formed by the metal planes in the PCBs can be obtained by Equation (1) [25].

$$f_{mn}(m,n)={\displaystyle \frac{1}{2\pi \sqrt{{\mu }_0{\epsilon }_0{\epsilon }_r}}}\sqrt{{\left({\displaystyle \frac{m\pi }{a}}\right)}^2+{\left({\displaystyle \frac{n\pi }{b}}\right)}^2}$$

(1)

In Equation (1), ${\mu }_0$ is the permeability in vacuum, ${\epsilon }_0$ is the permittivity in vacuum, ${\epsilon }_r$ is the relative permittivity of the dielectric material, a,b are the length and width of the PCBs, and m,n are non-negative integers that cannot be 0 at the same time.

3. VIA Modeling

With the advancement of technology, in recent years the design of PCBs has encountered new requirements in terms of size, transmission speed, and component integration. In order to meet these needs, PCB design is developing towards multilayer structures, which have to introduce VIAs to achieve electrical connections between different layers [26,27]. However, in high-speed digital circuits, VIA stubs such as antennas release electromagnetic radiation and receive interference, seriously affecting the transmission quality of the signal.

When the signal is transmitted from the top layer to the bottom layer through the VIAs to the connected signal layer, part of the signal continues to advance along the signal layer and part of it propagates downwards until the end of the VIA stubs [28,29,30]. When the signal reaches the bottom of the VIAs, it is reflected, transmitted back along the stubs, and separated at the layer switching point. Part of the signal is returned to the source end, causing reflection, while the other part continues to propagate along the same direction as the original signal. When the phase shifts of the original signal and the reflected signal equal 180 degrees, resonance is generated. When the transmission rate exceeds 10 Gbps, the integrity of high-speed signals is seriously affected by the VIA stubs.

In this section, the 3D model of the VIAs is established [31], as shown in Figure 2. In addition, the parameters are modified to verify the research of other scholars and the new VIA optimization scheme is verified by experiments. The details of the optimization scheme are listed in

Table 1. Detailed comparison between the optimization scheme proposed in this paper and previously proposed schemes.

Optimization Scheme	Measures Taken
Scheme 1	The influence of the back-drill length on the S-parameter was investigated by keeping the VIA radius and anti-pad radius constant.
Scheme 2	The influence of the anti-pad radius on the S-parameter was investigated by keeping the VIA radius and back-drill length constant.
Scheme 3	On the basis of Scheme 1 and Scheme 2, the radius of the VIAs and anti-pads and the length of back-drill all remained unchanged, then anti-pads were added in the part troughed by the back-drill. The influence on the S-parameter was investigated.

; Scheme 1 is validated in Section 3.1 and Scheme 2 in Section 3.2.

3.1. Parametric Analysis of VIA Stub Length

As mentioned in Section 1, the stub of the VIAs makes the signal resonant, affecting the signal transmission. Therefore, in this subsection, the impact of the stub is modeled and verified by simulation.

The differential VIA structure designed in this paper is located in a 12-layer PCB. The signal flows from the top layer to the fifth layer and is back-drilled from the bottom layer to the sixth layer. The total thickness of the board is 57.5 mil, and the total length of the part that can be back-drilled is 36.4 mil [32]. Due to the limitation of the production process, at least 2 mil stubs will remain when the VIAs are back-drilled. In order to be closer to the actually production situation, the length of the back-drill is controlled to change from 33 mil to 27 mil while the radius of the anti-pads is kept at 16 mil and the VIA radius keep constant, allowing the influence of the VIA stub length on the S-parameter to be analyzed. The numerical results of our 3D full-wave numerical simulations are shown in Figure 3 and Figure 4.

It can be seen from Figure 3 that the return loss curve has a sinking tip when the back-drill length is 33 mil at a frequency of about 13 GHz or when the back-drill length is 35 mil at a frequency of about 18 GHz. This is due to the fact that a relatively complete parallel plate resonator is formed in the power layer, with 13 GHz and 16 GHz being the exact resonant frequencies of this resonator. This corresponds exactly to the previous description of the VIA stub. However, Figure 4 shows that the insertion loss curve is smooth at the frequencies of 13 GHz and 16 GHz; thus, it can be seen that the resonance does not have a negative impact on signal transmission at this time.

Therefore, the results shown in Figure 3 and Figure 4 indicate that when the back-drill length of PCB gradually increases from 27 mil to 33 mil, the insertion loss and return loss successively decrease. As such, in high-speed PCB design the length of the back-drill should be increased as much as possible in order to minimize the stub of the VIAs; if necessary, a buried VIA or blind VIA can be used.

3.2. Parametric Analysis of Anti-Pad Radius

Anti-pads are mainly used to control the distance between the inner VIAs and the copper in the negative film process as well as to prevent short-circuits between the copper and the VIAs [33]. In addition, the VIAs and the surrounding copper form a capacitive system in which the size of the anti-pads affects the capacitive impedance of the VIAs. This capacitance leads to low impedance at the VIAs, causing discontinuity in the signal transmission links and resulting in reflection.

In this section, the model is the same 12-layer PCB mentioned above. The VIA radius is kept constant and the back-drill length is kept at 35 mil, while the radius of the anti-pads is gradually increased from 13 mil to 17 mil. The numerical results of our 3D full-wave simulations are shown in Figure 5 and Figure 6.

As can be seen from the above two graphs, the insertion loss gradually decreases as the anti-pad radius increases from 13 mil to 15 mil; however, when the frequency is in the range of 0 G–17 G, the return loss is higher with an anti-pad radius of 16 mil or 17 mil. This is mainly due to the effect of resonance. The resonant frequencies at this point are mainly 11 GHz and 18 GHz. In addition, the insertion loss curves in Figure 4 and Figure 6 are relatively smooth, indicating that there is no effect from resonance. However, as can be seen from Figure 6, the insertion loss gradually decreases as the radius of the anti-pad gradually increases from 13 mil to 17 mil. Therefore, while the anti-pad radius can be increased to a certain extent in high-speed PCB design, it is not possible to increase the radius of the anti-pads without limit, and the value should be analyzed concretely.

3.3. Optimization and Verification

Although there have been many studies on VIAs [8,9,24,30,33,34], at present there are no studies explaining whether anti-pads should be added to the back-drills. Based on the research of other scholars and engineers, this paper puts forward a new optimization scheme for the S-parameter at differential VIAs. Specifically, in the design of high-speed PCBs, the anti-pads are added to the back-drill of the differential VIAs. In addition, this paper presents a modeling study on the effect of adding different layers of anti-pads at the back-drills. The details of the proposed optimization scheme are shown in Figure 7; the left half of Figure 7 shows the design scheme commonly used by engineers at present, while the right half shows the new optimization scheme proposed in this paper. The stacked structure of the 12-layer circuit board designed in this paper and its functions are shown in

Table 2. Specifications of each layer function.

Plane	Type
Layer 1/12	Signal Plane
Layer 2/11	Power Plane
Layer 3/10	Signal Plane
Layer 4/9	Power Plane
Layer 5/8	Signal Plane
Layer 6/7	Power Plane

.

Moreover, the parameters (stub length and anti-pad radius) of the modeled differential VIAs are taken when the S-parameters are optimal, as verified in Section 3.1 and Section 3.2.

In this paper, after back-drilling the differential VIAs, the anti-pads are designed in the back-drilled part. The results are compared with no anti-pads at back-drilled part and anti-pads placed at different layers of the back-drilled part. The results are shown in Figure 8 and Figure 9.

It can be seen from Figure 8 and Figure 9 that when one layer of anti-pads is added to the reference layer closest to the signal outflow layer, the S-parameter curves coincide with each other when anti-pads are added to two layers or three layers. The insertion loss effect is the worst when the reference layers passed by the back-drill do not have added anti-pads. The effect is best when anti-pads are added to all reference layers passed by the back-drill. Under this situation, the insertion loss is increased from 0.7 dB to 0.25 dB at frequencies up to 30 GHz, and with the return loss optimized from about 10 dB to about 17 dB. At about 4 GHz–7 GHz there is a slight effect from resonance, resulting in the case of adding all possible anti-pads being slightly worse than the case of adding one, two, or three layers of anti-pads, although there is still a significant optimization effect compared with no anti-pads.

In another aspect, the new scheme proposed in this paper has a better optimization effect on S-parameter than Scheme 1 or Scheme 2. On the one hand, the return loss for the scheme proposed in this paper is 3.20 dB higher than Scheme 1 and 3.54 dB higher than Scheme 2; on the other hand, in terms of the insertion loss, the new scheme shows improvements of 0.01 dB compared with Scheme 1 and 0.028 dB compared with Scheme 2 at frequencies up to 25 GHz. Therefore, from the two aspects of insertion loss and return loss, the optimization scheme proposed in this paper is better than the other two schemes.

In addition, as mentioned in Section 2, resonance causes signal loss and affects the S-parameter curves. By comparing Figure 8 with Figure 3 and Figure 5, it can be seen that the optimization scheme proposed in this paper effectively reduces the influence of resonance on the return loss when the frequencies are around 11GHz and 13GHz, and the return loss curves become smoother.

Figure 10 and Figure 11 are the eye diagrams obtained by joint simulation in Advanced Design System (ADS) with and without anti-pads in the back-drilled part. Figure 10 shows the eye diagram in the case of the back-drilled part without anti-pads, while Figure 11 shows the eye diagram in the case of adding anti-pads to the back-drilled part. A comparison between Figure 10 and Figure 11 shows that the eyelid thickness of the eye diagram is significantly reduced after adding the anti-pads to the back-drilled part, indicating that the interference of the differential VIA part is significantly reduced after adding the anti-pads to the back-drilled part. In addition, both the eye duty cycle and the eye crossing ratio of the eye diagram are reduced, and the eye diagram shape is close to ideal except for a slight double eyelid.

In summary, when the signal transmission rate is high, after back-drilling the differential VIAs which the signal has passed, anti-pads can be added to the reference layers passed by the back-drill. This can not only reduce the transmission loss but also reduce the noise interference to a certain extent.

4. Conclusions

This paper proposes a novel optimization scheme for adding anti-pads to the layers passed by the back-drill of differential VIAs. The proposed optimization scheme has been verified using 3D full-wave numerical simulations and compared with other optimization methods, including different anti-pad radius values and different VIA stub lengths. Notably, the proposed optimization scheme involving adding anti-pads in the back-drilled part has a better optimization effect on the S-parameter compared with similar previous achievements. Our new scheme improves the return loss by about 3 dB at a frequency of 30 GHz. At 25 GHz, the insertion loss is increased by about 0.03 dB. In addition, this scheme can not only improve the optimization of insertion loss and return loss but also reduce the influence of resonance on the S-parameter curves. More importantly, adding anti-pads to the reference layers passed by the back-drill does not occupy the wiring space of the PCBs, and is more in line with the development trend towards high integration of high-speed PCBs. Moreover, this scheme is simple, has good feasibility, and can provide a reliable signal optimization scheme for engineers engaged in circuit board design.