Analysis of the Second-Order NS SAR ADC Performance Enhancement Based on Active Gain

Abstract

This paper presents a novel second-order passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) based on active gain. The proposed scheme achieves a further improvement in the signal-to-noise ratio (SNR) of the proposed NS SAR ADC by reducing the kT/C noise and the conversion rate. After having presented the conversion principle, the theoretical analysis of the performance enhancement based on noise and other considerations is presented.

1. Introduction

The successive approximation register (SAR) analog-to-digital converter (ADC) is one of the most widely used ADC architectures. It offers medium resolution and is simple to design [1,2,3,4]. However, for high-resolution applications, its power efficiency degrades due to stringent requirements on the comparator noise and the exponentially growing capacitor digital-to-analog converter (DAC) array. The noise shaping (NS) SAR ADC is an emerging hybrid ADC architecture that combines the advantages of SAR and Sigma–Delta ADCs [5,6,7,8]. The NS SAR ADC significantly reduces in-band comparator noise and quantization noise without degrading power efficiency [9,10]. Comparator noise is a critical factor in signal-to-noise ratio (SNR). Due to the simple structure and lower power consumption of dynamic comparators, they are more widely used in SAR ADCs than the static comparator. However, the input referred noise of dynamic comparators is larger than static comparators because of its low gain. Although the comparator noise is shaped in NS SAR ADC, it remains too large for high-resolution systems. Several methods have been proposed to minimize it. The SNR and spurious free dynamic range (SFDR) enhancement technique is proposed [11,12,13], repeating comparison of least significant bit (LSB) by using redundant DAC to average comparator noise. To effectively reduce the comparator noise and increase its lower-bits decision accuracy, the majority voting (MV) technique is proposed [14,15], and a tri-level voting technique is employed [16]. However, these techniques come at the expense of a lower sampling rate.

Although NS SAR ADCs can also reduce the number of quantizer bits, the kT/C noise decreases as the capacitance increases. Therefore, increasing the capacitor array is essential for high-resolution applications. There are three drawbacks associated with a large capacitance. The first, a large capacitance means a large area, which burdens the whole chip. Second, a larger capacitance consumes more dynamic power. Third, a large sampling capacitance also increases the power consumption of the input buffer. Therefore, increasing the capacitance may not be an effective way to reduce the kT/C noise. To overcome the limitations of the large capacitance and the input-referred noise of the dynamic comparator, this paper proposes a second-order NS SAR ADC based on active gain. The proposed method achieves a further improvement in the SNR of NS SAR ADC and sampling speed while using the smaller capacitance. This paper provides a mathematical analysis of the noise and non-ideal factors demonstrating the effectiveness of the proposed scheme.

This paper is organized as follows. Section 2 presents a mathematical analysis of previous second-order fully-passive NS SAR ADC architecture. Section 3 discusses the two schemes of proposed second-order NS SAR ADC based on active gain. Section 4 compares the advantages and disadvantages of the proposed schemes. Section 5 concludes this paper.

2. Mathematical Analysis of Previous Second-Order Fully-Passive NS SAR ADC

Some prior works utilized operational transconductance amplifiers (OTA) to construct active filters, which can achieve good NS effect [9]. However, OTA consumes high power and is scaling-unfriendly. In recent years, methods utilizing switches and capacitors to implement fully passive filters have been proposed [17,18]. These passive switched capacitor filters are simple, low power, robust, and scaling-friendly. The previous second-order fully-passive NS SAR ADC work is shown in Figure 1 [16]. According to the signal flow diagram shown in Figure 1, V_int1 and V_int2 can be obtained:

$${\mathrm{V}}_{\mathrm{i}\mathrm{n}\mathrm{t}1}(\mathrm{z})=(1-a){\displaystyle \frac{a}{1-(1-a){\mathrm{z}}^{-1}}}{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{s}}(\mathrm{z})$$

(1)

and

$${\mathrm{V}}_{\mathrm{i}\mathrm{n}\mathrm{t}2}\left(\mathrm{z}\right)={\displaystyle \frac{a}{1-\left(1-a\right){\mathrm{z}}^{-1}}}{\mathrm{V}}_{\mathrm{i}\mathrm{n}\mathrm{t}1}\left(\mathrm{z}\right)=(1-a){\displaystyle \frac{a^2}{{[1-\left(1-a\right){\mathrm{z}}^{-1}]}^2}}{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{s}}(\mathrm{z})$$

(2)

where the residual voltage is V_res(z) = V_in(z) − D_OUT(z).

The relationship between input and output can be expressed as:

$${\mathrm{D}}_{\mathrm{O}\mathrm{U}\mathrm{T}}\left(\mathrm{z}\right)={\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\mathrm{z}\right)+g_1{\mathrm{z}}^{-1}{\mathrm{V}}_{\mathrm{i}\mathrm{n}\mathrm{t}1}\left(\mathrm{z}\right)+g_2{\mathrm{z}}^{-1}{\mathrm{V}}_{\mathrm{i}\mathrm{n}\mathrm{t}2}\left(\mathrm{z}\right)+\mathrm{Q}\left(\mathrm{z}\right)$$

(3)

where Q(z) is quantization noise. By substituting (1) and (2) into (3), the z-domain transfer function with only quantization noise of the previous NS SAR ADC can be calculated as follows:

$${\mathrm{D}}_{\mathrm{O}\mathrm{U}\mathrm{T}}\left(\mathrm{z}\right)={\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\mathrm{z}\right)+{\displaystyle \frac{{[1-\left(1-a\right){\mathrm{z}}^{-1}]}^2}{1+\left(1-a\right)\left(g_2{a}^2+g_{1}a-2\right){\mathrm{z}}^{-1}+{\left(1-a\right)}^2(1-g_{1}a){\mathrm{z}}^{-2}}}\mathrm{Q}(\mathrm{z})$$

(4)

The typical values of a, g₁, g₂, and oversampling ratio (OSR) in Figure 1 are 1/4, 4, 16, 16, respectively. The parameter a is robust against process–voltage–temperature (PVT) variations and mismatches because it depends on the ratio of the capacitance. The parameters g₁ and g₂ represent the strengths of different input pairs of the comparator, and they are insensitive to PVT variations and mismatches. However, the variations of g₁ and g₂ with PVT do not affect the stability of the structure, which has been analyzed in detail [16].

The parameters a, g₁, and g₂ may be affected by PVT variations and mismatches during the manufacturing process. However, a, g₁, and g₂ are regarded as constant in the following analysis because PVT variations and mismatches are ignored. Therefore, the z-domain transfer function including only quantization noise can be simplified as follows:

$${\mathrm{D}}_{\mathrm{O}\mathrm{U}\mathrm{T}}\left(\mathrm{z}\right)={\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\mathrm{z}\right)+{[1-{\displaystyle \frac{3}{4}}{\mathrm{z}}^{-1}]}^2\mathrm{Q}(\mathrm{z})$$

(5)

The z-domain transfer function including quantization noise and other noise is shown in Figure 1b. The signal transfer function (STF) is given by STF = 1, indicating that there is no energy loss in the signal power. For different noise sources, the noise transfer functions (NTFs) are different. The quantization noise transfer function is given by (1 − 0.75 z⁻¹)². The noise power ${\mathrm{n}}_1^2$ − ${\mathrm{n}}_6^2$ are kT/C, (1 − a)kT/aC = 3 kT/C, (1 − a)²kT/aC = 2.25 kT/C, akT/C = 0.25 kT/C, (1 − a)²kT/aC = 2.25 kT/C, and akT/C = 0.25 kT/C, where k is the Boltzmann constant. Their in-band noise power will be calculated separately. In order to estimate the in-band power of the quantization noise, it is useful to find the magnitude of the quantization noise transfer function in the frequency domain by setting z = e^j2πf. For frequencies that satisfy f ≪ 1, |NTF(e^j2πf)| ≈ 1/16 + 3(πf)². The in-band power of the quantization noise, P_{Q_ib}, can be calculated as:

$$\begin{array}{c}{\mathrm{P}}_{\mathrm{Q}\_\mathrm{i}\mathrm{b}}=2{\int }_0^{{\displaystyle \frac{1}{2\mathrm{O}\mathrm{S}\mathrm{R}}}}{\left|{\left(1-{\displaystyle \frac{3}{4}}{z}^{-1}\right)}^2\right|}^2{\mathrm{P}}_{\mathrm{Q}}\mathrm{d}\mathrm{f}\\ \approx 2{\int }_0^{{\displaystyle \frac{1}{2\mathrm{O}\mathrm{S}\mathrm{R}}}}{\left({\displaystyle \frac{1}{16}}+3{\left(\mathsf{\pi }\mathrm{f}\right)}^2\right)}^2{\mathrm{P}}_{\mathrm{Q}}\mathrm{d}\mathrm{f} \\ \approx \left({\displaystyle \frac{1}{256}}+{\displaystyle \frac{{\mathsf{\pi }}^2}{32}}{\displaystyle \frac{1}{{\mathrm{O}\mathrm{S}\mathrm{R}}^2}}+{\displaystyle \frac{3.6{\mathsf{\pi }}^4}{32}}{\displaystyle \frac{1}{{\mathrm{O}\mathrm{S}\mathrm{R}}^4}}\right){\displaystyle \frac{{\mathrm{P}}_{\mathrm{Q}}}{\mathrm{O}\mathrm{S}\mathrm{R}}}\end{array}$$

(6)

where P_Q is the quantization noise power of the SAR ADC without NS. Ignoring considering other noises, the improved ideal effective number of bits (ENOBs), denoted as ENOB_imp, can be expressed as the following expression.

$${\mathrm{E}\mathrm{N}\mathrm{O}\mathrm{B}}_{\mathrm{i}\mathrm{m}\mathrm{p}}={\displaystyle \frac{-10\mathrm{l}\mathrm{o}\mathrm{g}(\frac{1}{256}\frac{1}{\mathrm{O}\mathrm{S}\mathrm{R}}+\frac{{\mathsf{\pi }}^2}{32}\frac{1}{{\mathrm{O}\mathrm{S}\mathrm{R}}^3}+\frac{3.6{\mathsf{\pi }}^4}{32}\frac{1}{{\mathrm{O}\mathrm{S}\mathrm{R}}^5})}{6.02}}$$

(7)

When the OSR is set to 16, ENOB_imp ≈ 5.76 can be obtained. Oversampling can reduce the in-band noise power by OSR times. By observing (6), it can be found that NS suppresses the low-frequency quantization noise power by approximately a factor of 256. Similar to quantization noise, comparator input-referred noise and DAC noise are also affected by the passive second-order NS.

Using similar calculations, the in-band noise powers of different noise sources can be obtained separately. The in-band noise power ${\mathrm{n}}_{1\_\mathrm{i}\mathrm{b}}^2$ − ${\mathrm{n}}_{6\_\mathrm{i}\mathrm{b}}^2$ are approximately ${\mathrm{n}}_1^2$/OSR, [0.1 + π²/(32OSR²)]${\mathrm{n}}_2^2$/OSR, [1.56 + π²/(2OSR²)]${\mathrm{n}}_3^2$/OSR, 16${\mathrm{n}}_4^2$/OSR, [1 + 4π²/OSR²] ${\mathrm{n}}_5^2$/OSR, [16 + 64π²/OSR²]${\mathrm{n}}_6^2$/OSR. It is obvious that the structure’s NS ability for different noises is not the same. If the noise is unaffected by NS, the noise power becomes 1/OSR times the original after oversampling. Since ${\mathrm{n}}_{2\_\mathrm{i}\mathrm{b}}^2$ is smaller than ${\mathrm{n}}_2^2$/OSR, the noise n₂ is shaped to contribute less noise. By examining ${\mathrm{n}}_{1\_\mathrm{i}\mathrm{b}}^2$ − ${\mathrm{n}}_{6\_\mathrm{i}\mathrm{b}}^2$, it is clear that only the in-band noise powers of C_res reset noise n₂, comparator input referred noise n₇ and DAC noise n₈ are suppressed by NS, and DAC sampling noise n₁ is not affected by NS. However, the in-band noise powers of n₃ − n₆ are enlarged by NS. Since n₁ − n₆ and n₈ are all kT/C noise and only n₈ is second-order shaped, n₁ − n₆ are the primary contributors of the kT/C noise.

The kT/C noise and comparator input-referred noise n₇ are the main two noise sources by mathematical analysis of previous second-order fully-passive NS SAR ADC. NS effectively suppresses the low-frequency comparator input-referred noise power, reducing it by approximately a factor of 256. In this structure, the comparator input-referred noise is suppressed by the second-order NS. However, NS achieves limited suppression of low-frequency C_res reset noise power, reducing it by about a factor of 10, while the in-band noise powers of n₃ − n₆ are enlarged by NS. In order to effectively reduce the kT/C noise, the capacitance must be large enough for high-resolution applications. To address this issue, the second-order NS SAR ADC based on active gain is proposed.

3. The Proposed Second-Order NS SAR ADC

In order to reduce the kT/C noise, an open-loop amplifier is used in the proposed second-order NS SAR ADC based on active gain. However, it can decrease the kT/C noise, except the DAC sampling noise. On the basis of second-order NS SAR ADC based on active gain, the improved second-order NS SAR ADC based on active gain is proposed to suppress the DAC sampling noise. Key parameters related to the amplifier need to be designed and selected reasonably for optimum noise performance. Finally, the speed issue and kickback noise issue of the proposed structures are analyzed.

3.1. The Second-Order NS SAR ADC Based on Active Gain

The schematic and signal flow diagram of SAR ADC are shown in Figure 2a [19]. Based on the signal flow diagram, the z-domain transfer function including only quantization noise is D_out(z) = V_in(z) + Q(z). The quantization noise Q(z) can be obtained.

$$\mathrm{Q}\left(\mathrm{z}\right)={\mathrm{D}}_{\mathrm{o}\mathrm{u}\mathrm{t}}\left(\mathrm{z}\right)-{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\mathrm{z}\right)$$

(8)

The schematic and equivalent signal flow diagram of SAR ADC based on active gain are shown in Figure 2b. An open-loop amplifier is integrated between the DAC capacitor array and the comparator. The DC gain of the open-loop amplifier is A. Based on the equivalent signal flow diagram, the quantization noise Q_A(z) can be obtained.

$${\mathrm{Q}}_{\mathrm{A}}\left(\mathrm{z}\right)=A\left({\mathrm{D}}_{\mathrm{o}\mathrm{u}\mathrm{t}}\left(\mathrm{z}\right)-{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\mathrm{z}\right)\right)=A\mathrm{Q}\left(\mathrm{z}\right)$$

(9)

Therefore, the z-domain transfer function including only quantization noise of SAR ADC based on active gain is:

$${\mathrm{D}}_{\mathrm{o}\mathrm{u}\mathrm{t}}\left(\mathrm{z}\right)={\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\mathrm{z}\right)+\mathrm{Q}\left(\mathrm{z}\right)$$

(10)

This result is the same as the transfer function of the SAR ADC, indicating that the addition of the amplifier does nothing to quantization noise. To assess the impact on other noises, the DAC sampling noise and the comparator input referred noise are added to the signal flow diagram shown in Figure 3. Since the DAC capacitor array and comparators in Figure 2a,b are identical, the DAC sampling noise n₁(z) and the comparator input referred noises n₇(z) remain consistent in both Figure 3a,b.

According to the signal flow diagram shown in Figure 3a, the z-domain transfer function with the DAC sampling noise and comparator input referred noise of SAR ADC is:

$${\mathrm{D}}_{\mathrm{o}\mathrm{u}\mathrm{t}}\left(\mathrm{z}\right)={\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\mathrm{z}\right)+\mathrm{Q}\left(\mathrm{z}\right)+{\mathrm{n}}_1\left(\mathrm{z}\right)+{\mathrm{n}}_7\left(\mathrm{z}\right)$$

(11)

However, the z-domain transfer function with the DAC sampling noise and comparator input referred noise of SAR ADC based on active gain can be obtained based on the signal flow diagram shown in Figure 3b.

$${\mathrm{D}}_{\mathrm{o}\mathrm{u}\mathrm{t}}\left(\mathrm{z}\right)={\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\mathrm{z}\right)+\mathrm{Q}\left(\mathrm{z}\right)+{\mathrm{n}}_1\left(\mathrm{z}\right)+{\displaystyle \frac{{\mathrm{n}}_7\left(\mathrm{z}\right)}{A}}$$

(12)

By comparing (11) and (12), It can be found that the amplifier suppresses the comparator input referred noise but not DAC sampling noise. Therefore, using the amplifier can suppress a portion of the noises, such as comparator input-referred noise, but has no influence on quantization noise and DAC sampling noise.

To mitigate the disadvantages of large capacitors, the scheme of the second-order NS SAR ADC based on active gain is proposed, as illustrated in Figure 4a. Compared to the second-order fully-passive NS SAR ADC, this scheme incorporates three additional components, which include an open-loop amplifier, a cancellation capacitor C_nc, and a sampling switch S₂. C_nc must satisfy C_nc:C_res:C_int1:C_int2 = 3:1:3:3. A represents the DC gain of the open-loop amplifier. At the end of the sampling phase, the sampling switches S₁ and S₂ are switched off simultaneously. Hence, the offset voltage V_osamp of the amplifier can be stored on the cancellation capacitor C_nc. During the conversion phase, the final residual voltage of the DAC array is amplified by a factor of A, which decreases the effect of noise n₂ − n₇ and n₉ on circuit performance.

In Figure 4, the residual voltage is V_res(z) = A (V_in(z) − D_OUT(z)). The output voltage of the amplifier can be thought of as V_res because the voltage stored on C_nc does not change during the SAR conversion. When φ_out becomes high, V_res is sampled by C_res, and the voltage on C_res is (1 − a) V_res(z). When φ_ns1 and φ_ns2 go high, the same expressions for V_int1 and V_int2 are obtained as those in the second-order fully-passive NS SAR. Therefore, (1) and (2) can be also obtained.

Using the signal flow diagram in Figure 4b, (13) can be obtained.

$${\mathrm{A}\mathrm{D}}_{\mathrm{O}\mathrm{U}\mathrm{T}}\left(\mathrm{z}\right)=A{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\mathrm{z}\right)+g_1{\mathrm{z}}^{-1}{\mathrm{V}}_{\mathrm{i}\mathrm{n}\mathrm{t}1}\left(\mathrm{z}\right)++g_2{\mathrm{z}}^{-1}{\mathrm{V}}_{\mathrm{i}\mathrm{n}\mathrm{t}2}\left(\mathrm{z}\right)+A\mathrm{Q}\left(\mathrm{z}\right)$$

(13)

(1) and (2) are substituted into (13), and the z-domain transfer function with only quantization noise of the proposed NS SAR ADC can be calculated without considering the PVT variations and mismatches of a, g₁, and g₂.

$${\mathrm{D}}_{\mathrm{O}\mathrm{U}\mathrm{T}}\left(\mathrm{z}\right)={\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\mathrm{z}\right)+{\left(1-0.75{\mathrm{z}}^{-1}\right)}^2\mathrm{Q}\left(\mathrm{z}\right)$$

(14)

The comparison of (14) and (5) demonstrates that using the amplifier has no effect on quantization noise. In order to accurately describe the noise suppression advantages of the proposed scheme for other noises, the signal flow diagram and complete z-domain transfer function with all noises of the proposed NS SAR ADC are shown in Figure 4b. The STF is still 1, and the noise transfer function has been changed. The magnitude of the noise n₂ − n₇ and n₉ is attenuated by the open-loop amplifier gain A, and the power of the noise n₂− n₇ and n₉ is attenuated by A². The noise n₂ − n₇ and n₉ is related to the capacitors C_nc, C_res, C_int1, and C_int2. Therefore, the active amplifier can be used to greatly reduce the capacitance of the capacitors C_nc, C_res, C_int1, and C_int2. Both n₉ and AMP input-referred noise n₁₀ are new noise sources. The power of C_nc sampling noise n₉ is kT/C. The structure of the amplifier [20] shown in Figure 4a can be employed in the proposed NS SAR ADC. The single-end input-referred noise power spectrum density (PSD) of a CMOS-input preamp is:

$${\displaystyle \frac{\overline{{\mathrm{n}}_{10}^2}}{\Delta \mathrm{f}}}={\displaystyle \frac{4\mathrm{k}\mathrm{T}\mathsf{\gamma }}{{\mathrm{G}}_{\mathrm{m}}}}$$

(15)

where the theoretical value of γ is 2/3 for long-channel devices and G_m is the transconductance of the open-loop amplifier. The noise bandwidth of the open-loop amplifier during the sampling phase is about 1/4R_outC_nc. R_out = A/G_m is the output resistance of the open-loop amplifier. Thus, the power of AMP input referred noise n₁₀ can be calculated as:

$$\overline{{\mathrm{n}}_{10}^2}={\displaystyle \frac{4\mathrm{k}\mathrm{T}\mathsf{\gamma }}{{\mathrm{G}}_{\mathrm{m}}}}\times {\displaystyle \frac{1}{4{\mathrm{R}}_{\mathrm{o}\mathrm{u}\mathrm{t}}{\mathrm{C}}_{\mathrm{n}\mathrm{c}}}}={\displaystyle \frac{\mathrm{k}\mathrm{T}\mathsf{\gamma }}{A\mathrm{C}}}$$

(16)

It can be seen that the AMP input-referred noise power is inversely proportional to the amplifier gain A from (16). Only the noises n₁ and n₈ are not suppressed by A. The noise n₁ directly affects the output signal and is not second-order-shaped like n₈. Therefore, n₁ becomes the main kT/C noise source.

3.2. Improved Second-Order NS SAR ADC Based on Active Gain

To alleviate the deterioration of the output signal by noise n₁, the improved second-order NS SAR ADC based on active gain is proposed, shown in Figure 5. The kT/C noise cancellation principle proposed by [21,22] is employed. There is a change in the timings compared to Figure 4a. φ_s is split into φ_sDAC and φ_snc, controlling switches S₁ and S₂, respectively.

The kT/C noise cancellation principle is shown in Figure 6. The sampling phase is divided into the C_DAC sampling phase and the C_nc sampling phase. The C_DAC sampling phase lasts from t₀ to t₁ controlled by φ_sDAC. At the moment t₁, the sampled input signal V_in(t₁) and kT/C noise n₁ are stored on C_DAC. The offset voltage V_osamp of the amplifier is stored on the C_nc, as in Figure 4a. The C_nc sampling phase operates from t₁ to t₂ controlled by φ_snc. At t₂, the input signal is V_in(t₂), and the input voltage of the amplifier is V_in(t₂) − V_in(t₁) − n₁ − V_osamp. Assuming the amplifier has infinite bandwidth, it fully settles during the C_nc sampling phase. The voltage stored on C_nc is:

$${\mathrm{V}}_{{\mathrm{C}}_{\mathrm{n}\mathrm{c}}}=A[{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left({\mathrm{t}}_2\right)-{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left({\mathrm{t}}_1\right)-{\mathrm{n}}_1-{\mathrm{V}}_{\mathrm{o}\mathrm{s}\mathrm{a}\mathrm{m}\mathrm{p}}]$$

(17)

Neglecting capacitances C_int1, C_int2, and C_res, the input–output relation can be computed as (18) at the end of the conversion phase.

$${\mathrm{D}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left({\mathrm{t}}_2\right)+{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{s}}/A\approx {\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left({\mathrm{t}}_2\right)$$

(18)

By observing (18), it can be seen that the sampling noise n₁ can be completely canceled if the amplifier has an infinite bandwidth. In fact, the bandwidth of the amplifier is limited. Therefore, the sampling noise voltage stored on C_nc is:

$${\mathrm{n}}_1\_{\mathrm{C}}_{\mathrm{n}\mathrm{c}}=-A{\mathrm{n}}_1(1-{\mathrm{e}}^{-\Delta \mathrm{t}/\mathsf{\tau }})$$

(19)

where τ is the settling time constant of the amplifier [23] and the time interval satisfies Δt = t₂ − t₁. The voltage stored on C_nc is A[V_in(t₂) − V_in(t₁) − n₁(1 − e^−Δt/τ) − V_osamp]. The new input–output relationship can be computed as:

$${\mathrm{D}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left({\mathrm{t}}_2\right)+{\mathrm{n}}_1{\mathrm{e}}^{-\Delta \mathrm{t}/\mathsf{\tau }}$$

(20)

From the above analysis, it can be concluded that kT/C noise cancellation allows the sampling noise power to be attenuated by e^2Δt/τ. As a result, the z-domain transfer function of the improved second-order NS SAR ADC scheme can be expressed as follows:

$$\begin{array}{c}{\mathrm{D}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\mathrm{z}\right)+{\mathrm{n}}_1{\mathrm{e}}^{-{\displaystyle \frac{\Delta \mathrm{t}}{\mathsf{\tau }}}}\left(\mathrm{z}\right)+{\mathrm{n}}_{10}\left(\mathrm{z}\right)+{\displaystyle \frac{{\mathrm{n}}_9\left(\mathrm{z}\right)}{A}}+{\displaystyle \frac{{\mathrm{n}}_4\left(\mathrm{z}\right){\mathrm{z}}^{-1}}{Aa}}\\ +\left({\displaystyle \frac{a{\mathrm{n}}_2\left(\mathrm{z}\right){\mathrm{z}}^{-1}}{A}}+{\displaystyle \frac{{\mathrm{n}}_3\left(\mathrm{z}\right){\mathrm{z}}^{-1}}{A}}\right)\left(2-0.75{\mathrm{z}}^{-1}\right) \\ +\left({\displaystyle \frac{{\mathrm{n}}_5\left(\mathrm{z}\right){\mathrm{z}}^{-1}}{Aa}}+{\displaystyle \frac{{\mathrm{n}}_6\left(\mathrm{z}\right){\mathrm{z}}^{-1}}{A{a}^2}}\right)\left(1-0.75{\mathrm{z}}^{-1}\right) \\ +\left(\mathrm{Q}\left(\mathrm{z}\right)+{\displaystyle \frac{{\mathrm{V}}_{\mathrm{O}\mathrm{S}}}{A}}+{\displaystyle \frac{{\mathrm{n}}_7\left(\mathrm{z}\right)}{A}}+{\mathrm{n}}_8\left(\mathrm{z}\right)\right){\left(1-0.75{\mathrm{z}}^{-1}\right)}^2 \\ +\epsilon \left(\mathrm{z}\right) \end{array}$$

(21)

It is possible to achieve a reduction in the overall capacitance in the improved second-order NS SAR ADC by designing the values of A and Δt/τ in a rational way. This makes it possible to use the structure in high-resolution applications where large-area capacitors are not applicable.

3.3. The Values of A and Δt/τ

The selection of A and Δt/τ is crucial for the attenuation of kT/C noise and the performance of the proposed scheme. If the gain A is too large, it can easily lead to saturation of the open-loop amplifier. On the contrary, if the gain A is too small, noises n₂ − n₇ and n₉ − n₁₀ cannot be sufficiently suppressed, resulting in little performance improvement. Therefore, the value of A must be reasonable. To ensure that the open-loop amplifier accurately amplifies the residual voltage of the DAC array generating V_res, it is necessary to ensure that (22) is satisfied.

$$A\left[{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left({\mathrm{t}}_2\right)-{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left({\mathrm{t}}_1\right)-{\mathrm{n}}_1-{\mathrm{V}}_{\mathrm{o}\mathrm{s}\mathrm{a}\mathrm{m}\mathrm{p}}\right]+A{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{s}\_\mathrm{D}\mathrm{A}\mathrm{C}}<{\displaystyle \frac{\mathrm{A}\mathrm{V}\mathrm{D}\mathrm{D}}{2}}-{\mathrm{V}}_{\mathrm{d}\mathrm{s}\mathrm{a}\mathrm{t}}$$

(22)

where V_{res_DAC} is the residual voltage of the DAC array, AVDD is the power supply voltage, and V_dsat is the saturation drain voltage. In order for the amplifier to quickly remain stable in the amplification region at the end of the conversion, V_{res_DAC} is taken to be at least 4LSB instead of LSB (LSB = (V_refp − V_refn)/2^N). The maximum amount of change in the input signal during the time interval Δt is:

$${\left|{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left({\mathrm{t}}_2\right)-{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left({\mathrm{t}}_1\right)\right|}_{\mathrm{m}\mathrm{a}\mathrm{x}}\approx {\left|{\mathrm{s}\mathrm{i}\mathrm{n}}^{’}\left(2\mathsf{\pi }{\mathrm{f}}_{\mathrm{i}\mathrm{n}\mathrm{m}\mathrm{a}\mathrm{x}}\mathrm{t}\right)\right|}_{\mathrm{m}\mathrm{a}\mathrm{x}}\times \Delta \mathrm{t}=2\mathsf{\pi }{\mathrm{f}}_{\mathrm{i}\mathrm{n}\mathrm{m}\mathrm{a}\mathrm{x}}\times \Delta \mathrm{t}=\mathsf{\pi }{\mathrm{f}}_{\mathrm{s}\mathrm{a}\mathrm{m}}\times \Delta \mathrm{t}/\mathrm{O}\mathrm{S}\mathrm{R}$$

(23)

where f_inmax is the maximum frequency of the input signal, f_sam is the sampling frequency, and f_inmax = f_sam/2OSR. n₁ is the DAC sampling noise voltage with a noise power of kT/C_DAC. Thus, the distribution of n₁ is N (0, √kT/C_DAC). The maximum value of n₁ can be considered:

$${\left|{\mathrm{n}}_1\right|}_{\mathrm{m}\mathrm{a}\mathrm{x}}=5\sqrt{\mathrm{k}\mathrm{T}/{\mathrm{C}}_{\mathrm{D}\mathrm{A}\mathrm{C}}}$$

(24)

The maximum gain can be calculated as follows:

$${\mathrm{A}}_{\mathrm{m}\mathrm{a}\mathrm{x}}={\displaystyle \frac{\frac{\mathrm{A}\mathrm{V}\mathrm{D}\mathrm{D}}{2}-{\mathrm{V}}_{\mathrm{d}\mathrm{s}\mathrm{a}\mathrm{t}}}{\frac{\mathsf{\pi }{\mathrm{f}}_{\mathrm{s}\mathrm{a}\mathrm{m}}}{\mathrm{O}\mathrm{S}\mathrm{R}}\times \Delta \mathrm{t}+5\sqrt{\frac{\mathrm{k}\mathrm{T}}{{\mathrm{C}}_{\mathrm{D}\mathrm{A}\mathrm{C}}}}+{\left|{\mathrm{V}}_{\mathrm{o}\mathrm{s}\mathrm{a}\mathrm{m}\mathrm{p}}\right|}_{\mathrm{m}\mathrm{a}\mathrm{x}}+4\mathrm{L}\mathrm{S}\mathrm{B}}}$$

(25)

In order to minimize sampling noise without increasing the array of sampling capacitors C_DAC, the value of Δt/τ needs to be as large as possible. However, it is clear that an increase in Δt leads to a decrease in A and sampling speed. Reducing τ will increase power consumption and improve sampling speed. Therefore, the value of Δt/τ cannot be too large. This requires a compromise between noise performance, power consumption, and speed.

3.4. Improved Sampling Speed

The structure of the three-path dynamic strong-arm comparator can be used in the proposed improved second-order NS SAR ADC scheme shown in Figure 7. The widths of the three input pairs are W, 4 W, and 16 W. Compared to a classic one-path comparator, which has the same total input pair width of 21 W, the noise referred to the 1× path of the three-path comparator is 21 times larger but it is attenuated by 16 times due to NS. As a result, the in-band noise of the three-path comparator is 21/16 times larger than that of the one-path comparator. Therefore, the noise of the three-path comparator is still relatively large for high-resolution applications. In a word, the second-order fully-passive NS SAR ADC, which mainly reduces the quantization noise from (5), does not bring any benefits to the comparator noise. To improve the SNR, reducing the comparator noise is necessary. For example, the NS SAR [14] performs a single comparison for the first 9 bits (including 1 redundant bit) and only performs repeated comparisons for the LSB bit, which reduces the sampling rate by almost half. However, the technique proposed in this paper not only reduces the kT/C noise but also reduces the comparator noise n₇ from (21). The proposed technique has no extra cycles to average the comparator noise but increases the power consumption of an amplifier. A compromise between power consumption and speed is needed for the designer.

3.5. Kickback Noise

A three-path dynamic strong-arm comparator is shown in Figure 7. This is a strong-arm latch with three input pairs. The summation of the input voltage is realized by merging the currents of input pairs, which are controlled by the input voltage. The summation is controlled by the clock and does not require a static analog adder. However, V_res, V_int1, and V_int2 need a fixed voltage gain ratio of 1:4:16. Because passive integrators do not provide voltage gain, it is best that the comparator provides the voltage gain ratio. Therefore, it is optimal for this comparator to have three input pairs. As a result, the relative gains can be realized by sizing the input pairs of the comparator into specific ratios. Setting the voltage gain ratio by sizing the input pairs is beneficial for PVT variation and mismatch. This does not require the involvement of amplifiers, which reduces the circuit complexity and saves power consumption.

The comparator is reset when φ_c is low. D_n, D_p, V_x, and V_Y are AVDD. When φ_c is high, V_x and V_Y begin to vary, resulting in one of D_n and D_p becoming low. The large voltage variations of V_x and V_Y are coupled through the parasitic capacitances of the input transistors to the input of the comparator. The input voltage will be disturbed, which will worsen the accuracy of the comparator. This disturbance is usually called kickback noise [24]. The kickback noise includes common noise and differential noise. The common kickback noise is coupled through C_GS (assume C_GS1 = C_GS2 = C_GS). The common kickback noise can usually be ignored since it has a common coupling point. The differential kickback noise is related to the difference V_X−Y between V_X and V_Y, as well as the ratio of C_GD to C_int1 using the 4× path as an example. The detailed analysis of V_X−Y is shown in [25]. Assume C_GD1 = C_GD2 = C_GD; the differential kickback noise ε_k can be approximately expressed as:

$${\mathsf{\epsilon }}_{\mathrm{k}}\approx {\displaystyle \frac{{\mathrm{C}}_{\mathrm{G}\mathrm{D}}}{{\mathrm{C}}_{\mathrm{i}\mathrm{n}\mathrm{t}1}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}}}}{\mathrm{V}}_{\mathrm{X}-\mathrm{Y}}\approx {\displaystyle \frac{{\mathrm{C}}_{\mathrm{G}\mathrm{D}}}{{\mathrm{C}}_{\mathrm{i}\mathrm{n}\mathrm{t}1}}}{\mathrm{V}}_{\mathrm{X}-\mathrm{Y}}$$

(26)

Thus, the reduction in capacitance leads to a degradation of the kickback noise. If C_int1 shrinks by a factor of A², the new kickback noise ε_k’ will be approximately A²ε_k. The input referred to as kickback noise is about Aε_k. If the capacitance is too small, the kickback noise will be the dominant noise. The kickback noise needs to be optimized when the capacitance becomes smaller. On the one hand, the size of the input transistors is optimized to reduce the parasitic capacitance C_GD. On the other hand, there is a trade-off between capacitance and kickback noise.

4. Performance Comparison

For the purpose of facilitating comparison, the single-ended second-order fully-passive NS SAR ADC, NS SAR ADC based on gain, and improved NS SAR ADC based on gain are equipped with three-path dynamic strong-arm comparators and only the effect of kT/C thermal noise on SNR is considered. In order to achieve the same SNR, the three different structures require different capacitance sizes. Therefore, N-bit binary weighted DACs (unit capacitance may vary) are used [26]. For the second-order fully-passive NS SAR ADC, the input capacitance is the total capacitance of N-bit binary weighted DAC. Thus, the input capacitance of the second-order fully-passive NS SAR ADC, named C_it, is:

$${\mathrm{C}}_{\mathrm{i}\mathrm{t}}=2^{\mathrm{N}}{\mathrm{C}}_0$$

(27)

where C₀ is the unit capacitance of the second-order fully-passive NS SAR ADC.

The ratio between the input capacitance and the integrating capacitance is C_it:C_res:C_int1:C_int2 = 3:1:3:3, shown in Figure 1a. Hence, the total capacitance of the second-order fully-passive NS SAR ADC, named C_tt, can be obtained.

$${\mathrm{C}}_{\mathrm{t}\mathrm{t}}={\displaystyle \frac{10\times 2^{\mathrm{N}}{\mathrm{C}}_0}{3}}$$

(28)

An open-loop amplifier is introduced in the structure of NS SAR ADC based on active gain. Meanwhile, a cancellation capacitor C_nc is introduced. The structure of NS SAR ADC based on active gain does not adopt the kT/C noise cancellation technique. In order to obtain the same SNR, the minimal input capacitance, named C_{ig_m}, is:

$${\mathrm{C}}_{\mathrm{i}\mathrm{g}\_\mathrm{m}}=2^{\mathrm{N}}{\mathrm{C}}_0$$

(29)

Observing the z-domain transfer function of NS SAR ADC based on active gain, it can be known that the noise powers of n₂ − n₆ and n₉ associated with C_nc, C_res, C_int1, and C_int2 are suppressed by the gain A². Therefore, C_res, C_int1, and C_int2 can all be approximately scaled down by a factor of A² compared to that of the second-order fully-passive NS SAR ADC. The ratio of the integrating capacitances is C_nc:C_res:C_int1:C_int2 = 3:1:3:3. Therefore, the minimal total capacitance of NS SAR ADC based on active gain, named C_{tg_m}, can be approximately expressed.

$${\mathrm{C}}_{\mathrm{t}\mathrm{g}\_\mathrm{m}}\approx 2^{\mathrm{N}}{\mathrm{C}}_0+{\displaystyle \frac{10\times 2^{\mathrm{N}}{\mathrm{C}}_0}{3}}\times {\displaystyle \frac{1}{A^2}}\approx 2^{\mathrm{N}}{\mathrm{C}}_0({\displaystyle \frac{10}{3A^2}}+1)$$

(30)

On the basis of the structure of NS SAR ADC based on active gain, the kT/C noise cancellation technique is introduced into the structure of improved NS SAR ADC based on active gain. It can be found that the DAC sampling noise is suppressed by a factor of e^Δt/τ from (21). In other words, the DAC sampling noise power is suppressed by a factor of e^2Δt/τ. The input capacitance of the structure of improved NS SAR ADC based on active gain can be reduced by a factor of e^2Δt/τ compared to that of the second-order fully-passive NS SAR in order to obtain the same SNR. Therefore, the minimal input capacitance of the structure of improved NS SAR ADC, named C_{iig_m}, is:

$${\mathrm{C}}_{\mathrm{i}\mathrm{i}\mathrm{g}\_\mathrm{m}}\approx {\displaystyle \frac{2^{\mathrm{N}}{\mathrm{C}}_0}{{\mathrm{e}}^{2\Delta \mathrm{t}/\mathsf{\tau }}}}$$

(31)

Therefore, the minimal total capacitance of improved NS SAR ADC based on active gain, named C_{tig_m}, can be approximately expressed as follows:

$${\mathrm{C}}_{\mathrm{t}\mathrm{i}\mathrm{g}\_\mathrm{m}}\approx 2^{\mathrm{N}}{\mathrm{C}}_0({\displaystyle \frac{10}{3A^2}}+{\displaystyle \frac{1}{{\mathrm{e}}^{2\Delta \mathrm{t}/\mathsf{\tau }}}})$$

(32)

In order to compare (27) and (28) and (29)–(32), the expressions all contain C₀, which is the unit capacitance of the second-order fully-passive NS SAR ADC. However, this does not mean that the unit capacitance of NS SAR ADC based on active gain and improved NS SAR ADC based on gain is C₀, and the unit capacitance of NS SAR ADC based on active gain and improved NS SAR ADC based on gain can be reasonably assigned based on the total capacitance and input capacitance.

The minimal C_total and input cap are shown by (27)–(32). However, non-ideal factors will limit the C_total and input cap in the process of circuit implementation, especially the C_total. Taking the kickback noise as an example, if C_int1 is reduced by A² times, the input-referred kickback noise associated with C_int1 will be increased by about A times from (26). If C_int1, C_int2, C_res, and C_nc are all reduced by A² times, the input-referred kickback noise will be increased by about A times. Worsened kickback noise may lead to the deterioration of the SNR. This will limit C_int1 from shrinking by a factor of A², which results in C_total not reaching the minimal C_total. Moreover, the influence of non-ideal factors such as clock feedthrough and charge injection will gradually increase with the decrease in C_total. Therefore, the selection of C_total also needs to consider the influence of non-ideal factors in the circuit implementation. However, even considering non-ideal factors, the C_total of second-order fully-passive NS SAR is large, and the C_total of improved NS SAR ADC base is small when the same SNR is achieved. Compared to the other two structures’ C_total, the C_total of NS SAR based on active gain is medium. The capacitance value reflects the circuit’s ability to suppress kT/C noise. The smaller the capacitance used to achieve the same performance, the better the circuit performance of suppressing kT/C noise. Therefore, capacitance is also an important parameter for SAR ADCs. Only the architecture of improved NS SAR ADC based on gain adopts the kT/C noise cancellation technique, so the input capacitance of this structure is minimal. This alleviates the difficulty of designing the input buffer. Active gain is introduced in the structures of NS SAR ADC based on gain and improved NS SAR ADC based on gain to decrease the comparator noise and the kT/C noise excluding kT/C sampling noise. The comparator noise is suppressed by the open-loop amplifier, which makes it unnecessary to use extra clock cycles to reduce the comparator noise. This improves the sample rate, which is a parameter characterizing the speed of the ADC. However, the open-loop amplifier used in the proposed architectures also consumes static power, which is not friendly to the overall power consumption and Schreier Figure of Merit (FoM) or Walden FoM. Therefore, power consumption is also an important parameter to compare. Performance comparison and summary of the single-ended second-order fully-passive NS SAR ADC, NS SAR ADC based on gain and improved NS SAR ADC based on gain is shown in

Table 1. Performance comparison and summary.

Architecture	Second-Order Fully-Passive NS SAR	NS SAR Based on Active Gain	Improved NS SAR Based on Activegain
Ctotal	large	medium	small
ADC Input Cap	$2^{\mathrm{N}}{\mathrm{C}}_0$	$2^{\mathrm{N}}{\mathrm{C}}_0$	${\displaystyle \frac{2^{\mathrm{N}}{\mathrm{C}}_0}{{\mathrm{e}}^{2\Delta \mathrm{t}/\mathsf{\tau }}}}$
kT/C Suppressed?	×	√	√
Comparator Noise Suppressed?	√	√	√
Extra Cycles?	√	×	×
Static Power	×	√	√

.

5. Conclusions

This paper proposes a novel second-order passive NS SAR ADC based on active gain, which effectively suppresses the negative effect of kT/C on SNR. Compared to the second-order fully-passive NS SAR ADC, an open-loop amplifier, a cancellation capacitor C_nc, and C_nc sampling switch S₂ are added to the proposed scheme. The open-loop amplifier mitigates both kT/C noise and comparator noise, improving sampling speed while significantly reducing capacitance. Although smaller capacitance leads to reduced dynamic power consumption, the introduction of the open-loop amplifier results in static power consumption. This necessitates a trade-off between performance and power consumption. However, this scheme is still a good choice for high-speed and high-resolution applications.