Multi-View Graph Learning for Path-Level Aging-Aware Timing Prediction
Abstract
:1. Introduction
- We have implemented an end-to-end aging-aware path time prediction framework based on multi-view graph learning, achieving a tradeoff between efficiency and accuracy.
- We customize a STTN-GAT model to improve the model’s expressing ability and reduce the over-smoothing issues.
- The prediction accuracy and runtime of our model has been validated on multiple industrial designs.
2. Related Works
2.1. Existing Approaches for Aging-Aware Timing Modeling
2.1.1. Aging-Aware SPICE Simulation
2.1.2. Aging-Aware STA
2.2. Frontier Machine Learning Techniques for Timing Prediction
3. Preliminaries
3.1. NBTI Degradation
3.2. Graph Neural Networks
3.3. Transformer Network
4. Aging-Aware Timing Prediction Model
4.1. Overview
4.2. Spatial–Temporal Transformer Network Design for Workload Features
4.2.1. Graph Representation and Workload Features
4.2.2. Spatial–Temporal Embedding
4.2.3. Spatial–Temporal Transformer Model
Algorithm 1 Dynamic path 1-hop subgraph overall representation |
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4.3. Graph Attention Networks Design for Path Timing Features
4.3.1. Graph Representation and Timing Features
4.3.2. Graph Attention Model
5. Experimental Result
5.1. Experiment Setup
5.2. Results and Comparison
5.2.1. Ablation Experiment
5.2.2. Comparison with Existing Models
6. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
References
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Type | Name | Description | Dimension |
---|---|---|---|
Node | cell_func | one-hot encoded cell type | 8 |
drive_strength | drive strength of cell | 1 | |
wst_output_slack | worst slack of output pins | 1 | |
wst_input_slack | worst slack of input pins | 1 | |
max_input_slew | maximum slew of input pins | 1 | |
max_output_slew | maximum slew of output pins | 1 | |
tot_input_cap | total capacitance of input pins | 1 | |
input_wst_sp | worst signal probability of input pins | 1 | |
output_sp | signal probability of output pins | 1 | |
Global | op_temp | operation temperature | 1 |
op_voltage | operation voltage | 1 | |
op_time | operation time range | 1 |
Type | Name | Description | Dimension |
---|---|---|---|
Node | cell_func | one-hot encoded cell type | 8 |
drive_strength | drive strength of cell | 1 | |
in_trans | transition time of input pins | 1 | |
in_type | transition type of input pins | 1 | |
out_trans | transition time of output pins | 1 | |
cell_delay | cell delay | 1 | |
cell_cap | cell load capacitance | 1 | |
fanout | cell fanout number | 1 | |
Global | path_delay | fresh path delay | 1 |
path_depth | path depth | 1 |
Design | #Cells | #FFs | #Train Paths | #Test Paths | |
---|---|---|---|---|---|
Known | RISC-V | 154,912 | 9829 | 10,385 | 2596 |
FFT | 102,226 | 9922 | 11,191 | 2238 | |
Unknow | AC_97 | 12,787 | 2229 | 0 | 2129 |
AES_CORE | 16,424 | 530 | 0 | 659 | |
SYSTEMCDES | 2258 | 190 | 0 | 445 | |
WB_DMA | 4573 | 611 | 0 | 921 |
Design | R2Score/MAPE (%) | |||||
---|---|---|---|---|---|---|
Ma | Mb | Mc | Md | M | ||
Known | RISC-V | 0.846/7.84 | 0.909/5.12 | 0.922/5.04 | 0.942/4.93 | 0.974/3.90 |
FFT | 0.850/5.87 | 0.914/4.43 | 0.938/5.14 | 0.973/4.67 | 0.981/4.19 | |
Unknow | AC_97 | 0.910/6.09 | 0.916/4.97 | 0.952/4.92 | 0.962/4.72 | 0.992/4.05 |
AES_CORE | 0.811/10.27 | 0.908/4.83 | 0.948/3.30 | 0.968/4.06 | 0.991/2.61 | |
SYSTEMCDES | 0.865/11.48 | 0.919/5.71 | 0.909/6.15 | 0.949/6.06 | 0.962/5.77 | |
WB_DMA | 0.830/9.26 | 0.916/5.29 | 0.927/3.84 | 0.964/3.766 | 0.986/3.21 | |
Average | 0.852/8.468 | 0.914/5.083 | 0.933/4.732 | 0.959/4.701 | 0.981/3.955 |
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Bu, A.; Li, X.; Li, Z.; Chen, Y. Multi-View Graph Learning for Path-Level Aging-Aware Timing Prediction. Electronics 2024, 13, 3479. https://doi.org/10.3390/electronics13173479
Bu A, Li X, Li Z, Chen Y. Multi-View Graph Learning for Path-Level Aging-Aware Timing Prediction. Electronics. 2024; 13(17):3479. https://doi.org/10.3390/electronics13173479
Chicago/Turabian StyleBu, Aiguo, Xiang Li, Zeyu Li, and Yizhen Chen. 2024. "Multi-View Graph Learning for Path-Level Aging-Aware Timing Prediction" Electronics 13, no. 17: 3479. https://doi.org/10.3390/electronics13173479