Frequent Power-Up-and-Down-Induced Degradation of Device and Bandgap Voltage Reference in 14-nm FinFET Technology

Abstract

The need for low power consumption in highly integrated systems-on-chip (SoCs), such as IoT-based smoke detection systems, has made frequent power-ups and power-downs a common practice. Although the device performance degradation caused by such frequent power-ups and power-downs is ignored in most circuit studies, in high-precision bandgap voltage references, the degradation of particular devices can result in a reference voltage shift. This work investigates the effects of frequent power-ups and power-downs on a simple bandgap reference circuit and demonstrates that the effects are real and non-negligible. Aging simulations based on simple bandgap reference circuits are performed to analyze the causes of device performance degradation and circuit output voltage shifts. The simulation results show that frequent power-ups and power-downs induce the negative bias temperature instability (NBTI) effect, a phenomenon that causes performance degradation in devices, such as threshold voltage degradation, under negative bias and high temperature conditions. Further, gate voltage waveforms of these devices were extracted for aging tests and the results of the tests in 14 nm FinFET and the NBTI aging model were used to infer the threshold voltage shift after 10 years at 125 °C. A circuit modification is proposed to mitigate the degradation of device performance and reference voltage shift. This work indicates that NBTI stresses introduced by frequent power-ups and power-downs need to be considered in circuit design.

1. Introduction

With the rapid advancement of system-on-chip (SoC) technology, the pursuit of high performance, large scale, and high integration has made the system power consumption a great challenge [1]. Low-power SoCs often utilize power management modules to switch parts of the circuitry that are temporarily not required into a power-down mode [2,3]. This approach allows for efficient power utilization and helps meet the increasingly high performance and low power consumption requirements in modern SoCs. As an example, the SoC for smoke detection integrates a series of sensors such as temperature and humidity, which are detected at regular intervals to achieve real-time monitoring and response to changes in the environment while also reducing power consumption [4,5]. However, this approach to reduce power consumption leaves some of the functional circuits to be powered up and down frequently, leading to reliability issues as the performance of the devices in the circuit degrades.

Frequent power-down-and-power-up-induced device degradation has not been a concern in circuit studies due to the fact that for most of the circuit modules, the aging of the devices in the power-down circuits does not affect the circuit performance or the effect is negligible. However, for bandgap voltage references, the start-up circuit connected to the power-down circuit directly affects the bias current [6], high-precision bandgap voltage references with output accuracy at the ppm level are sensitive to the absolute value of the bias current, and device degradation caused by frequent power-ups and power-downs cannot be ignored.

According to the existing research on the mechanism of device degradation, directly related to the device degradation caused by frequent power-ups and power-downs is negative bias temperature instability (NBTI) [7,8,9], which refers to the progressive degradation of various electrical parameters, including threshold voltage and saturation current, in p-channel devices due to the prolonged application of negative gate bias [10,11]. The research of NBTI-induced circuit reliability degradation primarily focusses on digital circuits and frequency-dependent circuits like PLL and oscillator circuits. This emphasis stems from the fact that the gate voltage and drain voltages in these circuits often exhibit magnitudes that are close to the power supply voltage [12,13,14]. In analog circuits, the primary consequence of NBTI on circuit reliability manifests in device mismatches under varied gate biases. Specifically, this leads to output delays in comparators, output voltage decreases in amplifiers, and mismatches in current mirrors [15,16,17,18,19]. However, it is worth noting that the causes of NBTI effects in the existing studies are due to the prolonged operation of the circuits rather than frequent power-ups and power-downs, and that the circuit reliability analyses are limited to simulations relying on the NBTI aging model and lack data from actual tests. Transient start-up currents occur in circuits under frequent power on/off cycles, generating Joule heat that can cause localized temperature rises. Concurrently, devices experience significant negative gate bias during repeated power-ups and power-downs. Both of these phenomena accelerate NBTI degradation, making the accurate modeling of degradation effects crucial for predicting device longevity and reliability. Further research is needed to fill gaps on the effect of frequent power-ups and -downs on performance degradation in circuits. Insights into circuit degradation can be gained by analyzing the aging of specific devices within the overall circuit, providing a deeper understanding of bandgap reference shifts due to frequent power-ups and power-downs. Therefore, anti-aging studies are conducted on a bandgap reference with repeated power-ups and -downs for smoke detection SoCs in FinFET technology. Compared to standard CMOS, FinFET technology has specific characteristics such as better energy efficiency and greater resistance to parameter variability, making it more suitable for high-density, high-performance, and low-power applications. Additionally, FinFETs offer better channel control and reduced leakage currents, which are crucial factors when studying NBTI effects.

In this paper, the effect of frequent power-ups and power-downs on the output shift of a bandgap reference circuit is investigated through aging simulations of a simple bandgap voltage reference circuit and aging tests of a p-FinFET device under NBTI stress. The aging simulation of the bandgap reference circuit is used to identify a specific device that causes the reference voltage to shift during frequent power-ups and power-downs. Based on the simulated waveforms of the device gate, NBTI stress is applied to actual devices manufactured using the 14 nm FinFET process. Aging tests are then conducted to estimate the threshold voltage shift of these devices after 10 years of exposure to this stress at 125 °C. The reasons for circuit degradation caused by this device are analyzed, and the circuit is improved to reduce NBTI degradation. Our study provides a more comprehensive understanding and analysis of analog circuit degradation caused by power-ups and -downs, offering guidance for circuit design and reliability assessment.

2. NBTI Degradation Model

NBTI refers to the degradation of electrical parameters in p-FETs that occurs when a negative gate voltage is applied at high temperatures. On the nanometer scale, the impact of NBTI on electrical parameters such as threshold voltage shift and saturation current reduction becomes increasingly severe. Extensive research has been conducted to investigate the influence of these parameter degradations on analog circuits. Although there is ongoing debate about the precise mechanisms of NBTI degradation, there are widely acknowledged factors contributing to NBTI effects [20]. These include interface trap formation, hole trapping in the oxide layer, and bulk trap generation [15]. All of these mechanisms are intricately linked to the manufacturing process and stress conditions. Here, the degradation model of NBTI is described in [21,22]:

$$\mathsf{\Delta }{\mathrm{V}}_{\mathrm{TH}}=\mathrm{A} \times {\mathrm{e}}^{-{\displaystyle \frac{{\mathrm{E}}_{\mathrm{a}}}{\mathrm{kT}}}} \times {\mathrm{e}}^{\mathrm{m}{\mathrm{V}}_{\mathrm{gs}}} \times {\mathrm{t}}^{\mathrm{n}}$$

(1)

where E_a is the activation energy, k is Boltzmann’s constant, V_gs is the applied gate-source voltage, and T and t are the aging temperature and time, respectively. A is a constant related to the process. m and n are acceleration exponential factors for gate source voltage and time, with n being 0.2 in the simulation. Based on the degradation model, the evaluation of threshold voltage shift at low voltages can be performed through device aging tests that are accelerated by applying high gate voltages and can also be extrapolated for long time aging threshold voltage shift.

3. Results and Discussion

3.1. Circuit Modules and Simulation

3.1.1. Configurations of Simulated Bandgap Voltage Reference

The schematic of the proposed bandgap reference circuit is shown in Figure 1a. The overall circuit architecture consists of the core circuit with a Proportional to Absolute Temperature (PTAT) current generation scheme, a start-up circuit, and choppers. The base-emitter voltage VBE of the BJT exhibits a negative correlation with temperature. The aforementioned core circuit combines the linear PTAT voltage generated by the PTAT current and the VBE with an appropriate scaling factor to generate a voltage that remains independent of temperature, power supply, and process variations.

As shown in Figure 1b, the PTAT current generated by the core circuit is:

$${\mathrm{I}}_{\mathrm{PTAT} }={\displaystyle \frac{{\mathrm{V}}_{\mathrm{T}}\ln \mathrm{n}}{{\mathrm{R}}_1}}$$

(2)

where V_T is the thermal voltage and n is the area ratio of BJT Q0 and Q1. Then, the PTAT current flows through R1 and R3 and generates bandgap reference voltage V_REF with V_BE1 of BJT Q1, as follows:

$${\mathrm{V}}_{\mathrm{REF} }={\mathrm{V}}_{\mathrm{T}}\ln \mathrm{n}·{\displaystyle \frac{{\mathrm{R}}_1+{\mathrm{R}}_3}{{\mathrm{R}}_1}}+{\mathrm{V}}_{\mathrm{B}\mathrm{E}1}$$

(3)

where the V_T is proportional to temperature and V_BE1 is negatively correlated with temperature. Thus, the two terms of the equation have positive and negative temperature coefficients, respectively. The PTAT voltage can be scaled by adjusting the coefficient associated with n, R1, and R3 to compensate for the voltage V_BE1 with a negative temperature coefficient and generate the reference voltage V_REF. This equation embodies the principle of voltage compensation based on temperature coefficients [6].

The operational amplifier of the core circuit is used to maintain the voltage levels at its two inputs approximately equal. Since the offset voltage at the two inputs of the op-amp directly affects the magnitude of the PTAT current, leading to the accuracy degradation of the bandgap voltage reference, choppers are used to periodically switch the input signals at the two inputs to reduce DC offset errors and improve the precision [23]. The filter at the output of the op-amp is used to average the output voltages at the OUTP and OUTN outputs. The load n-channel FinFETs are biased by M13 and M14.

In the bandgap voltage reference circuit, when the value of the voltage at the BP1 node is close to the supply voltage, the absence of current in the circuit signifies a specific steady state not intended. In order to avoid the state and to increase the start-up speed of the circuit, the start-up circuit in Figure 1c is applied. In the scenario where the enable signal EN is at the voltage level of VSS, the bandgap voltage reference circuit operates in a zero current mode. During this mode, the voltage at the VBG node closely approximates VSS and transistor M11 turns off while transistor M12 turns on, causing the BP1 node to be pulled down to the VSS level. This sequence allows the circuit to initiate its normal operation. It should be noted that the start-up circuit does not interfere with the normal operation of the circuit.

The circuit is simulated using the 14 nm FinFET process. The length of the devices in the PDK is limited, so to achieve the required size, nine devices are connected in series as a single device, as shown in Figure 1d.

3.1.2. Aging Analysis and Problem Identification

By using the Semiconductor Manufacturing International Corporation (SMIC) 14 nm FinFET process to simulate the proposed bandgap voltage reference, the results of the temperature variation of the pristine circuit and degraded circuit after 10 years of aging at 125 °C are shown below. The simulation of this circuit was conducted under a power supply voltage of 1.8 V. To emulate the frequent power-up process of the bandgap voltage reference in practical scenarios, a square wave signal was utilized as the enable signal. This signal ranged from 0 V to 1.8 V with a period of 500 μs and a pulse width of 250 μs. In this section, the devices cause degradation of the circuit will be discussed.

Figure 2 indicates the results of pre-layout simulation. Figure 2a shows the variation in VREF with temperature for the bandgap voltage reference. The VREF is 1.17 V at 25 °C and the temperature coefficient is 18.3 ppm/°C from −40 °C to 125 °C, with a maximum value of 1.172 V and a minimum value of 1.168 V. The temperature coefficient of the bandgap reference is calculated using the following equation:

$$\mathrm{TC}={\displaystyle \frac{\mathrm{VRE}{\mathrm{F}}_{\max }-\mathrm{VRE}{\mathrm{F}}_{\min }}{\mathsf{\Delta }\mathrm{Temperature} · \mathrm{VRE}{\mathrm{F}}_{\mathrm{average}}·{10}^6}}$$

(4)

Figure 2b illustrates the output curve of the bandgap voltage reference at VBG node within 500 μs after the circuit is turned on. The red curve corresponds to the VBG’s output voltage curve before aging, while the blue curve represents the output voltage curve after subjecting the circuit to the specified stresses, aging at 125 °C for 10 years. It is observed that the output of the bandgap voltage reference is reduced by about 10 mV after aging. Bandgap references are essential in integrated circuits for precision applications such as ADCs (analog-to-digital converters) and voltage regulation circuits. However, even minor variations in voltage can compromise the system’s accuracy and reliability, potentially leading to malfunctions or reduced performance. For instance, in high-precision, low-speed incremental Delta-Sigma ADCs used for measurement, slight shifts in the reference voltage can result in inaccuracies during the analog-to-digital conversion process, causing output errors. Figure 2c,d show the voltage waveforms at the VBP node within 500 μs of circuit start-up and the aging stress on the VBP during aging, respectively. A voltage reduction of about 80 mV is observed at VBP. A voltage source is added to VBP to verify if this reduction leads to the output voltage reference shift, as shown in Figure 2e. Figure 2f shows the shift of VBG as the shift of VBP varies from −100 mV to +100 mV, and the data point at VBP = −63 mV matches the output VBG value after aging. The reference voltage at the output of the circuit after the aging simulation is 1.156 mV, which is the same as the reference voltage of the circuit after the VBP node voltage is reduced by 63 mV. This indicates that it is indeed the aging of the device associated with the VBP node voltage that is causing the reference voltage to shift.

A substantial degradation of devices M2, M9, M10, and M15 is evident from the simulation results, showing threshold voltage shifts exceeding 10 mV. During circuit operation in the power-down mode, the Vgs for these P-channel FinFETs notably increases, approaching the supply voltage. Each series-connected device composing M2, M9, M10, and M15 operates with millivolt-level Vds (source-drain voltage) and approximately 1 µA Ids (source-drain current). These conditions—high Vgs and low Vds and Ids—confirm that the devices are undergoing NBTI stress rather than HCI (hot carrier injection) stress. Hot carrier injection stresses arise due to interfacial states induced by drain avalanche carrier injection, and the stress conditions are characterized by high Vgs, Vds, and Ids [24].

In the bandgap reference circuit, the gates of FinFETs M2, M9, M10, and M15 are connected to the VBP node. As these devices experience an increase in threshold voltage due to NBTI stress, the VBP node level decreases to maintain their saturated operating state. Consequently, this induces a further negative bias on the gates of the devices, exacerbating the NBTI effect. Simultaneously, it disrupts the circuit’s static operating point and introduces mismatches in the bandgap reference op-amps, causing a shift in the output reference voltage.

3.2. Device Aging Test Results and Discussion

Individual device aging tests were performed to validate the existence of NBTI aging in the simulation and to derive the device subthreshold voltage shift for practical applications. The FinFET devices tested in this work are core devices fabricated based on the SMIC FinFET process platform. The typical device has 14 fins, with a fin height of ~30 nm, a fin top width of ~10 nm, and an effective gate length of ~15 nm. NBTI stress is applied on p-channel FinFET with voltage acceleration using alternating gate bias at the temperature of 125 °C for 1000 s to represent the frequent power-ups of M2 in the bandgap voltage reference circuit. The drain, source, and well electrodes are biased at the supply voltage to prevent other degradation effects caused by excessive source-drain current during the stress process. The high level of the square wave of the gate stress varies between 3 V and 3.4 V to ensure that the degradation of the threshold voltage can be measured and that the gate dielectric breakdown does not occur.

The degradation of the p-channel FinFET is observed by threshold voltage shift with a stress-measure-stress technique [25,26]. Stress is applied at logarithmic time intervals with periodic interruptions to measure the drain current at a fixed voltage input of 0 V at the gate, 1.79 V at the source, and 1.8 V at the drain and well electrodes. The threshold voltage shift is extracted by linearly interpolating the I_d-V_g curves based on the measured drain current.

Figure 3 shows the conditions and results of the aging test. Figure 3a depicts the gate bias waveform during actual testing. Figure 3b presents the original I_d-V_g and I_d-V_d characteristics of the device being tested. Figure 3c illustrates the temporal variation in the V_th shift during a 1000 s aging test, where the gate input is a square wave with different high levels. Logarithmic scales are employed for both the horizontal and vertical axes. By applying logarithms to both sides of Equation (1), a linear fit can be performed on the obtained data. The average slope of the resulting curve is determined to be 0.283, which represents the tested value of the time exponent n in Equation (1). Figure 3d illustrates the relationship between the shift value of V_th and time when the gate is grounded. After applying logarithmic transformations and performing linear fit analysis, the resulting slope is determined to be 0.253. Figure 3e displays the fitting of the V_th shift over 1000 s, extracted from Figure 3c and Figure 3d, respectively. The fitting is performed based on the relationship between the V_th shift and V_gs, as described in Equation (1). Figure 3f is optimized from Figure 2f and represents the voltage shift of the bandgap reference output with respect to the VBP node voltage, where the shift is calculated by substituting into Equation (4) to obtain the ppm level of variation.

The average slopes obtained from the linear fit analysis in Figure 3c,d are 0.283 and 0.253, respectively. According to Equation (1) and related illustration, these values correspond to the time acceleration exponential factor n. Typically, n assumes a value around 0.2 in the context of NBTI effects. In contrast, existing studies have shown this acceleration exponential factor to be above 0.5 in the HCI effect [27]. Thus, the results affirm that device aging is predominantly influenced by NBTI rather than HCI.

Based on the VBP waveform acquired through simulation and the fitted curve depicted in Figure 3e, it is possible to extrapolate the results. It can be inferred that when V_gs is a square wave with a high level of 1.8 V, the shift value of V_th after 1000 s of aging at 125 °C is estimated to be 0.969 mV. Furthermore, by extrapolating from the curve presented in Figure 3c, the shift value of V_th is projected to reach 34.9 mV after 10 years, which corresponds to a bandgap reference accuracy degradation of 28.5 ppm/°C according to Figure 3f. Similarly, by extrapolating from Figure 3d, if the measured device is subjected to prolonged bias with a negative gate voltage of 1.8 V, the anticipated shift value of V_th after 10 years is determined to be 45.8 mV.

The threshold voltage shifts observed in M2, M9, M10, and M15 during frequent power-ups of the bandgap reference can be attributed to the substantial negative bias applied to the gate. This negative bias results from VBP approaching VSS during the power-down state. To mitigate this degradation, a modification was made to the original circuit’s start-up circuit, as depicted in Figure 4a. In this modified circuit, when the supply voltage is 0 V, VBP is also 0 V. Upon power-up, M1 is turned off, M2 is turned on, and VBP is pulled up, enabling normal circuit operation. Consequently, M2 remains in the “on” state while M1 remains in the “off” state, thus ensuring that the normal operation of the circuit is not disrupted. During power-down, the effect of the enable terminal causes VBP to be close to VDD. As shown in Figure 4b, the modified start-up circuit results in a voltage waveform of VBP floating around 1.3 V, with corresponding V_gs values of M2, M9, M10, and M15 only reaching 0.5 V. Figure 4c,d demonstrate that the modification of the start-up circuit significantly reduces the shift of VBG and VBP compared to the pre-modification one after simulating aging for 10 years 125 °C. Based on the modification to the start-up circuit, a long-term negative gate bias of 0.5 V can be effectively applied on M2, M9, M10, and M15. Extrapolating the curves in Figure 3d,e, tests suggest that the device threshold voltage is expected to degrade by 2.8 mV after 10 years of aging at 125 °C. According to Figure 3f, a threshold voltage shift of 2.8 mV corresponds to a degradation of 1.6 ppm/°C in bandgap reference accuracy. The degradation is minimal and has negligible impact over a period of 10 years at room temperature (25 °C).

4. Conclusions

Frequent power-ups and power-downs cause the output voltage of the high-precision bandgap reference to shift. This work investigates the degradation of devices and bandgap reference circuits caused by frequent power-ups and power-downs. Based on the aging simulation of the bandgap voltage reference with frequent power-ups and power-downs, devices that exhibit significant degradation and lead to the shift of reference voltage were identified and tested under the simulated NBTI stress. It was observed that the devices exhibit a significant shift in threshold voltage when subjected to NBTI stress, which disrupts the operating point of the circuit, consequently leading to a shift in the reference voltage. The substantial shift observed in the threshold voltage of these devices can be attributed to the specific design characteristics of the start-up circuit. Modifications were made to the startup circuit to reduce the NBTI stress on the devices and minimize the degradation of the bandgap voltage reference. The findings of this study highlight the impact of NBTI stress on the devices and analog circuits in the power-down mode. These results are crucial for enhancing the reliability and longevity of analog circuits in low-power SoCs. By considering the specific design characteristics of circuits and implementing appropriate modifications, circuit designers can create more reliable and durable analog circuits in low-power SoCs, ultimately improving the overall lifespan of integrated systems.