A CMOS Rail-to-Rail Class AB Second-Generation Voltage Conveyor and Its Application in a Relaxation Oscillator

Abstract

In this paper, we present a CMOS rail-to-rail second-generation voltage conveyor (VCII) suitable for low power applications, implemented in 180 nm CMOS technology with a supply voltage of ± 0.9 V. The proposed VCII consists of a current and voltage buffer operating in class AB. At the input of the voltage buffer, there is a bulk-driven differential amplifier, which provides a rail-to-rail input common-mode voltage. A common source output stage in class AB provides rail-to-rail at the output of the voltage buffer. The transistors are designed to operate in moderate inversion, achieving a relatively large current and voltage buffer bandwidth of 298.3 MHz and 173.2 MHz, respectively, with a power consumption of 157 μW. A sine wave with an amplitude of 1.5 V_pp and a frequency of 1 MHz on the output buffer has a total harmonic distortion of only 0.29%. The application of VCII in a relaxation oscillator with a frequency of up to 10 MHz is demonstrated, as well as its comparative characteristics with reference to other relevant square-wave generators published in the literature.

1. Introduction

An analog building block (ABB) is a fundamental electronic circuit or component that performs an analog function. It is used in various applications, including signal processing, communication systems, control systems, and instrumentation. The most used ABBs are long-conceived operational amplifiers (OAs). However, designing low-voltage supply circuits with a high-gain bandwidth product and high current and voltage drive capability is challenging in modern technologies, so recently, other ABBs have been more frequently used. Current conveyors (CCs) are well-known wide-bandwidth blocks with current mode signal processing and simpler circuitry than OAs [1,2]. Voltage conveyors (VCs) were obtained by swapping input and output stages in a CC [3,4,5,6,7], which resulted in an ABB with an input current buffer (CB) and an output voltage buffer (VB).

The VCII is an ABB with a low-impedance current input port (Y), a high-impedance current output port (X), and a low-impedance voltage output port (Z). Like a second-generation current conveyor (CCII), the VCII is versatile and can be configured in various ways to achieve different functions in a wide frequency range. However, it has an output voltage buffer, unlike CCII, so it is more suitable in circuits with low load impedance and high output current. Therefore, it is not necessarily an additional output voltage buffer as with the CCII-based circuits, so lower power consumption and a smaller chip area can be expected. Another important feature of the VCII is the ability to use the Y port as both current and voltage input because its input impedance can be very low [8,9,10]. The VCII processes the input current at the Y port, and due to the low impedance (practically grounded), a voltage can easily be applied via the series resistance (V/I conversion). This feature also allows simple implementations of current summing/subtracting operations at the Y port, and an additional advantage is the possibility of programmable control of the parasitic Y impedance [11,12,13,14]. Voltage conveyors are specifically designed to handle and transfer voltage signals directly, so signal processing operations, such as voltage amplifiers, typically require fewer active blocks than CCII-based ones [15,16]. During the past decade, the VCII has attracted the attention of researchers. Its various applications have been presented in positive and negative impedance simulators and impedance multipliers [8,11,15,17,18,19,20,21], different types of analog filters [12,13,22,23,24], voltage amplifiers [25,26,27,28], sinusoidal oscillators [29,30], the Schmitt Trigger [31,32], electronic interfaces for biosensors [33,34], etc. Since a literature survey has shown that realizations of relaxation oscillators with a VCII based on a negative impedance converter (NIC) have not yet been published, we have decided to investigate them. Like a CCII, a VCII provides high linearity and stability, which are useful in relaxation oscillators. This ensures that the oscillation frequency remains stable during the process, supplying voltage and temperature (PVT) variations. The wide bandwidth allows them to design square-wave oscillators with tunable frequencies by modifying passive components such as resistors and capacitors. A CCII is preferred in high-frequency current-mode oscillators, while a VCII is suitable for both oscillator types, whether current- or voltage-mode.

For increased efficiency, more efficient methods must be used, both statically and dynamically, which will polarize the output stage in class B or AB. Class B has the highest efficiency but also large crossover distortions and a difficult adjustment of open loop quiescent operating points. Class AB provides the possibility of obtaining high efficiency with relatively low distortion. A large voltage or current is required when there is a large output power load, either static or dynamic. Advanced CMOS technologies usually have low supply voltages, so the need for a large output swing is more pronounced. The output of VCII is VB, so a large input and output swing must be provided simultaneously. A more efficient CB is obtained when operating in class AB for the same reasons as the VB. Analyzing previously reported VCII implementations, it was noted that several circuits were designed in class AB [9,16,35,36,37,38,39], and some had very simple realizations [16,36,38]. The VCII described in [16] has very large current and voltage transfer bandwidths, but the current/voltage offset is significant. The other circuits are designed for low-voltage low-power applications but suffer from high input impedances at current inputs [36] or operate efficiently for relatively low frequencies [38]. Many reported realizations of class AB VCIIs are not rail-to-rail [9,16,37,39].

In this paper, we propose a VCII operating in class AB to reduce power consumption that has rail-to-rail input and output capability. Designing low-voltage supply circuits with high current and voltage drive capabilities is challenging. The design process of the proposed VCII includes several constraints: the higher the bandwidth, the lower the dissipation, and the smaller the area of the integrated CMOS realization. Moderate inversion was chosen as a compromise for transistor design. A negative feedback loop was applied to obtain a low impedance at the Y and Z terminals. It makes implementation more complex but provides a higher bandwidth and robustness to PVT variations. Current and voltage buffers are designed in class AB due to symmetry, high slew rate, and low dissipation. Because of the rail-to-rail requirement, simple current sink/source and common source transistors on their outputs were used. A folded cascode differential amplifier, which has a large power supply rejection ratio (PSRR), was used in the VB input stage.

A designed VCII was used to realize a NIC as an active part of the relaxation oscillator. Using rail-to-rail VCII, an oscillator with low phase noise is obtained [40]. The key VCII performances decisive for designing an oscillator are power dissipation, harmonic distortion, bandwidth, and port characteristic impedances. Since the short-channel transistor models are non-linear, the initial design provides rough estimates of the VCII characteristics. Iterative simulations are used to first adjust the operating point parameters, then the dynamic characteristics of the VCII, and finally, the assessment of deviations due to PVT variations.

The realization of a new CMOS rail-to-rail class AB second-generation voltage conveyor is described in Section 2. Simulation results for the proposed circuit and comparison with other reported class AB rail-to-rail VCII realizations are also presented in this section. The analysis of a relaxation oscillator based on a voltage conveyor is presented in Section 3. In this section, an approximate alternative determination of the oscillation frequency of an oscillator with negative resistance, its change due to PVT variations, Monte Carlo analysis, and phase noise are also given. All circuits are simulated in 180 nm CMOS integrated technology, and a supply voltage of ±0.9 V was used using the Cadence IC design package. Simulation results obtained by DC, AC, and transient simulations, as well as periodic steady state (PSS), phase noise, and s-parameter analysis, are given. Section 4 concludes this paper by comparing the proposed relaxation oscillator with a VCII and several other relevant oscillators.

2. Class AB Rail-to-Rail VCII

The second-generation voltage conveyor is a three-terminal element defined by the following relations [15]:

$$\left[\begin{array}{c}{i}_X\\ v_Y\\ v_Z\end{array}\right]=\left[\begin{array}{ccc}{\displaystyle \frac{1}{r_X}}+s{C}_X& \beta & 0\\ 0& r_Y+s{L}_Y& 0\\ \alpha & 0& r_Z+s{L}_Z\end{array}\right]\left[\begin{array}{c}{v}_X\\ i_Y\\ i_Z\end{array}\right],$$

(1)

where $\alpha$ is the voltage gain between X and Z terminals, $\beta$ is the current gain between Y and X terminals, and $r_X$, $C_X$, $r_Y$, $L_Y$, $r_Z$, and $L_Z$ are elements of parasitic impedances associated with terminals (Figure 1). In an ideal case, all parasitic impedances could be neglected and both gains are unitary, $\alpha =1$, $\beta =1$. The sign of current gain $\beta$ determines the type of VCII: positive $({\mathrm{VCII}}^{+})$ for positive $\beta$ (ideally $\beta =+1$) or negative $({\mathrm{VCII}}^{-})$ (ideally $\beta =-1$). As we shall see later, negative-type VCII will be necessary to implement a single VCII relaxation oscillator for the same reasons as shown for single VCII sinusoidal oscillators [29].

The three-terminal element defined by (1) can be realized as a cascade connection of a current buffer (CB) as the input block and a voltage buffer (VB) as the output block (Figure 2) [5].

2.1. The Class AB Current Buffer

The CB of the proposed VCII operates in class AB and is shown in Figure 3 [32]. Transistors $M_1-M_4$ form a translinear loop, while transistors $M_5-M_6$ create the negative feedback that decreases the input impedance of the CB. Transistors $M_9-M_{12}$ are added to the circuit to invert the CB characteristic to obtain a ${\mathrm{VCII}}^{-}$, a negative type of voltage conveyor. When $i_Y=0$, $M_5$ and $M_6$ conduct approximately $I_{B1}$ and the output current is $i_X=0$. As the input current $i_Y$ increases, the drain current $i_{D6}$ increases, while the current $i_{D5}$ decreases until $M_5$ is cut off, as well as $M_7$, $M_9$, $M_{12}$, and $M_{14}$. It is similar to the following: current $i_Y$ decreases; the transistor $M_6$ is cut off, as are $M_8$, $M_{10}$, $M_{11}$, and $M_{13}$. Since $M_1$ and $M_2$ have a constant drain current and work in the saturation, mapping the current through the current mirrors, an expression for the idealized current gain of the CB is easily obtained:

$$\beta ={\displaystyle \frac{i_x}{i_y}}=-1$$

(2)

The input resistance at the quiescent point is:

$$r_Y=r_{Y-up}||r_{Y-dn}\approx {\displaystyle \frac{1}{g_{m3}{g}_{m5}{r}_{ds3}}}||{\displaystyle \frac{1}{g_{m4}{g}_{m6}{r}_{ds4}}},$$

(3)

where $r_{Y-up}$ and $r_{Y-dn}$ are the input resistances of the upper and lower parts of the buffer, respectively. Transconductances $g_{m1}$ and $g_{m2}$ affect the $r_Y$ when the output resistances of the current sources $I_{B1,b,d}$ are small. Their influence can be neglected when $g_{m1}{R}_{out1,b}\gg 1$ and $g_{m2}{R}_{out1,d}\gg 1$, where $R_{out1,b}$ and $R_{out1,d}$ are the output resistances of current sources $I_{B1,b}$ and $I_{B1,d}$, respectively. The products $g_{m3}{r}_{ds3}$ and $g_{m4}{r}_{ds4}$ are the intrinsic transistor gains, which are simultaneously the loop gain of the CB. When they are high, the resistance at the Y port tends to zero.

The output resistance of the CB at the quiescent point is:

$$r_X=r_{ds13}||r_{ds14}={\displaystyle \frac{1}{g_{ds13}+g_{ds14}}}.$$

(4)

The dimensioning of the CB transistor results from the compromise for a low quiescent current, the largest bandwidth, the slightest influence of technological parameters, and the largest output voltage swing. A large $g_m/I_D$ means low power dissipation and a large output swing, while a small $g_m/I_D$ provides a larger bandwidth and a faster response [41]. Therefore, the operating points of all transistors are set for moderate inversion.

The transistor channel length was chosen to reduce the influence of the Early effect and provide a suitable bandwidth. Current sources $I_{B1,a}=I_{B1,b}=I_{B1,c}=I_{B1,d}=5 \mathsf{\mu }\mathrm{A}$ are implemented using NMOS ($I_{B1,c},I_{B1,d}$) and PMOS ($I_{B1,a},I_{B1,b}$) current mirrors with transistors whose dimensions are $4.32 \mathsf{\mu }\mathrm{m}/0.54 \mathsf{\mu }\mathrm{m}$ and $12.96 \mathsf{\mu }\mathrm{m}/0.54 \mathsf{\mu }\mathrm{m}$, respectively. In the current mirrors, transistors with $L=3L_{\min }=0.54 \mathsf{\mu }\mathrm{m}$ were used to reduce the Early ($\lambda$) effect and provide high output resistance. All other transistors have a channel length $L=0.36 \mathsf{\mu }\mathrm{m}$, while

Table 1. Channel width and g_m/I_D parameters in the current buffer.

Transistor	W (μm)	gm/ID (S/A)
M1, M3, M5	2.88	17.5
M2, M4, M6	7.31	17.1
M7, M9	8.64	18.8
M8, M10	2.88	17
M11, M13	8.64	18.3
M12, M14	2.88	17.2

lists the channel widths and their $g_m/I_D$ parameters.

Figure 4 shows the Y−X transfer function when the X terminal is connected to the ground. The same Figure also shows the $\beta$ coefficient, which was obtained using the derivative of the transfer function.

When transistors $M_5$ and $M_6$ conduct the same current, the current gain ${\beta }_{DC}$ has a minimum value ${\beta }_{DC\min }=-1.119$, and increases with the increasing absolute value of the current $i_Y$. The absolute value of the current gain is higher than 1 due to the Early effect in the current mirrors $M_7-M_{14}$.

To investigate the current buffer time-domain behavior, a 1 MHz sine wave with a parametric amplitude $I_m$ was applied to the Y terminal. By determining the short-circuit current of the X terminal in the time domain, total harmonic distortions (THDs) as a function of the amplitude $I_m$ are obtained (Figure 5). At a low input current amplitude $I_m$, all CB transistors are conducted in class A, which has a limited current drive capability at the X port. When the $I_m$ is high, transistor $M_{13}$ drives port X practically half the time, with the other half driven by $M_{14}$, and the quiescent current is the same as in class A. The benefits of driving in class AB are that significantly higher currents than bias currents are possible at port X, but at the cost of increased distortions. Therefore, the power dissipation is low, the efficiency is relatively high, and high currents can be achieved to drive the X capacitive load.

2.2. The Rail-to-Rail Voltage Buffer

The proposed voltage buffer is shown in Figure 6. It consists of an input folded-cascode amplifier ($M_{15}-M_{22}$) and a simple rail-to-rail common source output stage with class AB control ($M_{23}-M_{25}$). Because of the high gain of the output stage VB, the gate voltage of $M_{23}$ changes slightly as the output voltage changes, so all transistors in the rail-to-rail range will be saturated. It is well-known that the input common-mode voltage can be close to the negative power supply using a standard PMOS folded-cascode amplifier. The limitation of the input common-mode voltage from the upper side is that the transistor in the current source goes into the triode region.

Standard gate-driving differential amplifiers often use complementary input pairs (NMOS and PMOS) to cover the entire rail-to-rail input range [35,42]. The NMOS pair operates effectively when the input voltage is close to $V_{SS}$, while the PMOS pair is active when the input voltage is close to $V_{DD}$. Together, they ensure continuous operation across the entire input range. The design ensures a smooth transition between the NMOS and PMOS input pairs as the input voltage varies, preventing any dead zones or significant drops in performance across the input range. In low-voltage designs, the input can maintain operation across rail-to-rail input voltage by driving the bulk instead of the gate. Choosing a suitable voltage on the drain of the transistors $M_{15}$ and $M_{16}$, approximately $-550 \mathrm{mV}$, it is ensured that within $-0.9 \mathrm{V}\le V_{CM}\le 0.9 \mathrm{V}$, it cannot forward-bias the bulk-source and bulk-drain junctions in the PMOS structure [43,44]. If the input $V_{CM}$ increases in the rail-to-rail range, the voltage on the source-coupled pair $V_{S15,16}$ also increases. Due to the nonlinear characteristics $i_D=f(v_{GS},v_{BS},v_{DS})$, the change is smaller, approximately in the range of $-0.5 \mathrm{V}\le V_{S15,16}\le -0.1 \mathrm{V}$. When the $V_{CM}\le -400 \mathrm{mV}$, the body-source junction becomes forward-biased, but not enough to disturb the operation of transistors $M_{15}-M_{16}$ in the inversion region. Then, the input leakage currents are in the order of pA, similar to in [44].

Although its transconductance is significantly lower than when the excitation is applied to the gates, the DC voltage gain of the folded cascode amplifier is large, primarily due to the large output resistance. The output pole, determined by output capacitance and resistance, determines its frequency response.

The class AB output stage is implemented using the translinear contour $M_{23}-M_{25}$ [45]. The output transistors are in common-source configuration and have a large voltage gain whether they conduct both $M_{24}$ and $M_{25}$, or just one of them. Because of capacitances $C_{gd24}$ and $C_{gd25}$, the transfer function of the VB output stage has a right half-plane zero, so additional compensation is necessary to ensure a satisfactory phase margin when closing the feedback loop. This was achieved with the compensation capacitor $C_C$, using Miller compensation. We obtain approximately a single pole transfer function with it, but a new left half-plane zero also occurs. To reduce its influence, $C_C$ is connected to the source $M_{20}$, which has a low input resistance instead of the gate $M_{23}$.

According to the circuit configuration, the input impedance is predominantly capacitive, while the output impedance can be equivalent to a series connection of resistance and inductance. The output resistance of the voltage buffer can be obtained by applying Blackman’s theorem [46]:

$$r_Z={\displaystyle \frac{1}{g_{mb15,16}{R}_{out1}\cdot \left(g_{m24}+g_{m25}\right)}},$$

(5)

where $g_{mb15,16}$ is the body transconductance of $M_{15,16}$, while $R_{out1}$ is the output resistance of the first stage of the voltage buffer:

$$R_{out1}=g_{m20}{r}_{ds20}{r}_{ds22}\left|\right|g_{m18}{r}_{ds18}{r}_{ds16}.$$

(6)

The DC open-loop voltage gain is large:

$$A_0=g_{mb15,16}{R}_{out1}\cdot {\displaystyle \frac{g_{m24}+g_{m25}}{g_{ds24}+g_{ds25}}},$$

(7)

so the DC voltage gain of the VB is:

$$\alpha ={\displaystyle \frac{v_z}{v_x}}={\displaystyle \frac{A_0}{1+A_0}}\approx 1.$$

(8)

The design of the VB is based on the same principles as that of the CB. All transistors have the same channel length $L=0.36 \mathsf{\mu }\mathrm{m}$, while their channel widths and $g_m/I_D$ coefficients are given in

Table 2. Channel widths and g_m/I_D parameters in the voltage buffer.

Transistor	W (μm)	gm/ID (S/A)
M15, M16	10.8	18
M17, M18	2.88	15.2
M19–M22	8.64	14.7
M23	1.44	14.8
M24	3.24	13
M25	4.32	9.1

.

Current source $I_{B2}=10 \mathsf{\mu }\mathrm{A}$ is implemented using a PMOS current mirror with $W/L=25.92 \mathsf{\mu }\mathrm{m}/0.54 \mathsf{\mu }\mathrm{m}$. The NMOS current mirror, with (W/L) of $12.96 \mathsf{\mu }\mathrm{m}/0.54 \mathsf{\mu }\mathrm{m}$ and $4.32 \mathsf{\mu }\mathrm{m}/0.54 \mathsf{\mu }\mathrm{m}$, has been used in current sources $I_{B3,a}=I_{B3,b}=15 \mathsf{\mu }\mathrm{A}$ and $I_{B4}=5 \mathsf{\mu }\mathrm{A}$, respectively.

When the terminal Z is loaded with the resistance $R_L=10 \mathrm{k}\mathsf{\Omega }$, the VB voltage transfer function and its derivative are shown in Figure 7. Extremely good linearity of the VB is observed, and at $V_X=0$, the voltage gain is $\alpha =0.9994$. Distortion occurs if the voltage gain (α) is not uniform across the rail-to-rail input range. When the change is symmetrical concerning the operating point, the output voltage will not contain even harmonics, and a more significant deviation from unity leads to a stronger influence of odd harmonics and THD increases. When a complex periodic voltage appears at the input of the VB, as is the case in relaxation oscillators, intermodulation distortions occur.

2.3. Simulation Results for VCII

Nominal values of VCII parameters at the quiescent point with $V_{DD}=-V_{SS}=0.9 \mathrm{V}$ and $C_C=65 \mathrm{fF}$ were obtained by simulation: $V_{YDC}=2.23 \mathsf{\mu }\mathrm{V}$, $V_{XDC}=15.34 \mathsf{\mu }\mathrm{V}$, $V_{ZDC}=-189.3 \mathsf{\mu }\mathrm{V}$, $r_Y=110.4 \mathsf{\Omega }$, $L_Y=2.1 \mathsf{\mu }\mathrm{H}$, $r_X=759.7 \mathrm{k}\mathsf{\Omega }$, $C_X=41.95 \mathrm{fF}$, $r_Z=4.86 \mathsf{\Omega }$, and $L_Z=1.73 \mathsf{\mu }\mathrm{H}$. The circuit power consumption was $157 \mathsf{\mu }\mathrm{W}$. Voltage deviation from zero values on individual VCII terminals represents voltage offset. Due to the DC-negative feedback in the CB and the VB, the voltage offset is small at the Y and Z terminals. Adjusting the geometries of the transistors in the current buffer obtained a small voltage offset at the X terminal.

For the sake of comparison to the results from other works [37], the terminal Z is loaded with a parallel connection of capacitance $C_L=1 \mathrm{pF}$ and resistance $R_L=10 \mathrm{k}\mathsf{\Omega }$. Figure 8 shows the transfer functions of the CB ($\beta$) and the VB ($\alpha$). The DC gains of the current and the voltage buffer are ${\beta }_0=975.5 \mathrm{mdB}$ and ${\alpha }_0=-4.75 \mathrm{mdB}$, while the 3 dB bandwidths are ${\beta }_{BW}=298.3 \mathrm{MHz}$ and ${\alpha }_{BW}=173.2 \mathrm{MHz}$.

A $1 \mathrm{MHz}$ sine wave with a maximum peak amplitude of $1.5 \mathrm{V}$ was applied to the VB input. Using PSS analysis, the THD value with 10 harmonics was found to be 0.29%.

By determining the response to rectangular voltage excitation, it is obtained that the slew rate of the voltage buffer is $S{R}^{+}=173.8 \mathrm{V}/\mathsf{\mu }\mathrm{s}$ and $S{R}^{-}=146.3 \mathrm{V}/\mathsf{\mu }\mathrm{s}$. At a small fast change of excitation, the settling times in CB and VB are obtained. With capacitive load $C_L=1 \mathrm{pF}$, at $R_L=10 \mathrm{k}\mathsf{\Omega }$ and $R_L\to \infty$, VB settling times are $t_{s\alpha 1}=11.9 \mathrm{ns}$ and $t_{s\alpha 2}=15.1 \mathrm{ns}$, respectively. The CB settling time is also small, $t_{s\beta }=3.1 \mathrm{ns}$.

Variations in the process, supply voltage, and temperature have been investigated through PVT corner analysis, considering a ±10% variation at the power supply for temperatures of −20 °C, 25 °C, and 80 °C (shown in

Table 3. PVT Simulation results for $VCI{I}^{-}$ *.

Parameter	P				V(VDD − VSS)		T (°C)
	FF	FS	SF	SS	±0.99 V	±0.81 V	−20	25	80
rY [Ω]	107.6	113.4	108.2	112.3	101.8	123.3	110.1	110.3	116.4
LY [µH]	2.05	2.37	2.27	2.60	2.22	2.44	2.20	2.32	2.56
rX [kΩ]	642.4	788.0	734.4	896.0	762.9	756.8	744.3	759.1	772.0
CX [fF]	40.64	43.59	40.36	43.50	41.35	42.97	41.20	41.95	42.64
rZ [Ω]	3.65	4.42	5.64	7.59	2.84	12.2	6.62	4.90	4.40
LZ [µH]	1.16	1.60	1.89	2.89	1.09	3.52	2.26	1.74	1.54
β	1.151	1.118	1.121	1.091	1.145	1.091	1.110	1.119	1.128
α	0.9996	0.9995	0.9994	0.9992	0.9997	0.9998	0.9993	0.9995	0.9995
THDY-X [%]	1.32	1.21	1.20	1.09	1.19	1.23	1.09	1.19	1.30
THDX-Z [%]	0.39	0.29	0.28	0.32	0.37	1.45	0.28	0.29	0.45
Pdiss [µW]	186.9	159.6	153.5	137.6	218.5	118.8	141.5	155.9	174

* I_m = 100 µA.

).

Table 3 shows that the $\alpha$ and $\beta$ parameters are robust, while the series resistance $r_Z$ and inductance $L_Z$ change the most. It is a consequence of the dependence of the quiescent current of the VB output stage on the supply voltage.

The nominal inductive reactances of the Y and Z terminals at 1 MHz are $X_{LY}=2\pi f{L}_Y=13 \Omega$ and $X_{LZ}=2\pi f{L}_Z=11 \Omega$, respectively. Comparing these values with the resistances $r_Y$ and $r_Z$, it is concluded that series inductance has very little effect on the Y input, while its effect on the Z output is large. Even so, the impedance of the Z output is relatively small, as a magnitude of 50 Ω is reached at about 4.5 MHz.

At the minimum supply voltage of $\pm 0.81 \mathrm{V}$, distortions $TH{D}_{X-Z}$ increase due to clipping the sine wave at the output.

Table 4. Monte Carlo simulation results for $VCI{I}^{-}$.

MC	rY [Ω]	LY [µH]	rX [kΩ]	Cx [fF]	rZ [Ω]	LZ [µH]	β	α	Pdiss [µW]	THDY-X [%]	THDX-Z [%]
Mean	111.2	2.091	752.1	41.47	5.014	1.751	1.120	0.9994	157	1.204	0.2866
Sigma	2.220	0.079	28.42	0.629	0.606	0.233	7.827 m	52.35 μ	6.99	28.07 m	10.837 m

shows the results of the Monte Carlo simulation on 500 samples. It can be seen from this Table that VCII is quite immune to the statistical variation of the parameters.

Table 5. Comparison with other relevant previously reported class AB VCII topologies *.

	[38]	[35]	[36]	[37]	Proposed	Proposed
VCII type	positive	positive	positive	Positive	positive	negative
Class	AB	AB	AB	AB	AB	AB
α	0.94	0.972	1	0.953	0.9994	0.9994
αBW [MHz]	191.5	50	100	50	173.2	173.2
β	1	0.996	0.987	0.993	1.044	1.119
βBW [MHz]	86.6	165	169.7	11	311.1	298.3
rY [Ω]	602	23	1.88 k	973	97.48	110.4
rX [Ω]	591 k	522 k	273.8 k	120 k	804.4 k	759.7 k
rZ [Ω]	370	160	1.75 k	217	4.86	4.86
Pdiss [µW]	70	120	179	393	136.6	157
THDY-X [%]	-	1.1	1	2.4	1	1.19
Ixpp @ 1 MHz		0.5 mA	1.22 mA	10 mA	2 mA	200 μA
THDX-Z [%]	-	2.4	1	3.9	0.29	0.29
Vxpp @ 1 MHz		1.6 V	1.78 V	0.8 V	1.5 V	1.5 V
Number of transistors	19	37	12	38	31	35
Technology	0.18 μm	0.15 μm	0.18 μm	0.18 μm	0.18 μm	0.18 μm
Rail-to-rail	yes	yes	Yes	No	yes	yes

* The circuits in all reference works are powered by ±0.9 V.

shows the characteristics of the relevant published VCII. Due to the channel-length modulation effect (λ effect) in the current mirrors $M_7-M_{14}$, the CB ${\mathrm{VCII}}^{-}$ distortions are relatively large. When longer channels are used, these distortions are smaller, but the CB bandwidth is lower. The channel length $2L_{\min }=0.36 \mathsf{\mu }\mathrm{m}$ was selected as a compromise in the proposed CB design. When $M_{11}-M_{14}$ are removed from the circuit and the drains $M_9$ and $M_{10}$ are shorted to the output, the $VCI{I}^{+}$ current buffer is obtained. To obtain a small offset of CB $VCI{I}^{+}$, the channel width $M_{2,4,6}$ should be $W_{2,4,6}=11.77 \mathsf{\mu }\mathrm{m}$. Its current gain is slightly higher than one, $\alpha =1.044$, but it is much more linear. When the Y input has the same excitation as the CB ${\mathrm{VCII}}^{-}$, at a current of $2 {\mathrm{mA}}_{\mathrm{pp}}$, a THD of 1% is obtained. In the simulation, the offset voltage of the X port is $V_{XDC}=6.64 \mathsf{\mu }\mathrm{V}$, and other $VCI{I}^{+}$ parameters are shown in Table 5. Compared to this, only reference [37] has a better linearity. In that VCII, a λ effect cancellation circuit was used to obtain a more linear CB at the cost of increased power dissipation.

References [35,38] have lower power dissipation than the proposed VCII. When the class A CB and the class AB VB are supplied from the same voltage, $\pm 0.9 \mathrm{V}$, the VB in [38] is not rail-to-rail. Rail-to-rail functionality is obtained using a charge pump that increases the supply voltage of the output stage, and additional drivers are needed. The bandwidth of the proposed VB is slightly lower than in [38], while the bandwidth of the CB is significantly higher. In [35], CB and VB are rail-to-rail and class AB, and VB has two complementary differential amplifiers at the input. The differential amplifiers are switched on depending on the VCM voltage. The proposed VCII has slightly higher power dissipation but much higher bandwidth on both VCII stages.

Of all referenced VCIIs, reference [32] has the lowest consumption of only 38 uW. That $VCI{I}^{-}$ consists of a class AB CB and a push-pull class B VB, has a $\pm 1.65 \mathrm{V}$ power supply, and is part of a Schmitt Trigger. Due to the lack of other relevant parameters, the comparison with it in Table 5 is omitted.

Compared to other reference works, the proposed VCII has the best VB linearity, the highest input resistance at the X terminal, and the smallest sum of series resistances at the Y and the Z terminals. It also has a relatively low power consumption. The disadvantage of the proposed solution is a relatively low linearity of the CB ${\mathrm{VCII}}^{-}$, which is a consequence of implementing ${\mathrm{VCII}}^{-}$ by cascading current mirrors to invert the current.

3. Proposed Relaxation Oscillator with VCII⁻

A new VCII application, an implementation of a NIC-based relaxation oscillator, will be presented. Voltage conveyors can be used to perform the function of a NIC. The voltage-driven NIC is already used in some applications, for example, in VCII-based grounded C multiplier circuits with negative multiplication factors [8]. For the implementation of relaxation RC oscillators, NIC static characteristics should be uniquely defined for the current that controls the operation of the oscillator [47].

3.1. Circuit Description and Equivalent Model

Figure 9 shows a realization of current-driven NIC implemented with ${\mathrm{VCII}}^{-}$. Since the voltage at the X terminal is $v_X=-Z_X\cdot i_X$ and, according to (1), an ideal case is $i_X=-i_Y$, $v_Z=v_X$, $v_Y=0$, the input impedance between the Z and Y terminals is:

$$Z_{in}={\displaystyle \frac{v_Z-v_Y}{i_{IN}}}={\displaystyle \frac{v_X}{-i_Y}}=-Z_X.$$

(9)

At low frequencies, the parasitic impedance at terminal X is resistance $r_X$, which means that the equivalent impedance is negative $Z_{in}=-r_X$, even without additional impedance at terminal X. This means that the NIC static characteristic around the coordinate origin has an inherently high negative resistance (Equation (4)), which is a very useful feature for the implementation of the active part of an oscillator since it ensures the reliable startup of oscillations. As we shall see later, for large absolute values of control current, NIC static characteristics have positive slopes because some transistors will be cut off.

A schematic diagram of the proposed relaxation oscillator based on a ${\mathrm{VCII}}^{-}$ is shown in Figure 10a. Because of the small Y impedance, the output voltage is simply converted into current, and the output voltage buffer allows it to easily drive an external load. The active part of the oscillator is a current-driven NIC with current-voltage characteristic $v=f(i)$, which can be approximated by three linear segments, see Figure 10b. To better control the shape of the static characteristic of the NIC, we added a serial resistor $R_F$. The network of the oscillator contains a capacitor, but in the model, we have included the parasitic inductance at the Y or the Z terminal to explain fast current changes in the further analysis of the relaxation oscillator. The typical role of inductance is hindering abrupt current changes, but if we have a small inductance ($L_Z\to 0$), it allows very fast current changes ($d{i}_{L_Z}/dt\to \infty$) [48], i.e., the “jump” of current i in the relaxation oscillator in Figure 10a. For the sake of simplicity of analysis, the other parasitic elements can be ignored. This model and analysis are very similar to those of the relaxation oscillator based on the CCII described in [40], so they will be repeated in this paper briefly.

Using the notation from Figure 10a, the behavior of this circuit can be described as:

$${\displaystyle \frac{di}{dt}}=-{\displaystyle \frac{1}{L_Z}}f(i)+{\displaystyle \frac{1}{L_Z}}{v}_C,$$

(10)

$${\displaystyle \frac{d{v}_C}{dt}}=-{\displaystyle \frac{1}{C}}i.$$

(11)

Since the quiescent point of this circuit is at the coordinate origin where the characteristic $f(i)$ can be approximated by $R_{II}=-R_n$, the real part of the characteristic equation solution is positive for $R_n,L_Z>0$ [47]. Thus, it can be concluded that the oscillation startup in this oscillator is always reliable and does not depend on the value of the capacitance in the timing network. It is assumed that the negative slope segment on NIC characteristics exists. If the condition:

$$R_n>\sqrt{{\displaystyle \frac{4L_Z}{C}}}$$

(12)

is fulfilled, the characteristic equation solutions are real and positive, and the operating point is moving along a linear trajectory from the coordinate origin until the point where the current is limited by the NIC static characteristic. The limit cycle of the oscillator is almost immediately reached in the first period, and there is a direct oscillation startup. This behavior is typical of the relaxation oscillators, and it can be achieved for large values of $C$. If condition (12) is not fulfilled, the solutions are conjunctive-complex, and the limit cycle will be set up after several periods of oscillation [47]. In that case, the circuit behaves as a nearly sinusoidal oscillator, so we will not analyze it in this paper.

To determine $R_n$, i.e., the equivalent resistance seen by the capacitor $C$ at the quiescent operating point, we will use the circuit based on the VCII model for small signals at low frequencies (Figure 11). If we assume that the X terminal is unloaded, from the equations:

$$v_t=v_t^{+}-v_t^{-}=\alpha v_X+r_Z{i}_t+\left(r_Y+R_F\right)i_t,$$

(13)

$$v_X=-\beta i_Y{r}_X=\beta r_X{i}_t ,R_X\to \infty ,$$

(14)

we obtain the equivalent resistance

$$R_t=v_t/i_t=\alpha \beta r_X+r_Y+r_Z+R_F.$$

(15)

This resistance can be negative if we use a negative type VCII ($\beta <0$), and the following condition is fulfilled:

$$\left|\alpha \beta r_X\right|>r_Y+r_Z+R_F.$$

(16)

Since $r_X$ is the high output resistance of CB, both gains are approximately equal to unity and $r_Y,r_Z$ are low resistances (Table 5). This condition is easy to fulfill even for relatively high resistance $R_F$. According to the markings in Figure 10b and this analysis, the slope of segment II with negative resistivity is:

$$R_{II}=r_Y+r_Z+R_F-\left|\alpha \beta r_X\right|\approx R_F-r_X.$$

(17)

However, $R_F$ affects other characteristics of the oscillator, so the slope with negative resistance can be independently adjusted by external resistance $R_X$ (Figure 11). In that case, $r_X$ should be replaced with $r_X\left|\right|R_X$ in the previous analysis.

3.2. Estimation of the Oscillation Period

The period of oscillations is equal to the time needed for the operating point to go once through the limit cycle. It is a characteristic of relaxation oscillators that the operating point has “slow” and “fast” motions during the limit cycle. When the operating point reaches the circuit’s static characteristics at the beginning, it continues in “slow” motion on the positive slope segment until the breaking point of that segment. After that, it has to “jump” to the other positive slope segment of the static characteristics. This means that there is an instant current change controlling the oscillator operation while the voltage is constant. The current “jump” is made possible by the parasitic inductance $L_Z$ of a small value, and the voltage is kept constant by capacitance $C$. We can consider that these jumps are instantaneous and neglect them in the calculations of the period of oscillations. Thus, the period of oscillations is the time when the operating point is on segments I and III of the characteristics shown in Figure 10b:

$$T={\displaystyle \underset{c}{\oint }dt\approx }\Delta t_I+\Delta t_{III}.$$

(18)

For the analysis of slow motions, the parasitic element can be ignored, $L_Z=0$, and the static characteristic can be approximated as $f(i)=R_I\cdot i$ or $f(i)=R_{III}\cdot i$. Under these assumptions, from (11) and (18), the period of oscillation can be easily calculated:

$$T=C{R}_I\ln {\displaystyle \frac{I_1}{I_2}}+C{R}_{III}\ln {\displaystyle \frac{I_3}{I_4}}.$$

(19)

The period depends on the capacitance $C$ and the shape of the NIC static characteristic: the slope of segments I and III and the location of the turning points [47]. To simplify the analysis, we can assume that the characteristic is symmetrical, and the slopes of these segments are equal, $R_I=R_{III}$. In that case, $V_1=-V_2$, $I_2=-I_4$, $I_1=-I_3$ and:

$${\displaystyle \frac{I_1}{I_2}}={\displaystyle \frac{I_3}{I_4}}={\displaystyle \frac{R_{III}-2R_{II}}{R_{III}}}.$$

(20)

According to (19), the oscillation period is:

$$T=2C{R}_{III}\ln {\displaystyle \frac{I_3}{I_4}}=2C{R}_{III}\ln {\displaystyle \frac{R_{III}-2R_{II}}{R_{III}}}.$$

(21)

3.3. Analysis and Design of the Proposed Relaxation Oscillator

In the steady-state oscillation process, due to the rail-to-rail feature, the maximum and the minimum VB output voltages are approximately $V_{DD}$ and $V_{SS}$, respectively. For the initial observation time, we will take the state when the output Z has a minimum voltage. Then, there is also a low voltage on the X terminal and the transistor $M_{14}$ is in the triode region. The current $i_Y$, which is simultaneously the current of the capacitor $C$, increases, as does the current $-i_X$. When the current $i_X$ reaches the value that drives $M_{14}$ out of the triode region, both $M_{13}$ and $M_{14}$ are in saturation, a positive feedback loop is established in the circuit that drives $M_{13}$ into the triode region, and the output Z goes from a low to a high voltage level. The voltage on the capacitor $C$ cannot be changed instantaneously, so this fast change in the voltage $v_Z$ causes a fast change in the current $i_Y$, after which the current falls exponentially until $M_{13}$ exits the triode region. Then, again, both $M_{13}$ and $M_{14}$ are in saturation, so due to the strong positive feedback, the voltage at the X terminal drops sharply from a high to a low voltage level, driving the transistor $M_{14}$ into the triode region and fast-changing the voltage $v_Z$ from a high to a low voltage level. The current $i_Y$ has a steep downward change and then rises exponentially until it reaches a threshold that again drives the transistor $M_{14}$ out of the triode region, thus ending one period of the steady-state operation.

Figure 12 shows the periodic steady-state diagrams of the voltage $v_Z$ and $v_X$, as well as the current $i_Y$ in the oscillator with $V_{DD}=-V_{SS}=0.9 \mathrm{V}$, $R_F=22 \mathrm{k}\mathsf{\Omega }$, and $C=6.5 \mathrm{pF}$.

To adjust the shape of the static characteristic of the active part of the oscillator, we need to determine the slope of the segments with positive resistivity (segments I and III in Figure 10b). In these areas, the output Z is in voltage saturation, so the slopes of these segments are:

$$R_I=R_{III}=r_Y+r_{Zsat}+R_F,$$

(22)

where $r_{Zsat}$ is the output resistance of the saturated output Z. Note that $R_F$ affects these slopes. We previously determined the expression for the negative slope on segment II (Equation (17)) and explained the effects of resistances $R_F$ and $R_X$.

Figure 13 shows the resistance seen by the capacitor C for two feedback resistances, $R_{F1}=10 \mathrm{k}\mathsf{\Omega }$ and $R_{F2}=22 \mathrm{k}\mathsf{\Omega }$, and two external resistances, $R_X=100 \mathrm{k}\mathsf{\Omega }$ and $R_X\to \infty$. The slope in segment II must be negative, and this will be fulfilled when it is $R_{F1,2}<r_X\left|\right|R_X$. Because of the large CB output resistance $r_X$, the slope in segment II changes slightly with the change in $R_F$.

Assuming $r_Y,r_Z,r_{Zsat}<<R_F$ and combining (17), (21), and (22), the oscillation period for circuits with unloaded X terminal is:

$$T=2C{R}_{III}\ln {\displaystyle \frac{R_{III}-2R_{II}}{R_{III}}}\approx 2C{R}_F\ln \left({\displaystyle \frac{2\left|\alpha \beta r_x\right|}{R_F}}-1\right).$$

(23)

With external resistance $R_X$, the oscillation period is:

$$T\approx 2C{R}_F\ln \left({\displaystyle \frac{2\left|\alpha \beta \left(r_x\left|\right|R_X\right)\right|}{R_F}}-1\right),$$

(24)

and in the idealized case, $\alpha =1$ and $\beta =-1$ become:

$$T\approx 2C{R}_F\ln \left({\displaystyle \frac{2\left(r_x\left|\right|R_X\right)}{R_F}}-1\right).$$

(25)

Due to extra resistance $R_X$, the oscillation frequency can be adjusted better, thus making the oscillator more robust to PVT variations. The same expression for the frequency of the idealized relaxation oscillator $(r_X\to \infty )$, but in a different way, was obtained in reference [49].

The first step in relaxation oscillator design is to ensure the oscillations start. According to (16) and the VCII parameters shown in Table 5, we have chosen $R_F=22 \mathrm{k}\mathsf{\Omega }$ and $R_X=100 \mathrm{k}\mathsf{\Omega }$. Since $R_F$ determines the slope of positive segments of the static characteristic, i.e., determines the location of the turning points (Figure 10b), with the chosen value, we limited the current to approximately 70 µA. Finally, choosing the capacitance $C$, the oscillation frequency $f_0$ can be determined according to (25). For example, for $C=11.5 \mathrm{pF}$, the estimated operating frequency is 1.013 MHz, while it is 1.049 MHz when simulated.

The dependence $f_0$ as a function of the capacitance $C$ is shown in Figure 14. The same picture shows the specified dependency obtained by simulation and the dependence of the relative error of the frequency estimation on the frequency.

The simplified Formula (25) for determining the oscillation frequency shows good agreement with simulations, as shown in Figure 14. At low frequencies, the relative error has an offset because of the influence of parasitic series resistances. As the frequency is increased, hysteresis appears in the controlled impedance $v=f(i)$. As Figure 15 shows, the width of hysteresis increases when the working frequency increases. Neglecting the transition time yields a simplified expression for the oscillation period. With increasing frequency, the time that the oscillator spends in the zone with negative impedance is no longer negligible, and the frequency decreases to the idealized characteristic. This is mostly due to the influence of the Y and Z inductive reactances, which decrease the rate of change of the capacitor current when the oscillator switches from one state to another.

To decrease the CB distortion, $R_F$ is adjusted to limit the maximum current of the Y input. The series inductances $L_Y$ and $L_Z$ additionally limit the fast-change $i_Y$ and thus the CB distortion.

Figure 16a shows the periodic steady-state diagrams of the voltage $v_Z$ and $v_X$ and the current $i_Y$ when $C=0.79 \mathrm{pF}$, while other parameters are unchanged, being $R_F=22 \mathrm{k}\mathsf{\Omega }$ and $R_X=100 \mathrm{k}\mathsf{\Omega }$. This sets the oscillation frequency to 10 MHz. The rise and fall times of the current $i_Y$, when the oscillator switches from one state to another, are determined from the $i_Y$ diagram as $t_r\approx t_f=12.5 \mathrm{ns}$. When these times are added to the idealized charging and discharging times, the estimated (24) and simulated frequencies are approximately the same. Figure 16b shows the dependence of the voltage on the capacitor as a function of the capacitor current at the oscillation frequency, that is, the phase portrait of the oscillator at 10 MHz. It is observed that the oscillator enters the steady state after one period of oscillation.

In transition mode, when the supply voltage reaches ±0.5 V, the oscillations begin to establish and reach their final amplitude at ±0.9 V. When the solutions of the characteristic equation are real and positive (condition (12)), i.e., for the relaxation type of oscillations, the startup time is approximately equal to one oscillation period (Figure 16b). If the solutions of the characteristic equation are conjunctive-complex, the startup time is several periods (we did not analyze it in this paper because it is a nearly sinusoidal oscillator).

3.4. Simulation Results for the Relaxation Oscillator

Table 6. Oscillation frequency, power dissipation, and phase noise vs. PVT variation.

Parameter	P				V(VDD − VSS)		T (°C)
	FF	FS	SF	SS	±0.99 V	±0.81 V	−20	25	80
f0 [MHz]	1.025	1.046	1.051	1.049	0.978	1.067	1.056	1.056	1.027
Pdiss [μW]	216.8	210.4	209.8	205.7	229.3	192.6	207.8	209.9	213.1
PN [dBc/Hz]	−85.70	−86.41	−85.79	−86.76	−86.58	−86.03	−85.97	−86.05	−86.53

shows the oscillating frequency after standard PVT variation in the oscillator with $R_F=22 \mathrm{k}\mathsf{\Omega }$, $R_X=100 \mathrm{k}\mathsf{\Omega }$, and $C=11.5 \mathrm{pF}$. Apart from $C_C$, which is implemented as a MIM capacitor, the other passive components are implemented outside the chip. The nominal frequency of oscillation is $f_0=1.049 \mathrm{MHz}$, while its maximum change is 6.6%. The power dissipation for the unloaded output is entered in the same Table and changes by a maximum of 17.5% compared to the circuit with typical parameters. Without the external resistor $R_X$, similar results are obtained, and the frequency change is slightly higher and amounts to 6.8%. After the Monte Carlo simulation on 500 samples, mean values of $f_0=1.0493 \mathrm{MHz}$ and $P_{diss}=210.2 \mathsf{\mu }\mathrm{W}$ and standard deviations of ${\sigma }_f=4.512 \mathrm{kHz}$ and ${\sigma }_P=1.504 \mathsf{\mu }\mathrm{W}$ were obtained.

Figure 17 shows the phase noise of the oscillator at 1.049 MHz, with three power supplies ±0.81 V, ±0.9 V, and ±0.99 V. At the offset frequency of 100 kHz, the phase noise is about $-86 \mathrm{dBc}/\mathrm{Hz}$ with a change of $0.55 \mathrm{dBc}/\mathrm{Hz}$. Under the same conditions, with a temperature change from −20 °C to 80 °C, the phase noise changes by approximately $0.5 \mathrm{dBc}/\mathrm{Hz}$. Table 6 shows the phase noise values for PVT variations, and the maximum change of phase noise is about $1 \mathrm{dBc}/\mathrm{Hz}$.

As Table 6 shows, the relative changes in frequency, power dissipation, and phase noise are relatively small and amount to ${\delta }_f=8.5\%$, ${\delta }_P=17.4\%$, and ${\delta }_{PN}=1.2\%$, respectively.

When the frequency of oscillation increases, so does the influence of parasitic Y and Z inductances and X capacitance. The selectivity of the positive feedback circuit is improved, and the rectangular pulses at the Z output change from square wave via trapezoidal wave to nearly sinusoidal. The maximum frequency for generating square-wave signals is around 10 MHz, and the power dissipation is 190 μW. The oscillator can regularly oscillate up to about 40 MHz in a nearly sinusoidal mode.

Table 7. Comparison of the proposed square-wave generator with previously reported generators.

Ref	[50]	[51]	[52]	[53]	[54]	[55]	Proposed
ABB	CCII	FTFN	ZC-CG-VDCC	CCCII	MO-CFDITA	CA	VCII
Num. of ABB	1	1	1	1	1	1	1
Passive elem.	3R, 1C	2R, 1C	2R, 1C	2R, 1C	1C	-	2R, 1C
Max Op. Freq.	50 MHz	5 MHz	4.385 MHz	4.99 MHz	50 MHz	7 MHz	10 MHz
Number of transistors	17	23	52	13	21	33	35
Area [μm2]	-	-	-	-	-	50,000	1250
Power supply	±0.75 V	±1.65 V	±1.0 V	±1.0 V	±1.25 V	±0.75 V	±0.9 V
Power dissip.	0.750 mW	2.81 mW	6.28 mW	0.6 mW	1.45 mW	11 μW	0.19 mW
FOM [kHz/μW]	66.7	1.78	0.70	8.32	34.5	636.36	52.6

FTFN, four-terminal floating nullor; ZC-CG-VDCC, Z-copy controlled gain voltage differencing current conveyor; CCCII, current controlled current conveyor; MO-CFDITA, multiple-output current follower differential input transconductance amplifier; CA, current amplifier.

gives comparative characteristics of individual square-wave generators. From many previously published works, designs by integrated oscillators and a similar achieved oscillation frequency were selected.

For comparison, the figure of merit (FOM) of the oscillator was used as the ratio of the maximum oscillation frequency to the power dissipation. The oscillator in [50] has a higher FOM than the proposed oscillator. Although it is simpler to implement and has fewer transistors, the square wave generator in [50] requires three resistors and one capacitor. The output has a high output impedance, so an additional buffer is required. In [51], the oscillator has a low output resistance, significantly higher power consumption, and a significantly lower FOM. The generator in [52] provides square wave outputs in the form of voltage and current that can also be used to output a differential square wave. It can electronically control the frequency, and due to the higher power consumption, this one also has a lower FOM than the proposed one. In [53], an oscillator with a CCCII is used. Although the circuit is simple, it has a relatively high power consumption and an output with high output resistance. Reference [54] shows a generator consisting of one MO-CFDITA and only one grounded capacitor, making the proposed generator circuit suitable for implementation in an integrated circuit. Although it has a high oscillation frequency, this generator provides an output square wave in the current mode. Of all the oscillators in Table 7, the circuit [55] has the highest FOM, but also has a current output and large die area, which is a consequence of implementing passive components in the chip. The circuits in [51,53] have a layout, but the area information is missing.

By comparing the proposed square wave oscillator with the results from previously published papers in Table 7, it can be concluded that this oscillator has a relatively high FOM, but also a great advantage in a small output impedance.

4. Conclusions

A CMOS rail-to-rail $VCI{I}^{-}$ is designed with a power consumption of 157 μW, and a current and voltage buffer bandwidth of 298.3 MHz and 173.2 MHz, respectively. With a rail-to-rail 1 MHz sinusoidal excitation, total harmonic distortions in the voltage buffer are 0.29%. Distortions in the current buffer $VCI{I}^{-}$ at a current amplitude of 200 μA are 1.19%, while in $VCI{I}^{+}$, similar distortions are obtained at 10-fold higher currents. The dynamic characteristics of $VCI{I}^{-}$ were tested in a relaxation oscillator. Due to the wide bandwidth of the current and voltage buffer and a high slew rate, it was shown that a low-power relaxation oscillator with a frequency of up to 10 MHz and good stability can be made. The application of the realized rail-to-rail $VCII$ in our further research will focus on low-voltage, low-power energy harvesting applications. Future research will aim to improve the linearity of the low-power current buffer using feedforward and feedback techniques. Since the proposed VCIIs have good driving capabilities, they can drive switching transistors in high-frequency soft-switching DC-DC and switched capacitor converters [38,56].