Enhancing Security and Power Efficiency of Ascon Hardware Implementation with STT-MRAM
Abstract
:1. Introduction
2. Our Contribution
- A duplicated-complemented permutation for which the internal state S and its complemented value are computed in parallel.
- A Differential Novolatile Flip-Flops (DNVFF) adding the nonvolatility property to the internal state registers of the duplicated-complemented permutation. This DNVFF combines two CMOS FF and a nonvolatile circuitry.
- Saving the states S and in the penultimate round of each encryption before potential attacks. Faults are detected by xoring the tag T with its inverted value . If a fault is detected, faulty states can be corrected, thus preventing an attacker from exploiting injected faults. To assess the effectiveness of the proposed countermeasure, we have performed Statistical Ineffective Fault Analysis (SIFA) [11] and Subset Fault Analysis (SSFA) [7] on both unprotected and protected version of the cipher.
- Reducing the dependency between manipulated data and power consumption thanks to the duplicated-complemented permutation, which makes it more difficult to recover the key by means of side-channel analysis. We have also conducted both a Correlation Power Analysis (CPA) and Differential Power Analysis (DPA) [5] on Ascon. These evaluations have been performed through power analysis simulations.
3. Background and Related Work
3.1. Description of Ascon
3.2. STT-MRAM
3.3. Statistical Ineffective Fault Analysis (SIFA)
3.4. Subset Fault Analysis (SSFA)
3.5. Side-Channel Attacks
3.6. Related Work
4. Proposed Solution
4.1. Core Idea
4.2. Differential Nonvolatile Flip-Flop Design
- CMOS FFs are based on transmission gate DFF triggered by a rising edge of the clock. When the asynchronous reset is asserted, the output is forced to 0.
- When the write signal is enabled, both and are stored into and . MTJs are always in opposite states. As the memory is nonvolatile, information is retained even if power is removed.
- When the read signal is enabled, nodes are discharged through pass transistors. Depending on MTJ resistance values, two nodes will be forced to 0 and two nodes will be forced to 1. The read operation can only be activated if and only if the clock signal is low.
4.3. Protected Ascon Implementation
- Interchange all 0 s with 1 s, and all 1 s with 0 s;
- Change OR gates into AND gates, and AND gates into OR gates;
- Convert XOR gates to XNOR gates, and XNOR gates to XOR gates.
5. Security Evaluation
5.1. Simulation Flow for Fault-Based Attacks
5.2. SIFA
- Case #1: Bit-reset on bits for each pair of S-Boxes ;
- Case #2: Bit-set on bits for each pair of S-Boxes ;
- Case #3 (protected version only): Bit-reset on bits for each pair of S-Boxes ;
- Case #4 (protected version only): Bit-reset on bits and bit-set on bits for each pair of S-Boxes .
5.3. SSFA
- Case #1: Bit-reset on input bit of each S-Box j;
- Case #2 (protected version only): Bit-reset on input bits of each S-Box j;
- Case #3 (protected version only): Bit-reset on input bit and bit-set on input bit of each S-Box j.
5.4. Power Analysis Attacks
6. Discussion
7. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
Abbreviations
AP | Antiparallel |
ASIC | Application Specific Integrated Circuit |
CMOS | Complementary Metal Oxide Semiconductor |
CPA | Correlation Power Analysis |
DK | Design Kit |
DNVFF | Differential Nonvolatile Flip-Flop |
DPA | Differential Power Analysis |
EDA | Electronic Design Automation |
FM | Ferromagnetic |
FSM | Finite State Machine |
GE | Gate Equivalent |
HW | Hamming Weight |
IoT | Internet of Things |
LWC | Lightweight Cryptography |
MRAM | Magnetic Random Access Memory |
MTJ | Magnetic Tunnel Junction |
NIST | National Institute of Standards and Technology |
NVFF | Nonvolatile Flip-Flop |
P | Parallel |
SEI | Squared Euclidean Imbalance |
SR | Success Rate |
SIFA | Statistical Ineffective Fault Analysis |
SSFA | Subset Fault Analysis |
TMR | Tunnel Magnetoresistance Ratio |
WDDL | Wave Dynamic Differential Logic |
References
- Alioto, M.; Shahghasemi, M. The Internet of Things on Its Edge: Trends Toward Its Tipping Point. IEEE Consumer Electron. Mag. 2018, 7, 77–87. [Google Scholar] [CrossRef]
- NIST FIPS PUB 197; Advanced Encryption Standard (AES). National Institute of Standards and Technology, U.S. Department of Commerce: Gaithersburg, MD, USA, 2001.
- Dobraunig, C.; Eichlseder, M.; Mendel, F.; Schläffer, M. Ascon v1.2: Lightweight Authenticated Encryption and Hashing. J. Cryptol. 2021, 34, 33. [Google Scholar] [CrossRef]
- Bernstein, D.J. CAESAR Competition. 2014. Available online: https://competitions.cr.yp.to/index.html (accessed on 1 September 2024).
- Samwel, N.; Daemen, J. DPA on hardware implementations of Ascon and Keyak. In Proceedings of the Computing Frontiers Conference, CF’17, Siena, Italy, 15–17 May 2017; ACM: New York, NY, USA, 2017; pp. 415–424. [Google Scholar] [CrossRef]
- Ramezanpour, K.; Ampadu, P.; Diehl, W. FIMA: Fault Intensity Map Analysis; Springer: Cham, Switzerland, 2019; pp. 63–79. [Google Scholar] [CrossRef]
- Joshi, P.; Mazumdar, B. SSFA: Subset fault analysis of ASCON-128 authenticated cipher. Microelectron. Reliab. 2021, 123, 114155. [Google Scholar] [CrossRef]
- Sanislav, T.; Mois, G.D.; Zeadally, S.; Folea, S.C. Energy Harvesting Techniques for Internet of Things (IoT). IEEE Access 2021, 9, 39530–39549. [Google Scholar] [CrossRef]
- Dieny, B.; Prejbeanu, I.L.; Garello, K.; Gambardella, P.; Freitas, P.; Lehndorff, R.; Raberg, W.; Ebels, U.; Demokritov, S.O.; Akerman, J.; et al. Opportunities and challenges for spintronics in the microelectronics industry. Nat. Electron. 2020, 3, 446–459. [Google Scholar] [CrossRef]
- Roussel, N.; Potin, O.; di Pendina, G.; Dutertre, J.; Rigaud, J. CMOS/STT-MRAM Based Ascon LWC: A Power Efficient Hardware Implementation. In Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2022, Glasgow, UK, 24–26 October 2022; IEEE: New York, NY, USA, 2022; pp. 1–4. [Google Scholar] [CrossRef]
- Ramezanpour, K.; Ampadu, P.; Diehl, W. A Statistical Fault Analysis Methodology for the Ascon Authenticated Cipher. In Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019, McLean, VA, USA, 5–10 May 2019; IEEE: New York, NY, USA, 2019; pp. 41–50. [Google Scholar] [CrossRef]
- Dobraunig, C.; Eichlseder, M.; Korak, T.; Mangard, S.; Mendel, F.; Primas, R. SIFA: Exploiting Ineffective Fault Inductions on Symmetric Cryptography. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2018, 2018, 547–572. [Google Scholar] [CrossRef]
- Tezcan, C. Truncated, Impossible, and Improbable Differential Analysis of ASCON. In Proceedings of the 2nd International Conference on Information Systems Security and Privacy, ICISSP 2016, Rome, Italy, 19–21 February 2016; Camp, O., Furnell, S., Mori, P., Eds.; SciTePress: Lisbon, Portugal, 2016; pp. 325–332. [Google Scholar] [CrossRef]
- Kocher, P.C.; Jaffe, J.; Jun, B. Differential Power Analysis; Springer: Berlin/Heidelberg, Germany, 1999; pp. 388–397. [Google Scholar] [CrossRef]
- Brier, E.; Clavier, C.; Olivier, F. Correlation Power Analysis with a Leakage Model; Springer: Berlin/Heidelberg, Germany, 2004; pp. 16–29. [Google Scholar] [CrossRef]
- Kharbouche-Harrari, M.; di Pendina, G.; Wacquez, R.; Dieny, B.; Aboulkassimi, D.; Postel-Pellerin, J.; Portal, J. Light-Weight Cipher Based on Hybrid CMOS/STT-MRAM: Power/Area Analysis. In Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, 26–29 May 2019; IEEE: New York, NY, USA, 2019; pp. 1–5. [Google Scholar] [CrossRef]
- Saha, S.; Jap, D.; Roy, D.B.; Chakraborty, A.; Bhasin, S.; Mukhopadhyay, D. A Framework to Counter Statistical Ineffective Fault Analysis of Block Ciphers Using Domain Transformation and Error Correction. IEEE Trans. Inf. Forensics Secur. 2020, 15, 1905–1919. [Google Scholar] [CrossRef]
- Baksi, A.; Kumar, V.B.Y.; Karmakar, B.; Bhasin, S.; Saha, D.; Chattopadhyay, A. A Novel Duplication Based Countermeasure to Statistical Ineffective Fault Analysis; Springer: Cham, Switzerland, 2020; pp. 525–542. [Google Scholar] [CrossRef]
- Bogdanov, A.; Knudsen, L.R.; Leander, G.; Paar, C.; Poschmann, A.; Robshaw, M.J.B.; Seurin, Y.; Vikkelsoe, C. PRESENT: An Ultra-Lightweight Block Cipher; Springer: Berlin/Heidelberg, Germany, 2007; pp. 450–466. [Google Scholar] [CrossRef]
- Jabeur, K.; Bernard-Granger, F.; Di Pendina, G.; Prenat, G.; Dieny, B. Comparison of Verilog-A compact modelling strategies for spintronic devices. Electron. Lett. 2014, 50, 1353–1355. [Google Scholar] [CrossRef]
- Prenat, G.; Jabeur, K.; Vanhauwaert, P.; di Pendina, G.; Oboril, F.; Bishnoi, R.; Ebrahimi, M.; Lamard, N.; Boulle, O.; Garello, K.; et al. Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing. IEEE Trans. Multi Scale Comput. Syst. 2016, 2, 49–60. [Google Scholar] [CrossRef]
- Coi, O.; Pendina, G.; Prenat, G.; Torres, L. Spin-Transfer Torque Magnetic Tunnel Junction for Single-Event Effects Mitigation in IC Design. IEEE Trans. Nucl. Sci. 2020, 67, 1674–1681. [Google Scholar] [CrossRef]
- Goodstein, R. Boolean Algebra; Dover Books on Mathematics; Dover Publications: Mineola, NY, USA, 2012. [Google Scholar]
- Groß, H.; Wenger, E.; Dobraunig, C.; Ehrenhöfer, C. Ascon hardware implementations and side-channel evaluation. Microprocess. Microsyst. 2017, 52, 470–479. [Google Scholar] [CrossRef]
- Tiri, K.; Verbauwhede, I. A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. In Proceedings of the 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), Paris, France, 16–20 February 2004; IEEE Computer Society: Washington, DC, USA, 2004; pp. 246–251. [Google Scholar] [CrossRef]
- IEEE STD 1800-2009; IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language. IEEE: Piscataway, NJ, USA, 2009; pp. 1–1285. [CrossRef]
- Soos, M.; Nohl, K.; Castelluccia, C. Extending SAT Solvers to Cryptographic Problems. In International Conference on Theory and Applications of Satisfiability Testing, Proceedings of the 12th International Conference, SAT 2009, Swansea, UK, 30 June–3 July 2009; Lecture Notes in Computer Science; Kullmann, O., Ed.; Springer: Berlin/Heidelberg, Germany, 2009; Volume 5584, pp. 244–257. [Google Scholar] [CrossRef]
- Dutertre, J.; Beroulle, V.; Candelier, P.; Castro, S.D.; Faber, L.; Flottes, M.; Gendrier, P.; Hély, D.; Leveugle, R.; Maistri, P.; et al. Laser Fault Injection at the CMOS 28 nm Technology Node: An Analysis of the Fault Model. In Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2018, Amsterdam, The Netherlands, 13 September 2018; IEEE Computer Society: Washington, DC, USA, 2018; pp. 1–6. [Google Scholar] [CrossRef]
- Park, J.; Anandakumar, N.N.; Saha, D.; Mehta, D.; Pundir, N.; Rahman, F.; Farahmandi, F.; Tehranipoor, M.M.; PQC-SEP: Power Side-Channel Evaluation Platform for Post-Quantum Cryptography Algorithms. Cryptology ePrint Archive, Paper 2022/527. 2022. Available online: https://eprint.iacr.org/2022/527 (accessed on 1 September 2024).
- Bottinelli, P.; Bos, J.W. Computational aspects of correlation power analysis. J. Cryptogr. Eng. 2017, 7, 167–181. [Google Scholar] [CrossRef]
- Guilley, S.; Chaudhuri, S.; Sauvage, L.; Graba, T.; Danger, J.L.; Hoogvorst, P.; Vong, V.N.; Nassar, M.; Flament, F. Shall we trust WDDL? In Future of Trust in Computing, Proceedings of the First International Conference Future of Trust in Computing 2008, Villach, Austria, 11–12 March 2008; Vieweg+Teubner: Wiesbaden, Germany, 2009; pp. 208–215. [Google Scholar] [CrossRef]
- Dobraunig, C.; Mangard, S.; Mendel, F.; Primas, R. Fault Attacks on Nonce-Based Authenticated Encryption: Application to Keyak and Ketje; Springer: Cham, Switzerland, 2019; pp. 257–277. [Google Scholar] [CrossRef]
- Yazigy, N.; Postel-Pellerin, J.; Marca, V.D.; Sousa, R.C.; Ribotta, A.L.; Pendina, G.D.; Canet, P. Real-time electrical measurements during laser attack on STT-MRAM. In Proceedings of the 2023 35th International Conference on Microelectronic Test Structure (ICMTS), Tokyo, Japan, 27–30 March 2023; pp. 1–6. [Google Scholar] [CrossRef]
- Zhang, F.; Lou, X.; Zhao, X.; Bhasin, S.; He, W.; Ding, R.; Qureshi, S.; Ren, K. Persistent Fault Analysis on Block Ciphers. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2018, 2018, 150–172. [Google Scholar] [CrossRef]
- Bagheri, N.; Sadeghi, S.; Ravi, P.; Bhasin, S.; Soleimany, H. SIPFA: Statistical Ineffective Persistent Faults Analysis on Feistel Ciphers. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022, 2022, 367–390. [Google Scholar] [CrossRef]
- Marchand, C.; O’Connor, I.; Cantan, M.; Breyer, E.T.; Slesazeck, S.; Mikolajick, T. FeFET based Logic-in-Memory: An overview. In Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2021, Montpellier, France, 28–30 June 2021; IEEE: New York, NY, USA, 2021; pp. 1–6. [Google Scholar] [CrossRef]
- Khan, R.S.; Noor, N.; Jin, C.; Scoggin, J.; Woods, Z.; Muneer, S.; Ciardullo, A.; Nguyen, P.; Gokirmak, A.; van Dijk, M.; et al. Phase Change Memory and Its Applications in Hardware Security; CRC Press: Boca Raton, FL, USA, 2017; pp. 93–114. [Google Scholar] [CrossRef]
- Rajendran, G.; Banerjee, W.; Chattopadhyay, A.; Aly, M.M.S. Application of Resistive Random Access Memory in Hardware Security: A Review. Adv. Electron. Mater. 2021, 7, 2100536. [Google Scholar] [CrossRef]
Parameters | Description | Value |
---|---|---|
D | MTJ diameter | 28 nm |
TMR at 0 V, 300 K | 1.5 | |
Parallel resistance (P state) | 4.87 kΩ | |
Resistance Area product at 0 V, 300 K | 3 Ω · | |
Thickness of the oxide barrier | 1.48 nm | |
Thickness of the free layer | 1.3 nm |
DNVFF design | IC 6.1.8 |
Electrical simulation | Spectre 20.1.0 |
Logical library (.lib/.db) | Liberate 21.1 (Spectre engine) Library Compiler R-2020.09 |
Physical library (.lef) | IC 6.1.8 |
Logical model (.v) | Verilog HDL |
Logical simulation | Questasim 2020.4 |
HDL language | VHDL |
Logical simulation language | Verilog/System Verilog |
Logical simulator | Questasim 2020.4 |
Synthesis | Design Compiler R-2020.09-SP4 |
Placement Routing Clock Tree Synthesis (CTS) | Innovus v20.13 |
Backend verifications | PVS 19.15 |
Parasitic extraction | Quantus 20.1.1 |
Timing analysis | PrimeTime R-2020.09-SP4 |
Power estimation | Voltus v20.13 |
GE: Gate Equivalent | Ascon Unprotected | Ascon Protected | |||
---|---|---|---|---|---|
Instances | GE | GE | |||
FSM | 130.1 | 265.7 | 204.3 | 417.3 | |
4-bit counter | 27.1 | 55.4 | 30.2 | 61.7 | |
Permutation | 3646.1 | 7447.1 | 10,549.4 | 21,547 | |
Cipher and tag registers | 1173.6 | 2397.1 | 1173.6 | 2397.1 | |
Toplevel clock tree | 24.5 | 50 | 38.7 | 79 | |
Control circuit (Figure 10) | - | - | 14.2 | 29 | - |
Verification | - | - | 146.2 | 298.6 | - |
Total | 5001.1 | 10,214.7 | 12,156.6 | 24,829.7 |
Naïve Duplicated- Complemented Ascon | Proposed Implementation | ||
---|---|---|---|
Stage | Energy (pJ) | Energy (pJ) | Δ (%) |
Initialization | 1568 | 1412.4 | 11 |
Associated data (64-bit) | 1871.5 | 1412.4 | 32.5 |
Unprotected Implementation | Proposed Implementation | |
---|---|---|
Case | Correct Key Found ? | Correct Key Found ? |
#1 | Yes | No |
#2 | Yes | No |
#3 | Not implementable | No |
#4 | Not implementable | Yes |
Unprotected Implementation | Proposed Implementation | |
---|---|---|
Case | Correct Key Found ? | Correct Key Found ? |
#1 | Yes | No |
#2 | Not implementable | No |
#3 | Not implementable | Yes |
Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content. |
© 2024 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
Share and Cite
Roussel, N.; Potin, O.; Di Pendina, G.; Dutertre, J.-M.; Rigaud, J.-B. Enhancing Security and Power Efficiency of Ascon Hardware Implementation with STT-MRAM. Electronics 2024, 13, 3519. https://doi.org/10.3390/electronics13173519
Roussel N, Potin O, Di Pendina G, Dutertre J-M, Rigaud J-B. Enhancing Security and Power Efficiency of Ascon Hardware Implementation with STT-MRAM. Electronics. 2024; 13(17):3519. https://doi.org/10.3390/electronics13173519
Chicago/Turabian StyleRoussel, Nathan, Olivier Potin, Grégory Di Pendina, Jean-Max Dutertre, and Jean-Baptiste Rigaud. 2024. "Enhancing Security and Power Efficiency of Ascon Hardware Implementation with STT-MRAM" Electronics 13, no. 17: 3519. https://doi.org/10.3390/electronics13173519