Use of Threshold Median Adjustment to Achieve Accurate Current Balancing of Interleaved Buck Converter with Constant Frequency Hysteresis Control

Abstract

This paper proposes a current balancing loop that is obtained using the threshold median adjustment (TMA-CBL) to achieve the accurate current balancing of an interleaved constant frequency hysteresis (CFH) buck converter. The CFH control is implemented with a frequency phase loop based on a threshold width adjustment (TWA-FPL). To ensure the loop’s stability and minimize the steady-state error, a multi-phase, coupled, small-signal model (MPC-SSM) is derived with a consideration of the coupling effect among the multiple phases. Furthermore, the current balancing error is analyzed in detail, with a consideration of the sensing resistance deviations in the loop. Finally, based on a 180 nm BCD process, a four-phase interleaved buck converter is fabricated to verify the effectiveness of the proposed TMA-CBL. The maximum current balancing error is within 0.68% when the sensing resistors are deviated by 5%.

1. Introduction

The demand for CPU power supplies continues to grow, necessitating power levels in the range of 100–200 W and slewing rates of ~A/ns [1,2]. In contrast, single-phase linear control buck converters typically achieve only ~A/µs and power levels below 10 W [3,4]. To meet these increasing demands, interleaved hysteresis control buck converters have been proposed [5,6], which significantly enhance the response speed and power output. However, two main challenges arise with this approach:

• The unpredictable switching frequency associated with conventional hysteresis control can lead to severe electromagnetic interference (EMI).
• Current imbalances among the phases reduce both the efficiency and lifespan of the system.

To maintain a constant switching frequency, periodic thresholds, like triangular waveforms or spike pulses, have been introduced into hysteresis control [7,8,9,10]. While these methods stabilize the frequency, they struggle to operate effectively over a broad range, potentially causing converter misconvergence. To address this limitation, phase-frequency-error-based methods have been developed to extend the switching frequency range [11,12,13,14,15,16,17]. These methods adjust the current-sensing slope, threshold width, or delay time based on the phase frequency error detected by a phase frequency detector (PFD), thereby regulating the switching frequency. However, implementing these constant frequency hysteresis (CFH) controls in interleaved buck converters remains challenging due to the absence of effective current balancing techniques in CFH controls.

The current balancing methods are typically categorized as either passive or active. Passive methods, including coupled inductors, temperature-dependent impedances, and passive impedance matching techniques [18,19,20,21], generally lack precision. For improved accuracy, active methods regulate equivalent impedance through duty cycle adjustments [22]. In some approaches, a single current threshold adjustment loop controls the inductor current for balancing [23,24,25]. However, these active methods are not well suited for interleaved CFH buck converters due to the dynamic nature of threshold width adjustments, which can inadvertently alter the switching frequency and exacerbate EMI issues. There are two issues in the existing research: 1. conventional hysteresis control cannot maintain a constant switching frequency over a wide load range, and 2. interleaved CFH buck converters based on the phase frequency error lack an effective current-balancing technique. These problems highlight the significant gaps in the current research, particularly regarding current balancing and maintaining a constant switching frequency in interleaved CFH buck converters.

To realize current balancing and CFH for interleaved buck converters, this paper proposes a frequency phase loop based on the threshold width adjustment (TWA-FPL), and a current-balancing loop based on the threshold median adjustment (TMA-CBL), as shown in Figure 1. The threshold width of the CFH buck converter is regulated by the PFD to maintain a constant switching frequency, while the threshold median is adjusted to achieve current balancing. To realize the threshold median adjustment, in each phase, a current-sensing resistor R_S and a capacitor C_S convert the inductor current per phase i_L into the sensing voltage v_S. Then, the sensing voltages of all the phases are averaged as the reference voltage v_CSB by resistor R_B, which is proportional to the average inductor current for all the phases. Finally, the threshold median v_TM of the hysteresis comparator is adjusted by the error between v_S and v_CSB.

The rest of this paper is organized as follows. In Section 2, the hysteresis comparator in the TWA-FPL is linearized so as to calculate the transfer function of the FPL. In Section 3, the TMA-CBL is proposed to realize current balancing for the interleaved CFH buck converter. Furthermore, the MPC-SSM is derived with a consideration of the coupling effect among the multiple phases. Section 4 presents the detailed circuit design of the control chip. Section 5 shows the layout and simulation results. Section 6 shows the prototype and experimental results. Section 7 concludes this paper. The abbreviations covered in this paper are listed at the last of the main text.

2. Linearization of Hysteresis Comparator in Threshold Width Adjustment-Based Frequency Phase Loop

To construct a model for the TWA-FPL, it is necessary to analyze the composition of the TWA-FPL, which is composed of a PFD, a charge pump (CP), and a hysteresis comparator, as shown in Figure 2. The PFD detects the phase error between the driving signal and the external clock, and the CP converts the phase error into the voltage v_TW. v_TW, as half of the threshold width, is introduced into the hysteresis comparison. The RC network, at the output of the CP, is used to compensate the TWA-FPL.

According to Figure 2, the small-signal model of the TWA-FPL is shown in Figure 3. In Figure 3, φ_clk and φ_d are the clock phase and driving signal phase, respectively. G_cfp is the transfer function of the RC compensator. F_φv is the transfer function of the hysteresis comparator, which is difficult to derive due to its non-linear behavior.

For the transfer function of the hysteresis comparator, its calculation should consider the driving signal phase response when the threshold width steps, as shown in Figure 4. The threshold width is adjusted so that the driving signal is in the same frequency and phase as the external clock. The left part of Figure 4 shows the relationship between the variation in the threshold width and the phase variation, and the specific transfer function is derived below. After one switching cycle, the increment of the time delay is given by

$$T={\displaystyle \frac{2\Delta v_{TW}{v}_{in}}{\left(v_{in}-v_{out}\right)v_{out}}}{R}_f{C}_f$$

(1)

where Δv_TW is the step amplitude of the threshold width. v_in and v_out are the input voltage and the output voltage. R_f and C_f are the feedback resistor and the capacitor.

Furthermore, according to (1), the linear approximation of the driving signal’s phase variation is given by

$$\Delta {\phi }_d\left(t\right)=2\pi {\displaystyle \frac{T}{T_s}}t{\displaystyle \frac{1}{T_s}}=2\pi {\displaystyle \frac{2\Delta v_{TW}{v}_{in}}{\left(v_{in}-v_{out}\right)v_{out}}}{\displaystyle \frac{R_f{C}_f}{T_s^2}}t$$

(2)

where T_s is the switching period.

Therefore, based on (2), the transfer function of the hysteresis comparison is given by

$$F_{\phi v}\left(s\right)={\displaystyle \frac{{\phi }_d\left(s\right)}{v_{TW}\left(s\right)}}=4\pi {\displaystyle \frac{v_{in}}{\left(v_{in}-v_{out}\right)v_{out}}}{\displaystyle \frac{R_f{C}_f}{T_s^2}}{\displaystyle \frac{1}{s}}$$

(3)

According to Figure 3, the loop gain of the TWA-FPL is given by

$$T_{fp}=2{\displaystyle \frac{G_{cfp}{I}_p{v}_{in}{R}_f{C}_f}{C_p(v_{in}-v_{out})T_s^2{s}^2}}$$

(4)

The bode plot of the TWA-FPL’s loop gain is shown in Figure 5a. The system is unstable due to the loop gain having two poles at the origin. According to the compensation method of phase-locked loops, the loop needs to place a pole and a zero:

• As shown in Figure 5b, a zero is placed before the crossing frequency so that there is sufficient phase margin at the bandwidth and it is crossed with a slope of −20 dB/dec. When the phase margin is 60°, this pole is ${\omega }_z=\sqrt{{\displaystyle \frac{4}{3}}{\displaystyle \frac{I_p{v}_{in}{R}_f{C}_f}{C_p(v_{in}-v_{out})v_{out}{T}_s^2}}}$.
• As shown in Figure 5c, based on Figure 5b, a pole needs to be placed at ${\omega }_p=2\pi f_s/10$ in order to suppress the switching frequency ripple.

3. Multi-Phase Coupled Small Signal Model Analysis for Steady-State Accuracy and Loop Stability

To minimize steady-state error and ensure loop stability of the TMA-CBL, MPC-SSM and the loop gain of the TMA-CBL are derived. According to the loop gain, a compensator is designed to achieve a high DC loop gain and sufficient phase margin.

3.1. Multi-Phase Coupled Small Signal Model Analysis

To analyze the stability of the current balancing loop, an MPC-SSM is derived considering the coupling effect among multiple phases, as shown in Figure 6. Each phase is constructed with a power stage (from the duty cycle to the inductor current), a hysteresis comparator (from the feedback voltage and the threshold median to the duty cycle), a feedback network (from the inductor current to the feedback voltage) and a TMA-CBL (from the error voltage to the threshold median). All phases are coupled by a shared voltage control loop. In order to analyze the dynamic response of a current imbalance step, a current imbalance disturbance $\widehat{{\displaystyle i}}$ is introduced into the first phase. The Kth phase represents the phase that maintains the current balancing, i.e., K ≠ 1.

In Figure 6, Z_S describes the impedance of the power stage. H_vi describes the transfer function of the feedback network. F_dv describes the transfer function of the hysteresis comparator. Z_S, H_vi and F_dv are given by

$$\{\begin{array}{l}{Z}_S={\displaystyle \frac{\left(sL+R_{SL}\right)\left(R_f+1/s{C}_f\right)}{sL+R_{SL}+R_f+1/s{C}_f}}\\ H_{vi}={\displaystyle \frac{sL+R_{SL}}{s^{2}L{C}_f+s\left(R_{SL}+R_f\right)C_f+1}}\\ F_{dv}={\displaystyle \frac{2L}{v_{in}{T}_S{H}_{vi}}}\end{array}$$

(5)

where L is the inductance value; R_SL is the parasitic resistance of the inductor; R_f is the feedback resistance value; C_f is the feedback capacitance value. All these parameters are labeled in Figure 1. v_in is the input voltage and T_s is the switching period.

According to Figure 6, small signals of the inductor current ${\widehat{{\displaystyle i}}}_L$, feedback voltage ${\hat{v}}_{fb}$, capacitor current ${\widehat{{\displaystyle i}}}_{CS}$, and output of the TMA-CBL ${\hat{v}}_{cb}$ are the same expressions for the first and Kth phase, as given by ${\hat{v}}_S$

$$\{\begin{array}{l}{\widehat{i}}_L=\left[\left({\widehat{v}}_{cv}+{\widehat{v}}_{cb}-{\widehat{v}}_{fb}\right)F_{dv}{V}_{in}-\left({\widehat{v}}_S+{\widehat{v}}_{out}\right)\right]/Z_S\\ {\widehat{v}}_{fb}={\widehat{i}}_L{H}_{vi}+{\widehat{v}}_S+{\widehat{v}}_{out}\\ {\widehat{i}}_{CS}=s{C}_S\left({\widehat{v}}_S+{\widehat{v}}_{out}\right)\\ {\widehat{v}}_{cb}=G_{cb}\left({\widehat{v}}_{CSB}-{\widehat{v}}_S\right)\end{array}$$

(6)

where ${\hat{v}}_{\mathrm{S}}$, ${\hat{v}}_{cb}$ and ${\hat{v}}_{out}$ are small signals for sensing the resistor voltage, the output of the voltage control loop and the output voltage. G_cb is the compensator transfer function of the TMA-CBL.

The sensing resistor voltages are different expressions for the first and Kth phase. Small signals of the sensing resistor voltage and the reference voltage are given by

$$\{\begin{array}{l}{\widehat{v}}_{S\left(1\right)}=\left({\widehat{i}}_{L\left(1\right)}-{\widehat{i}}_{CS\left(1\right)}-\widehat{i}\right)R_S,{\widehat{v}}_{S\left(\mathrm{K}\right)}=\left({\widehat{i}}_{L\left(\mathrm{K}\right)}-{\widehat{i}}_{CS\left(\mathrm{K}\right)}\right)R_S\\ {\widehat{v}}_{CSB}={\displaystyle \frac{\left({\displaystyle \sum _{\mathrm{K}=2}^N{\widehat{v}}_{S\left(\mathrm{K}\right)}}+{\widehat{v}}_{S\left(1\right)}\right)}{N}}\end{array}$$

(7)

where N is the total phase number.

According to Figure 6, small signals of the output voltage and the output of the voltage control loop are expressed as

$$\{\begin{array}{l}{\widehat{v}}_{out}=Z_O\left[{\displaystyle \sum _{\mathrm{K}=2}^N\left({\widehat{i}}_{L\left(\mathrm{K}\right)}-{\widehat{i}}_{CS\left(\mathrm{K}\right)}\right)}+{\widehat{i}}_{L\left(1\right)}-{\widehat{i}}_{CS\left(1\right)}-\widehat{i}\right]\\ {\widehat{v}}_{cv}=-G_{cv}{\widehat{v}}_{out}\\ Z_O={\displaystyle \frac{R_L}{s{R}_{L}C+1}}\end{array}$$

(8)

where R_L and C are the output resistance and the capacitance value.

3.2. Loop Compensation of the TMA-CBL

Furthermore, a compensator is designed based on the derived MPC-SSM. Combining (5)–(8), small signals for inductor currents of the first and Kth phases (${\widehat{{\displaystyle i}}}_{L(1)}$ and ${\widehat{{\displaystyle i}}}_{L(\mathrm{K})}$) are derived as (9). In (9), G_iv describes the transfer function from the output voltage to the inductor current, which depends on G_cv and G_cb. G_il describes the transfer function from the current disturbance to the inductor current, which depends on G_cb. G_vl describes the transfer function from the current disturbance to the output voltage, which depends on G_cv.

$$\{\begin{array}{l}{\widehat{i}}_{L\left(1\right)}={\widehat{v}}_{out}{G}_{iv}+\widehat{i}{G}_{il},{\widehat{i}}_{L\left(\mathrm{K}\right)}={\widehat{v}}_{out}{G}_{iv},{\widehat{v}}_{out}=\widehat{i}{G}_{vl}\\ G_{iv}={\displaystyle \frac{G_{cb}\left(\frac{R_S}{N{Z}_O}{F}_{dv}{V}_{in}+s{R}_S{C}_S{F}_{dv}{V}_{in}\right)-G_{cv}{F}_{dv}{V}_{in}-F_{dv}{V}_{in}-1}{G_{cb}{R}_S{F}_{dv}{V}_{in}+Z_S+R_S{F}_{dv}{V}_{in}+H_{vi}{F}_{dv}{V}_{in}+R_S}}\\ G_{il}={\displaystyle \frac{G_{cb}{R}_S{F}_{dv}{V}_{in}+R_S{F}_{dv}{V}_{in}+R_S}{G_{cb}{R}_S{F}_{dv}{V}_{in}+Z_S+R_S{F}_{dv}{V}_{in}+H_{vi}{F}_{dv}{V}_{in}+R_S}}\\ G_{vl}={\displaystyle \frac{-Z_O\left(Z_S+H_{vi}{F}_{dv}{V}_{in}\right)}{Z_S+R_S{F}_{dv}{V}_{in}+H_{vi}{F}_{dv}{V}_{in}+R_S+N{Z}_O\left(G_{cv}{F}_{dv}{V}_{in}+F_{dv}{V}_{in}+1+s{C}_S{Z}_S+s{H}_{vi}{C}_S{F}_{dv}{V}_{in}\right)}}\end{array}$$

(9)

Therefore, from (9), the closed-loop transfer function of the first phase is derived as

$$G_{cl\_b\left(1\right)}={\displaystyle \frac{{\widehat{i}}_{L\left(1\right)}}{i}}=G_{iv}{G}_{vl}+G_{il}$$

(10)

According to the relationship between the closed-loop transfer function and the loop gain, the loop gain is derived from (10), as given in (11).

$$T_{b\left(1\right)}={\displaystyle \frac{G_{cl\_b\left(1\right)}}{1+G_{cl\_b\left(1\right)}}}={\displaystyle \frac{G_{iv}{G}_{vl}+G_{il}}{1-G_{iv}{G}_{vl}-G_{il}}}$$

(11)

Based on (5) and (9)–(11), loop gain T_b(1) depends on the circuit parameters (L, R_SL, R_f, C_f, R_L, C, R_S, C_S, N), and transfer functions of the voltage control loop and the TMA-CBL compensators (G_cv, G_cb). G_cv is designed according to the small-signal model of the voltage control loop. Therefore, loop gain T_b(1) is only improved by G_cb.

Substituting the circuit parameters and the transfer function of the voltage control loop compensator into (5) and (9)–(11), bode plots of loop gain T_b(1) without and with compensation (G_cb = 1 and G_cb = K_b/s) are shown in Figure 7. Without the compensation (G_cb = 1), the low DC gain of the T_b(1) causes large steady-state error. To reduce the current balancing error, a type-I compensator (G_cb = K_b/s) is adapted, which places a pole at the origin as a dominant pole to improve the DC gain. Furthermore, to achieve a sufficient phase margin, parameter K_b satisfies

$$\{\begin{array}{l}{A}_v{K}_b{\displaystyle \frac{1}{\mathrm{BW}}}{\displaystyle \frac{1}{\sqrt{1+{\left(\frac{\mathrm{BW}}{{\omega }_{p0}}\right)}^2}}}=1\\ 180°-90°-\arctan {\displaystyle \frac{\mathrm{BW}}{{\omega }_{p0}}}=\mathrm{PM}\end{array}$$

(12)

where A_v and ω_p0 are the DC gain and the domain pole of T_b(1) without the compensation, respectively. BW and PM are bandwidth and phase margin of T_b(1) with the compensation. Therefore, from (12), if PM = 60°, parameter K_b is selected as

$$K_b={\displaystyle \frac{2}{3}}{\displaystyle \frac{{\omega }_{p0}}{A_v}}$$

(13)

4. Detailed Circuit Design

The proposed four-phase interleaved buck converter is shown in Figure 8. It consists of a bandgap and protect module, a soft-start module, a voltage control loop compensator and a four-single-phase buck converter, where a single-phase buck converter consists of a PFD, a CP, a deadtime generator, a driver, power switches, a threshold generator, a hysteresis comparator and a current balance loop. Input signals are v_ref, v_out, v_fb<1:4>, CLK<1:4>, V_{O_CS}<1:4> and V_{o_com}, and output signals are I_out<1:4>, where I_out<1:4> are output currents of per phase, V_{O_CS}<1:4> are voltages converted by inductance current of per phase, and V_{o_com} is voltage converted by average inductance current. To analyze the operating details, some critical module designs are discussed as follows.

4.1. Soft-Starting Module

The schematic diagram of the soft-starting module is shown in Figure 9. The input signals are v_fb, v_ref, V_CP, SYS_RDY and EN, and the output signal is MODE. When the feedback voltage v_fb is larger than the low voltage threshold v_ref-V_CP/5, the output signal MODE flips to a high voltage level from a low voltage level. Afterward, the proposed converter starts to operate at the closed-loop control.

EN is an active high enable signal for the converter starting. SYS_RDY is an active low enable signal for turning off the comparator and the resistor divider network to eliminate the bias current after soft-starting. The logic of the output signal MODE is in Figure 10. The soft-starting is classified into three stages:

• The converter is off (EN = 0): MODE and C are set to a low voltage level.
• The converter is on (EN = 1), and v_fb < v_ref-V_CP/5: MODE and C are set to a low voltage level.
• The converter is on (EN = 1), and v_fb > v_ref-V_CP/5: C flips to a high voltage level in a short time, and MODE flips to a high voltage level and latch, which indicates that the converter enters closed-loop control.

4.2. Phase Frequency Detector and Charge Pump

The schematic diagram of the PFD is shown in Figure 11. Conventional PFD and CP are difficult to converge at the large frequency and phase errors. Therefore, the PFD and CP are improved:

• The proposed adjusting frequency circuit can reduce the frequency error quickly.
• The proposed CP can adjust the charge or discharge current to accelerate the regulating process.

According to Figure 11, the frequency error of the drive signal and the clock is reduced to 0.5f_CLK~f_CLK:

• f_d > f_CLK (UP = 1, DN = 0): V_CP rises to increase the switching frequency.
• f_d < f_CLK (UP = 0, DN = 1): V_CP falls to decrease the switching frequency. Then, the multiplexers select outputs of D flip-flops to reduce the phase error.

Finally, V_CP is regulated to synchronize the driving signal with the clock.

4.3. Threshold Generator

To generate the thresholds of the hysteresis comparator, the threshold generator should proportionally add or subtract outputs of the frequency phase loop, voltage loop and current balancing loop. Input signals are CSCMPI, CSCMPO, v_ref, V_{o_com}, V_{o_cs}, MODE, MODEN, V_E and V_CP, and output signals are V_TH and V_TL, where CSCMPI and CSCMPO are compensation networks of current balancing loop.

At the soft-starting period, outputs of the current balancing loop and the voltage control loop, follow the reference voltage by unit gain amplifiers, as shown in Figure 8. According to Figure 12, when the proposed converter operates at the soft-starting period (MODE = 0 and MODEN = 1), V_TH and V_TL are given by

$$\begin{array}{l}{V}_{TH}={\displaystyle \frac{{\mathrm{V}}_{\mathrm{E}}}{2}}+{\displaystyle \frac{v_{ref}}{2}}+{\displaystyle \frac{{\mathrm{V}}_{\mathrm{CP}0}}{5}}=v_{ref}+{\displaystyle \frac{{\mathrm{V}}_{\mathrm{CP}0}}{5}}\\ V_{TL}={\displaystyle \frac{{\mathrm{V}}_{\mathrm{E}}}{2}}+{\displaystyle \frac{v_{ref}}{2}}-{\displaystyle \frac{{\mathrm{V}}_{\mathrm{CP}0}}{5}}=v_{ref}-{\displaystyle \frac{{\mathrm{V}}_{\mathrm{CP}0}}{5}}\end{array}$$

(14)

where V_CP0 is the initial output voltage of the TWA-FPL.

At the closed-loop control period, outputs of the current balancing loop and the voltage control loop are generated by the compensators. When the proposed converter operates at the closed-loop control period (MODE = 1 and MODEN = 0), V_TH and V_TL are given by

$$\begin{array}{l}{V}_{TH}={\displaystyle \frac{1}{2}}\underset{{\mathrm{V}}_{\mathrm{E}}}{\underbrace{G_{cv}\left(v_{ref}-v_{out}\right)}}+{\displaystyle \frac{1}{2}}{G}_{cb}\left(V_{o\_com}-V_{o\_cs}\right)+{\displaystyle \frac{1}{5}}\underset{{\mathrm{V}}_{\mathrm{CP}}}{\underbrace{G_{cfp}\left({\phi }_{clk}-{\phi }_d\right)}}\\ V_{TL}={\displaystyle \frac{1}{2}}\underset{{\mathrm{V}}_{\mathrm{E}}}{\underbrace{G_{cv}\left(v_{ref}-v_{out}\right)}}+{\displaystyle \frac{1}{2}}{G}_{cb}\left(V_{o\_com}-V_{o\_cs}\right)-{\displaystyle \frac{1}{5}}\underset{{\mathrm{V}}_{\mathrm{CP}}}{\underbrace{G_{cfp}\left({\phi }_{clk}-{\phi }_d\right)}}\end{array}$$

(15)

Therefore, according to (15), the threshold median is determined by the voltage control loop and the current balancing loop, and the threshold width is determined by the frequency phase loop.

4.4. Hysteresis Comparator

To reduce the comparing delay, two single-edge fast comparators and RS flip-flops are used. The hysteresis comparator is shown in Figure 13.

The single-edge fast comparator is shown in Figure 14. M₀~M₅ constitute a dissymmetrical differential input structure. M1 regulates its current by the feedback voltage v_fb. M₆ copies the current of M₁, and M₇ copies I_bp. Furthermore, the current of M₁ is compared with I_bp to obtain the output.

A high-speed single-edge comparator is the most important at the switching frequency above 10 MHz. The small comparing delay can improve the loop stability. The dominant pole is at the gate nodes of M₅ and M₆ due to the capacitor of the gate node. The capacitance of the gate node is enlarged because of the Miller effect of M₆. The dominant pole is approximated as

$${\omega }_p\approx {\displaystyle \frac{g_{m5}}{C_{GS5}+\left(1-A_v\right)C_{GD6}+C_{GS6}}}$$

(16)

where A_V is the voltage gain generated by M₆. Obviously, reducing the amplitude of A_v effectively increases the pole and reduces the comparing delay.

Although the single-edge comparator has the advantage of high speed, comparing accuracy is affected by the substrate bias effect, threshold voltages of transistors, temperature and so on. The compensating branch is constructed by M₀, M₂ and M₄, and the source voltage of M₁ follows M₀ by the unit gain amplifier. The compensating branch has a long signal path and larger delay due to the transmission delay of the unit gain amplifier, which causes the dissymmetrical comparing delay of the single-edge comparator. Therefore, the high-speed hysteresis comparator requires two single-edge comparators.

At the tt process corner, the rising rates of the input signal are 1000 V/μs and 100 V/μs, and the comparing delays are 878 ps and 2.4 ns, respectively. In addition, when the rising rate is 100 V/μs, the slew rate of the hysteresis comparator is 18,000 V/μs.

5. Layout and Simulation Results

A four-phase interleaved CFH buck converter is designed with HHGrace 180 nm BCD process, which occupies a 2.55 mm × 1.775 mm die area. The layout of the chip is shown in Figure 15. Cadence IC is used to perform transistor-level simulations using foundry-provided models. Current balancing error, soft-starting period, transient response and efficiency are evaluated in post-layout simulations.

Figure 16 shows current balancing errors at 1% and 5% sensing resistor deviations after TMA-CBL reaches a steady state. In Figure 16a, the sensing resistor deviation in the first phase is +1% and the sensing resistor deviations in the other phases are −1%. Its current balancing error is 0.48%. In Figure 16b, the sensing resistor deviation in the first phase is +5% and the sensing resistor deviations in the other phases are −5%. Its current balancing error is 0.68%.

The soft-starting is implemented by PWM with a gradually increasing duty cycle. The driving signals use external PWM signals from CLK<1:4>. When the feedback signal v_ref rises to the low voltage threshold v_ref-V_CP/5, the soft-starting module changes the chip operating mode and closed-loop control starts operation, as shown in Figure 17. At the closed-loop control period, the current balancing loop and the voltage control loop compensate and generate the thresholds. Figure 17a shows the output voltage v_out, inductor currents i_L and outputs of TMA-CBLs v_cb in the transition period of TMA-CBL. After the output voltage achieves the steady state, TMA-CBL starts to work. Inductor currents are adjusted from imbalance to balance. Figure 17b shows the output voltage v_out, the driving signal DR and the outputs v_TW of TWA-FPLs in the transition period. After TWA-FPL starts to work, the frequency and phase of the driving signal are adjusted to synchronize with the external clock.

6. Prototype and Experimental Results

Based on the above chip, the inductors and capacitors of each phase power stage, the resistors of the current balancing network, and the resistors and capacitors of each loop compensator are added to the peripheral circuits to design the test PCB of this chip; a photo of the prototype is shown in Figure 18.

Figure 19 shows the bench setup for the prototype measurement, where the model number of the power supply is IT6720 (ITECH, Nanjing, China) and the model number of the oscilloscope is MDO3024 (TEKTRONIX, Shanghai, China).

Figure 20 shows the output voltage waveform when the output current steps. The output voltage overshoots are 374 mV and 370 mV when the output current steps from 0.89 A to 1.78 A and from 1.78 A to 0.89 A, respectively. Their response times are both 4.9 μs approximately.

Figure 21 shows efficiencies with output power at different switching frequencies and input voltages. The peak efficiency reaches 89.51% at 10 MHz switching frequency, 3.3 V input voltage and 1.8 V output voltage.

Table 1. Performance comparison with the reported works.

Publication	This Work	[15]	[16]	[22]	[26]
Technology	180 nm BCD	350 nm CMOS	65 nm CMOS	180 nm BCD	130 nm BCD
Control Methods	Interleaved CFH	CFH	CFH	Current mode	Current mode
Balancing Method	Threshold Median Adjustment	×	×	Duty Cycle Adjustment	Single Threshold Adjustment
fsw × Phase	10 MHz × 4	1 MHz	1, 0.5, 0.25 MHz	500 KHz × 4	2.25 MHz × 4
Inductance (L)	1 μH × 4	4.7 μH	4.7 μH	×	470 nH × 4
Capacitance (C)	100 nF × 5	10 μF	10 μF	×	88 μF
vin (V)	3.3~5	3.3~3.6	2.7~3.3	12	2.8~5
vout (V)	1.6~2	0.9~2.5	1	1	0.68~1.92
Load Range (W)	0.4~3.2	<1.5	0.02~0.15	<12	<7.68
Peak Efficiency	89.51%	90%	96.5%	×	91.1%
Voltage Ripple (mV)	0.2	59.289	32.5	×	×
FOM	3.6	0.0353	0.912	×	×
Current Balancing Accuracy	<0.68%	×	×	6.3%	<10.5%

shows a comparison of the proposed interleaved CFH buck converter with other CFH converters [15,16]. The power level of this work is twice that of [15]. The CFH buck proposed in this paper utilizes a multiphase interleaving technique and has a lower voltage ripple compared to [15,16]. In this paper, the parameter FOM is defined as

$$\mathrm{FOM}={\displaystyle \frac{{10}^3}{8}}\times {\displaystyle \frac{\left(v_{in}-v_{out}\right)\left(\mathrm{V}\right)\times v_{out}\left(\mathrm{V}\right)}{L\left(\mu H\right)\times C\left(\mu F\right)\times \mathrm{Voultage} \mathrm{Ripple}\left(\mathrm{mV}\right)\times f_{sw}^2\left({\mathrm{MHz}}^2\right)\times v_{in}\left(\mathrm{V}\right)}}$$

(17)

Voltage ripple is affected by switching frequency, input voltage, output voltage, inductance and capacitance values. FOM can exclude the influence of the above factors on the voltage ripple and can more fairly reflect the ability of the circuit itself to suppress the voltage ripple. The FOM of this work is four times that of [16], which means better ripple suppression. Therefore, this work has significant advantages on the power level and voltage ripple. In addition, the circuit structure of TWA-FPL enables constant frequency control and solves the EMI problem.

In this paper, the current balancing among the phases is achieved by adjusting the median value of the threshold, which is named as TMA-CBL structure. Table 1 shows a comparison of TMA-CBL with other current balancing methods [22,26]. It can be seen that the accuracy of current balancing in this paper is much higher than theirs.

In summary, this work has significant advantages in voltage ripple, constant switching frequency and current balancing accuracy.

7. Conclusions

This paper proposes a TMA-CBL method for current balancing in interleaved CFH buck converters. An MPC-SSM model is established to ensure the loop stability of the converter, and the current balancing error is analyzed to verify the accuracy of the proposed TMA-CBL approach. With the implementation of the TMA-CBL, the current balancing error is reduced to below 0.68% even when the sensing resistors deviate by 5%. This effectively addresses the current balancing issue in interleaved buck converters in CFH controls, offering potential benefits in ripple reduction and power extension. However, this work primarily addresses steady-state performance, with limited analysis of transient response and dynamic behavior. Future research could focus on enhancing the method’s effectiveness during transient conditions to ensure reliable performance in a wider range of operating scenarios.