Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology
Abstract
:1. Introduction
- An aided TDC circuit is implemented as the core adaptive control module in the PLL, and it can accurately convert the phase difference signal to switch the instructions to dynamically control the CP and VCO.
- An auxiliary secondary CP with a selectable switch is designed to construct a parallel output topology that forms paired CP modules, which can double the charging/discharging current to speed up the locking phase; otherwise, the CP operates in power-saving mode.
- A novel coarse- or fine-grained programmable frequency tunable ring voltage-controlled oscillator (VCO) is proposed, which can be adaptively tuned to the third or the fifth order by the TDC in order to dynamically optimize the phase noise and power consumption, leading to an optimal performance tradeoff.
2. PLL Design and Implementation
2.1. Previous Work
2.2. Proposed PLL Architecture
2.3. TDC-Aided Control
3. Design Tradeoff of Fast-Locking and Other Features
3.1. Theoretical Analysis of Phase Locking
3.2. Principle and Design of Ring-VCO
3.3. Feature Analysis of Individual Three-Stage and Five-Stage Ring Oscillators
3.4. Proposed TDC-Control-Based Adaptive Dual-Mode Switchable Ring-VCO
4. Performance Verification and Discussion
4.1. Simulation-Based Analysis
4.2. Comparison of Design Cases
5. Conclusions and Future Work
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
References
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Performance Index | Pre-Opti. | Post-Opti. |
---|---|---|
Voltage [V] | 1.80 | 1.80 |
Temperature [°C] | 25 | 25 |
PN [dBc/Hz@1 MHz] | −78.13 | −98.07 |
Power [μW] | 244.47 | 382.12 |
FoM [dBc/Hz] | −150.41 | −157.06 |
Process Corner | TT | SS | FF |
---|---|---|---|
Technology [nm] | 180 | 180 | 180 |
Voltage [V] | 1.80 | 1.62 | 1.98 |
Temperature [°C] | 25 | 120 | −40 |
Lock Time [μs] | 1.11 | 0.82 | 0.57 |
Power Diss. [mW] | 1.86 | 0.85 | 3.43 |
Items | [1] | [2] | [14] | [15] | [26] | [27] | [28] | [29] | [30] | This Work |
---|---|---|---|---|---|---|---|---|---|---|
Technology [nm] | 180 | 130 | 180 | 130 | 28 | 14 | 55 | 180 | 65 | 180 |
Supply voltage [V] | 1.80 | 1.20 | 0.70 | 1.50 | N/A | 0.80 | 1.20 | 1.80 | N/A | 1.80 |
Phase noise [dBc/Hz @1 MHz] | −100 | N/A | −99.5 | −109 | −99.3 | −113.6 | −110 | −90 | N/A | −98.07 |
Output freq. range [GHz] | 4.8–5.0 | 2.32–2.56 | N/A | 5.7–6.0 | 22.5–27.7 | N/A | 4.4–5.6 | 1.06–1.60 | 0.2–2.0 | 0.05–0.324 |
Power dissipation [mW] | 11 | N/A | 0.43 | 12 | 25 | 13.4 | 20 | 11 | 9 | 1.86 |
Locking time [μs] | 5 | 2.5 | 18 | N/A | 45 | 310 | 15 | 5 | 9.34 | 1.11 |
Data type | Sim | Sim | Meas | Meas | Meas | Meas | Meas | Sim | Meas | Sim |
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Sun, L.; Luo, Y.; Deng, Z.; Wang, J.; Liu, B. Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology. Electronics 2024, 13, 3586. https://doi.org/10.3390/electronics13183586
Sun L, Luo Y, Deng Z, Wang J, Liu B. Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology. Electronics. 2024; 13(18):3586. https://doi.org/10.3390/electronics13183586
Chicago/Turabian StyleSun, Ligong, Yixin Luo, Zhiyao Deng, Jinchan Wang, and Bo Liu. 2024. "Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology" Electronics 13, no. 18: 3586. https://doi.org/10.3390/electronics13183586