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Open AccessArticle
A Variation-Aware Binary Neural Network Framework for Process Resilient In-Memory Computations
by
Minh-Son Le
Minh-Son Le ,
Thi-Nhan Pham
Thi-Nhan Pham ,
Thanh-Dat Nguyen
Thanh-Dat Nguyen and
Ik-Joon Chang
Ik-Joon Chang
Prof. Dr. Ik-Joon Chang is currently an Associate Professor at the Department of Electronic Kyung of [...]
Prof. Dr. Ik-Joon Chang is currently an Associate Professor at the Department of Electronic Engineering, Kyung Hee University, Yongin-si, Republic of Korea. He received a B.S. degree, summa cum laude, in electrical engineering from Seoul National University, Seoul, Republic of Korea. He acquired his M.S. and Ph.D. degrees from the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA, in 2005 and 2009, respectively. He was awarded by the Samsung Scholarship Foundation in 2005. His research interests are low-power VLSI design, radiation-aware design, and deep learning architectures.
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Department of Electronic Engineering, Kyung Hee University, Yongin-si 17104, Republic of Korea
*
Author to whom correspondence should be addressed.
Electronics 2024, 13(19), 3847; https://doi.org/10.3390/electronics13193847 (registering DOI)
Submission received: 12 August 2024
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Revised: 24 September 2024
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Accepted: 26 September 2024
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Published: 28 September 2024
Abstract
Binary neural networks (BNNs) that use 1-bit weights and activations have garnered interest as extreme quantization provides low power dissipation. By implementing BNNs as computation-in-memory (CIM), which computes multiplication and accumulations on memory arrays in an analog fashion, namely, analog CIM, we can further improve the energy efficiency to process neural networks. However, analog CIMs are susceptible to process variation, which refers to the variability in manufacturing that causes fluctuations in the electrical properties of transistors, resulting in significant degradation in BNN accuracy. Our Monte Carlo simulations demonstrate that in an SRAM-based analog CIM implementing the VGG-9 BNN model, the classification accuracy on the CIFAR-10 image dataset is degraded to below 50% under process variations in a 28 nm FD-SOI technology. To overcome this problem, we present a variation-aware BNN framework. The proposed framework is developed for SRAM-based BNN CIMs since SRAM is most widely used as on-chip memory; however , it is easily extensible to BNN CIMs based on other memories. Our extensive experimental results demonstrate that under process variation of 28 nm FD-SOI, with an SRAM array size of , our framework significantly enhances classification accuracies on both the MNIST hand-written digit dataset and the CIFAR-10 image dataset. Specifically, for the CONVNET BNN model on MNIST, accuracy improves from 60.24% to 92.33%, while for the VGG-9 BNN model on CIFAR-10, accuracy increases from 45.23% to 78.22%.
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MDPI and ACS Style
Le, M.-S.; Pham, T.-N.; Nguyen, T.-D.; Chang, I.-J.
A Variation-Aware Binary Neural Network Framework for Process Resilient In-Memory Computations. Electronics 2024, 13, 3847.
https://doi.org/10.3390/electronics13193847
AMA Style
Le M-S, Pham T-N, Nguyen T-D, Chang I-J.
A Variation-Aware Binary Neural Network Framework for Process Resilient In-Memory Computations. Electronics. 2024; 13(19):3847.
https://doi.org/10.3390/electronics13193847
Chicago/Turabian Style
Le, Minh-Son, Thi-Nhan Pham, Thanh-Dat Nguyen, and Ik-Joon Chang.
2024. "A Variation-Aware Binary Neural Network Framework for Process Resilient In-Memory Computations" Electronics 13, no. 19: 3847.
https://doi.org/10.3390/electronics13193847
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