Simple Voltage Balancing Control of Four-Level Inverter

Abstract

Multilevel inverters with improved voltage quality are widely used in applications such as motor control and electric vehicles. The four-level active neutral point clamped (4L-ANPC) inverter effectively meets the demands for high power density and low device voltage stress. However, balancing the capacitor voltage and reducing its low-frequency voltage fluctuation are critical challenges that need to be addressed. To address these challenges, this paper proposes a “variable reference + zero-sequence injection” method that requires only three reference voltage signals to determine the injected zero-sequence components. Particularly, the expression of the midpoint current, regarding the modulation index and phase current amplitude, is theoretically derived. This reveals the fundamental connection between the zero-sequence voltage signal and the midpoint current, providing a theoretical foundation for the zero-sequence injection method in four-level inverters. Subsequently, a simulation model and an experimental platform of the 4L-ANPC inverter were developed to compare and analyze the waveforms of the upper and lower capacitor voltages, phase currents, and line voltages under different modulation methods. Additionally, the upper and lower capacitor voltage waveforms were examined for various modulation indices. The results indicate that as the modulation index increases, the low-frequency voltage fluctuation in the upper and lower capacitor voltages also rises. At a modulation index of 0.95, the “variable reference + zero-sequence injection” method effectively suppresses the fluctuation in the upper and lower capacitor voltages to be no more than 1 V. These experimental findings validate the effectiveness of the proposed method.

1. Introduction

Multilevel converters are known for their superior output voltage quality and reduced voltage variability, making them widely applicable in low-voltage, high-power industrial applications, such as photovoltaic power generation, motor control, and electric vehicles. In this domain, multilevel power converter topologies include the three-level neutral point clamped (3L-NPC) converter [1,2], the three-level active neutral point clamped (3L-ANPC) converter [3,4,5], the four-level active neutral point clamped (4L-ANPC) converter [6,7,8], and the five-level active neutral point clamped (5L-ANPC) converter [9,10,11]. The 3L-NPC, 3L-ANPC, and 5L-ANPC converters are popular due to their lower harmonic distortions compared to traditional two-level converters. However, the 5L-ANPC inverter requires multiple film capacitors in parallel at each phase leg to handle high input current requirement, leading to increased size and cost. The 4L-ANPC inverter, on the other hand, meets the demands for high power density, low device voltage stress, and reduced harmonics. The primary challenge for the 4L-ANPC inverter is balancing the capacitor voltage and reducing the ripple of the midpoint current, as it flows into or out of the DC capacitor.

Voltage imbalance brings in increased voltage stress on MOSFETs and increased harmonics. This issue can be addressed by incorporating additional switched-capacitor resonant circuits [12,13], but this approach inevitably results in increased power loss. So far, only a limited number of balancing control methods have been reported to address this issue. One method is virtual space vector pulse width modulation (VSVPWM), which uses multiple switching states to generate each virtual vector, ensuring an equal average current at each neutral point throughout the switching period [14]. Another approach employs model predictive control (MPC), which balances the system by optimizing a cost function [15,16]. A third technique involves an overlapping carrier modulation scheme, as reported in [8,17,18]. Additionally, a recent solution is the variable carrier-based voltage balancing method, described in [19]. Nonetheless, a simpler voltage balancing control method for implementation in a DSP is still needed. The CBPWM method proposed in [20] compares the three modulating signals to the carrier signal and introduces a PI regulator to control the intermediate capacitor voltage at 1/3 U_dc, effectively balancing the upper and lower capacitor voltages. Compared to the virtual vector SVPWM method in [12,13], the CBPWM method in [20] has a shorter computation time and is easier to implement digitally in a DSP. However, a significant drawback of the CBPWM method is its inability to adequately address the imbalance between the upper and lower capacitances. Additionally, there is triple fundamental frequency voltage oscillation on the upper and lower capacitors. In the CBPWM schemes described in [21], two simple PI controllers are utilized: one is designed to balance the middle capacitor voltage, while the other focuses on balancing the upper and lower capacitor voltages. However, the PI regulator does not perform optimally in achieving the desired regulation. To address this, a “variable reference proportional resonant (PR) control-based ZSV injection” method is proposed in [22], which effectively balances the DC-link capacitor voltage and eliminates its ripple. The performance of the DC-link capacitor voltage balancing largely depends on the design of the closed-loop controllers. A new carrier-overlapped pulse width modulation (COPWM) method is proposed in [23], utilizing the volt-second balance principle to achieve natural capacitor voltage balancing. In this process, the COPWM method can increase the switching losses. To address this issue, a composite modulation and voltage balancing method is proposed in [24]. For modulation indices below 0.5, a phase-disposition PWM is used, while for indices above 0.5, a decoupled voltage balancing method based on carrier-overlapped PWM is employed. This approach balances NP voltages across the full modulation index range, while reducing switching losses.

Another common method for balancing DC-link capacitor voltages in NPC inverters is to add a zero-sequence voltage signal to the sinusoidal reference signals. This injected zero-sequence voltage signal modifies the direction and magnitude of the neutral-point (NP) current by adjusting the modulation signal’s duty cycle, thereby influencing the balance and ripple of the DC-link capacitor voltage. Thus, selecting the appropriate injected zero-sequence voltage signal is crucial. In [25], a modified phase-shifted PWM (PS-PWM) method is used to balance the central DC-link capacitor voltages by exploiting redundant switching states. An optimal zero-sequence voltage is injected to simultaneously balance the neutral-point voltage and reduce the common-mode voltage, effectively utilizing the degrees of freedom offered by the redundant voltage vectors. An appropriate amount of zero-sequence voltage is injected into the DC bus reference voltage waveform by modeling the discrete dynamic prediction of the current in [26]. However, the voltage balancing performance of the DC capacitor significantly depends on the model parameter design. While ref. [27] studies the relationship between neutral point currents and output voltage, balancing the upper and lower DC-link capacitor voltages through optimal zero-sequence voltage injection, it does not elucidate the fundamental connection between zero-sequence voltage signal injection and midpoint current flow. Consequently, selecting parameters to effectively suppress low-frequency ripples in DC-link capacitor voltages remains a challenge for four-level inverters.

This article proposes a novel and straightforward method for determining the injected zero-sequence voltage signal by comparing the three reference voltage signals for CBPWM in the four-level NPC inverter. This method eliminates the need for predictive modeling or redundant switching to determine the zero-sequence voltage signal. Theoretical analyses show that the proposed CBPWM method balances the DC-link capacitor voltages and reduces the voltage ripples effectively, a requirement in the existing CBPWM schemes in [28].

2. Proposed Voltage Balancing Control

The topology of the four-level active neutral-point clamped (4L-ANPC) inverter is illustrated in Figure 1. Assuming that the intermediate capacitor voltage is regulated to 1/3 of the DC bus voltage, each phase capacitor voltage can be controlled to 1/6U_dc, allowing the inverter to generate four voltage levels per phase bridge arm. However, the upper and lower capacitor voltages are not inherently balanced.

In the conventional level-shifted carrier modulation scheme, three reference signals u_refa, u_refb, and u_refc are defined by Equation (1):

$$\left\{\begin{array}{l}{u}_{\mathrm{ref}a}=m\sin (2\pi f_{m}t)\\ u_{\mathrm{ref}b}=m\sin (2\pi f_{m}t-{\displaystyle \frac{2\pi }{3}})\\ u_{\mathrm{ref}c}=m\sin (2\pi f_{m}t+{\displaystyle \frac{2\pi }{3}})\end{array}\right.$$

(1)

where m represents the modulation index, and f_m denotes the fundamental frequency. Additionally, only one triangular carrier signal V_carr is utilized with the carrier frequency f_s.

The current waveforms of the three phases are defined by Equation (2):

$$\left\{\begin{array}{l}{i}_a=I_m\sin (\theta -{\phi }_x)\\ i_b=I_m\sin (\theta -{\phi }_x-{\displaystyle \frac{2\pi }{3}})\\ i_c=I_m\sin (\theta -{\phi }_x+{\displaystyle \frac{2\pi }{3}})\end{array}\right.$$

(2)

where θ = 2πf_mt, and φ_x (x = a, b, c) is the power factor angle.

A detailed derivation of the capacitor current expression has been carried out in [29] to reveal the mechanism of capacitor voltage imbalance. Briefly, I_C1 and I_C3 during each fundamental period are influenced by the output current amplitude I_m, power factor angle φ_x, switching angle α, modulation index m, and the DC I_dc. In contrast, I_C2 is independent of the modulation index m. Furthermore, the amplitude of I_C1 is equal to I_C3 but greater than I_C2. This means that without a voltage balancing circuit or control method, the middle capacitor C₂ will be charged less than the other two capacitors. As a result, the capacitor voltage of C₂ will eventually discharge to zero, while C₁ and C₃ equally share the total DC-link voltage, leading to a capacitor voltage imbalance.

As analyzed above, the capacitor voltage imbalance issue of the 4L-ANPC inverter is the over-discharge of the middle capacitor. Balancing the voltage of capacitor C₂ at 1/3U_dc is crucial. This paper proposes a variable reference voltage balancing method to achieve this. The specific derivation of this method has been presented in [29]. Additionally, to mitigate the voltage fluctuations in the upper and lower DC-link capacitor voltages, the reference voltage is adjusted using a zero-sequence voltage injection method.

2.1. Variable Reference Voltage Method

The variable reference voltage method is shown in Figure 2. The PI compensator regulates the middle capacitor voltage U_C2 to the target value of 1/3U_dc with the voltage control error for C₂ defined as:

$$\Delta U_{C2}={\displaystyle \frac{1}{3}}{U}_{dc}-U_{C2}$$

(3)

The three new modulated wave signals u_refx (x = a, b, c) are as follows:

$$\left\{\begin{array}{l}{u}_{refx1}=u_{refx}\\ u_{refx2}={\displaystyle \frac{u_{refx3}}{k}}\\ u_{refx3}=u_{refx}+1\end{array}\right.$$

(4)

With the adopted variable reference voltage method, the intermediate capacitor voltage U_c2 can be controlled at 1/3 U_dc. Meanwhile, the upper and lower capacitance voltage U_c1 and U_c3 can be automatically balanced due to the symmetry of the proposed four-level converters.

2.2. Zero-Sequence Voltage Injection Method

The zero-sequence voltage signal expression is as follows:

$$u_{zs}=\left\{\begin{array}{l}{u}_{zs\max }=1-\max (u_{refa},u_{refb},u_{refc}),\mathrm{if}{U}_{\mathrm{C}1}\ge U_{\mathrm{C}3}\\ u_{zs\min }=-1-\min (u_{refa},u_{refb},u_{refc}),\mathrm{if}{U}_{\mathrm{C}1}<U_{\mathrm{C}3}\end{array}\right.$$

(5)

where U_C1 and U_C3 are the voltages of the upper and lower capacitors, respectively.

Three phase modulation signals u_xmod (x = a, b, c) are obtained by adding the zero-sequence voltage signal to the reference signal. Then, this modulating signal is compared to the carrier signal to generate a PWM drive signal. The structure of the adopted “variable reference + zero-sequence injection” method is shown schematically in Figure 3. In the figure, the red, blue and green lines represent the three modulated wave signals respectively, and the purple line represents the carrier signal.

$$u_{x\mathrm{mod}}=u_{refx}+u_{zs},x=(a,b,c)$$

(6)

When the phase current flows through the midpoint N1 (or N2) of the 4L-ANPC inverter, in other words, when the capacitor potential output is U_dc/6 or −U_dc/6, it causes the DC-link capacitor voltage to be imbalanced. As shown in Figure 4, since the switching frequency is much higher than the fundamental frequency, the reference signal can be regarded as constant in one switching period. The three modulating signals are compared to the carrier signal to obtain the duty cycles for the different levels in one switching cycle.

Since I_C1 and I_C2 are equal, this paper examines the relationship between the zero-sequence voltage signal injection and midpoint current flow, using midpoint current i_N1 as an example.

According to Figure 4, d_x1 is denoted as:

$$d_{x1}=d_{x2}={\displaystyle \frac{1-\left|u_{refx}\right|}{2}}$$

(7)

The average current I_N1 in one pulse cycle is denoted as:

$$\begin{array}{ll}{i}_{N1}& =({\displaystyle \frac{1-\left|\left.u_{a\mathrm{mod}}\right|\right.}{2}})i_a+({\displaystyle \frac{1-\left|\left.u_{b\mathrm{mod}}\right|\right.}{2}})i_b+({\displaystyle \frac{1-\left|\left.u_{c\mathrm{mod}}\right|\right.}{2}})i_c\\ & =\left\{\begin{array}{l}{i}_{N1\_\max },\mathrm{if}{u}_{zs}=u_{zs\_\max }\\ i_{N1\_\min },\mathrm{if}{u}_{zs}=u_{zs\_\min }\end{array}\right.\end{array}$$

(8)

According to Equations (5)–(8), it is possible to derive the maximum and minimum values of midpoint currents i_{N1_max} and i_{N1_min}, where k = 0, ±1, ±2…… The expression for the maximum value of the midpoint current is shown in Equations (9)–(11). If 2πf_st $\in$ [2kπ, 2kπ + π/3] and [2kπ + 5π/3, 2(k + 1) π], u_refa = max (u_refa, u_refb, u_refc), as shown in Equation (9). If 2πf_st $\in$ [2kπ + π/3, 2kπ + π], u_refb = max (u_refa, u_refb, u_refc), as shown in Equation (10). If 2πf_st $\in$ [2kπ + π, 2kπ + 5π/3], u_refc = max (u_refa, u_refb, u_refc), as shown in Equation (11).

$$i_{N1\_\max }=\left\{\begin{array}{l}-{\displaystyle \frac{3I_m}{4}}m\cos (\phi ),m\le {\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [2k\pi ,2k\pi +{\displaystyle \frac{\pi }{3}}]\mathrm{and}[2k\pi +{\displaystyle \frac{5\pi }{3}},2(k+1)\pi ]\\ -{\displaystyle \frac{I_m}{4}}[2\sqrt{3}m\sin (4\pi f_{s}t-\phi )+4\cos (2\pi f_{s}t-\phi +{\displaystyle \frac{\pi }{3}})-\sqrt{3}m\sin (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [2k\pi +{\displaystyle \frac{5\pi }{3}},{\theta }_1],{\theta }_1=2k\pi +{\displaystyle \frac{\pi }{6}}-\arccos ({\displaystyle \frac{1}{\sqrt{3}m}})\\ -{\displaystyle \frac{I_m}{4}}[4\cos (2\pi f_{s}t-\phi )-3m\cos (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [2k\pi ,{\theta }_2]\mathrm{and}[{\theta }_1,2(k+1)\pi ],{\theta }_2=2k\pi +{\displaystyle \frac{11\pi }{6}}+\arccos ({\displaystyle \frac{1}{\sqrt{3}m}})\\ -{\displaystyle \frac{I_m}{4}}[-2\sqrt{3}m\sin (4\pi f_{s}t-\phi )+4\cos (2\pi f_{s}t-\phi )+\sqrt{3}m\sin (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [{\theta }_2,2k\pi +{\displaystyle \frac{\pi }{3}}]\end{array}\right.$$

(9)

$$i_{N1\_\max }=\left\{\begin{array}{l}-{\displaystyle \frac{3I_m}{4}}m\cos (\phi ),m\le {\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [2k\pi +{\displaystyle \frac{\pi }{3}},2k\pi +\pi ]\\ -{\displaystyle \frac{I_m}{4}}[2\sqrt{3}m\sin (4\pi f_{s}t-\phi +{\displaystyle \frac{2\pi }{3}})+4\cos (2\pi f_{s}t-\phi -{\displaystyle \frac{\pi }{3}})-\sqrt{3}m\sin (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [2k\pi +{\displaystyle \frac{\pi }{3}},{\theta }_1+{\displaystyle \frac{2\pi }{3}}],{\theta }_1=2k\pi +{\displaystyle \frac{\pi }{6}}-\arccos ({\displaystyle \frac{1}{\sqrt{3}m}})\\ -{\displaystyle \frac{I_m}{4}}[4\cos (2\pi f_{s}t-\phi -{\displaystyle \frac{2\pi }{3}})-3m\cos (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [{\theta }_1+{\displaystyle \frac{2\pi }{3}},{\theta }_2+{\displaystyle \frac{2\pi }{3}}],{\theta }_2=2k\pi +{\displaystyle \frac{11\pi }{6}}+\arccos ({\displaystyle \frac{1}{\sqrt{3}m}})\\ -{\displaystyle \frac{I_m}{4}}[-2\sqrt{3}m\sin (4\pi f_{s}t-\phi +{\displaystyle \frac{2\pi }{3}})+4\cos (2\pi f_{s}t-\phi -\pi )+\sqrt{3}m\sin (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [{\theta }_2+{\displaystyle \frac{2\pi }{3}},\pi ]\end{array}\right.$$

(10)

$$i_{N1\_\max }=\left\{\begin{array}{l}-{\displaystyle \frac{3I_m}{4}}m\cos (\phi ),m\le {\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [2k\pi +\pi ,2k\pi +{\displaystyle \frac{5\pi }{3}}]\\ -{\displaystyle \frac{I_m}{4}}[2\sqrt{3}m\sin (4\pi f_{s}t-\phi +{\displaystyle \frac{4\pi }{3}})+4\cos (2\pi f_{s}t-\phi +\pi )-\sqrt{3}m\sin (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [2k\pi +\pi ,{\theta }_1+{\displaystyle \frac{4\pi }{3}}],{\theta }_1=2k\pi +{\displaystyle \frac{\pi }{6}}-\arccos ({\displaystyle \frac{1}{\sqrt{3}m}})\\ -{\displaystyle \frac{I_m}{4}}[4\cos (2\pi f_{s}t-\phi +{\displaystyle \frac{2\pi }{3}})-3m\cos (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [2k\pi ,{\theta }_2]\mathrm{and}[{\theta }_1+{\displaystyle \frac{4\pi }{3}},{\theta }_2+{\displaystyle \frac{4\pi }{3}}],{\theta }_2=2k\pi +{\displaystyle \frac{11\pi }{6}}+\arccos ({\displaystyle \frac{1}{\sqrt{3}m}})\\ -{\displaystyle \frac{I_m}{4}}[-2\sqrt{3}m\sin (4\pi f_{s}t-\phi +{\displaystyle \frac{4\pi }{3}})+4\cos (2\pi f_{s}t-\phi +{\displaystyle \frac{\pi }{3}})+\sqrt{3}m\sin (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [{\theta }_2+{\displaystyle \frac{4\pi }{3}},2k\pi +{\displaystyle \frac{5\pi }{3}}]\end{array}\right.$$

(11)

The expression for the minimum value of the midpoint current is shown in Equations (12)–(14). If 2πf_st$\in$[2kπ, 2kπ + 2π/3], u_refc = min (u_refa, u_refb, u_refc), as shown in Equation (12). If 2πf_st $\in$ [2kπ + 2π/3, 2kπ + 4π/3], u_refa = min (u_refa, u_refb, u_refc), as shown in Equation (13). If 2πf_st $\in$ [2kπ + 4π/3, 2(k + 1) π], u_refb = min (u_refa, u_refb, u_refc), as shown in Equation (14).

$$i_{N1\_\min }=\left\{\begin{array}{l}{\displaystyle \frac{3I_m}{4}}m\cos (\phi ),m\le {\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [2k\pi ,2k\pi +{\displaystyle \frac{2\pi }{3}}]\\ {\displaystyle \frac{I_m}{4}}[2\sqrt{3}m\sin (4\pi f_{s}t-\phi -{\displaystyle \frac{2\pi }{3}})+4\cos (2\pi f_{s}t-\phi )-\sqrt{3}m\sin (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [2k\pi ,{\theta }_3],{\theta }_3=2k\pi +{\displaystyle \frac{\pi }{2}}-\arccos ({\displaystyle \frac{1}{\sqrt{3}m}})\\ {\displaystyle \frac{I_m}{4}}[4\cos (2\pi f_{s}t-\phi -{\displaystyle \frac{\pi }{3}})-3m\cos (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [{\theta }_3,{\theta }_4],{\theta }_4=2k\pi +{\displaystyle \frac{\pi }{6}}+\arccos ({\displaystyle \frac{1}{\sqrt{3}m}})\\ {\displaystyle \frac{I_m}{4}}[-2\sqrt{3}m\sin (4\pi f_{s}t-\phi -{\displaystyle \frac{2\pi }{3}})+4\cos (2\pi f_{s}t-\phi -{\displaystyle \frac{2\pi }{3}})+\sqrt{3}m\sin (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [{\theta }_4,2k\pi +{\displaystyle \frac{2\pi }{3}}]\end{array}\right.$$

(12)

$$i_{N1\_\min }=\left\{\begin{array}{l}{\displaystyle \frac{3I_m}{4}}m\cos (\phi ),m\le {\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [2k\pi +{\displaystyle \frac{2\pi }{3}},2k\pi +{\displaystyle \frac{4\pi }{3}}]\\ {\displaystyle \frac{I_m}{4}}[2\sqrt{3}m\sin (4\pi f_{s}t-\phi )+4\cos (2\pi f_{s}t-\phi )-\sqrt{3}m\sin (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [2k\pi +{\displaystyle \frac{2\pi }{3}},{\theta }_3+{\displaystyle \frac{2\pi }{3}}],{\theta }_3=2k\pi +{\displaystyle \frac{\pi }{2}}-\arccos ({\displaystyle \frac{1}{\sqrt{3}m}})\\ {\displaystyle \frac{I_m}{4}}[4\cos (2\pi f_{s}t-\phi -\pi )-3m\cos (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [{\theta }_3+{\displaystyle \frac{2\pi }{3}},{\theta }_4+{\displaystyle \frac{2\pi }{3}}],{\theta }_4=2k\pi +{\displaystyle \frac{\pi }{6}}+\arccos ({\displaystyle \frac{1}{\sqrt{3}m}})\\ {\displaystyle \frac{I_m}{4}}[-2\sqrt{3}m\sin (4\pi f_{s}t-\phi )+4\cos (2\pi f_{s}t-\phi -{\displaystyle \frac{4\pi }{3}})+\sqrt{3}m\sin (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [{\theta }_4+{\displaystyle \frac{2\pi }{3}},2k\pi +{\displaystyle \frac{4\pi }{3}}]\end{array}\right.$$

(13)

$$i_{N1\_\min }=\left\{\begin{array}{l}{\displaystyle \frac{3I_m}{4}}m\cos (\phi ),m\le {\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [2k\pi +{\displaystyle \frac{4\pi }{3}},2(k+1)\pi ]\\ {\displaystyle \frac{I_m}{4}}[2\sqrt{3}m\sin (4\pi f_{s}t-\phi +{\displaystyle \frac{2\pi }{3}})+4\cos (2\pi f_{s}t-\phi +{\displaystyle \frac{2\pi }{3}})-\sqrt{3}m\sin (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [2k\pi +{\displaystyle \frac{4\pi }{3}},{\theta }_3+{\displaystyle \frac{4\pi }{3}}],{\theta }_3=2k\pi +{\displaystyle \frac{\pi }{2}}-\arccos ({\displaystyle \frac{1}{\sqrt{3}m}})\\ {\displaystyle \frac{I_m}{4}}[4\cos (2\pi f_{s}t-\phi +{\displaystyle \frac{\pi }{3}})-3m\cos (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [{\theta }_3+{\displaystyle \frac{4\pi }{3}},{\theta }_4+{\displaystyle \frac{4\pi }{3}}],{\theta }_4=2k\pi +{\displaystyle \frac{\pi }{6}}+\arccos ({\displaystyle \frac{1}{\sqrt{3}m}})\\ {\displaystyle \frac{I_m}{4}}[-2\sqrt{3}m\sin (4\pi f_{s}t-\phi +{\displaystyle \frac{2\pi }{3}})+4\cos (2\pi f_{s}t-\phi )+\sqrt{3}m\sin (\phi )],\\ m>{\displaystyle \frac{1}{\sqrt{3}}},2\pi f_{s}t\in [{\theta }_4+{\displaystyle \frac{4\pi }{3}},2(k+1)\pi ]\end{array}\right.$$

(14)

The relationship between the DC-link capacitor voltage ripple and midpoint current is:

$$\Delta U_N={\displaystyle \frac{1}{3C}}{\displaystyle \int i_{N1}dt}$$

(15)

where C is the capacitance value of the DC-link capacitor. When the 4L-ANPC inverter operates normally, i_N1 is i_{N1_max} or i_{N1_min}. Therefore, when ΔU_N is zero:

$$i_{NP\_\min }\ge 0\mathrm{and}{i}_{NP\_\max }\le 0$$

(16)

According to Equations (9)–(14), when $m\le {\displaystyle \frac{1}{\sqrt{3}}}$, i_{N1_max} and i_{N1_min} are both DC components, and i_{N1_max} ≤ 0, i_{N1_min} ≥ 0. Therefore, there is no low-frequency ripple in the DC-link capacitor voltage in this modulation index. When $m>{\displaystyle \frac{1}{\sqrt{3}}}$, there are AC components and DC components for both i_{N1_max} and i_{N1_min}. Taking the example of 2πf_st $\in$ [π/3,π], when $2\pi f_{s}t\in [2k\pi +{\displaystyle \frac{\pi }{3}},{\theta }_1+{\displaystyle \frac{2\pi }{3}}]$ in the i_{N1_max} expression, this corresponds to segments $2\pi f_{s}t\in [{\theta }_4,2k\pi +{\displaystyle \frac{2\pi }{3}}]$ and $2\pi f_{s}t\in [2k\pi +{\displaystyle \frac{2\pi }{3}},{\theta }_3+{\displaystyle \frac{2\pi }{3}}]$ in the i_{N1_min} expression. Replacing 2πf_st in the i_{N1_max} expression with 2πf_st-π/3, when $2\pi f_{s}t\in [2k\pi +{\displaystyle \frac{2\pi }{3}},{\theta }_3+{\displaystyle \frac{2\pi }{3}}]$ i_{N1_max} = −i_{N1_min}, the fundamental frequency of its AC component is 3f_s. However, when $2\pi f_{s}t\in [{\theta }_4,2k\pi +{\displaystyle \frac{2\pi }{3}}]$, i_{N1_max} is not equal to −i_{N1_min}, the ripple of this segment cannot be eliminated. For the same reason, when $2\pi f_{s}t\in [{\theta }_1+{\displaystyle \frac{2\pi }{3}},{\theta }_2+{\displaystyle \frac{2\pi }{3}}]$ in the i_{N1_max} expression, corresponding to segments $2\pi f_{s}t\in [{\theta }_3+{\displaystyle \frac{4\pi }{3}},{\theta }_4+{\displaystyle \frac{4\pi }{3}}]$ in the i_{N1_min} expression, the ripple of this segment can also eliminated, while the other segments cannot be. When $2\pi f_{s}t\in [{\theta }_2+{\displaystyle \frac{2\pi }{3}},\pi ]$ in the i_{N1_max} expression, corresponding to segments $2\pi f_{s}t\in [{\theta }_4+{\displaystyle \frac{2\pi }{3}},2k\pi +{\displaystyle \frac{4\pi }{3}}]$ in the i_{N1_min} expression, the ripple can be eliminated. Therefore, most of the ripple can be eliminated during the whole cycle, and other parts of the ripple can only be weakened, and with the increase in the modulation index, the capacitance voltage ripple amplitude will also increase.

3. Analysis of Simulation Results

A simulation model of the 4L-ANPC inverter has been developed using Matlab/Simulink to validate the proposed “variable reference + zero-sequence injection” method. The specifications for the 4L-ANPC inverter are detailed in

Table 1. Simulation parameter.

Parameter	Value
DC-link voltage Udc	50 V
DC-link capacitors	1.32 mF
Switching frequency fs	10 kHz
LR Load	5 mH, 10 Ω
Fundamental current	2 Hz

. Figure 5 presents the modulating waveform for the variable reference voltage balancing method, along with the resulting PWM switching signal.

With the application of the “variable reference” voltage balancing method, the capacitor voltage of the 4L-ANPC inverter is maintained at 50 V. Key simulation results for the 4L-ANPC inverter are illustrated in Figure 6 and Figure 7, with a modulation index of 0.95. The intermediate capacitor voltage U_C2 is stabilized at 16.7 V, which is 1/3 of the DC-link voltage, verifying the effectiveness of the “variable reference” voltage balancing method. However, the voltage ripple is up to about 10 V for the upper and lower capacitors, and the intermediate capacitor voltage ripple is up to 1 V. This is high for a DC-link voltage of only 50 V. When the “variable reference + zero-sequence injection” method is used, the upper and lower capacitor voltage ripple is less than 0.1 V, and the voltage ripple of the intermediate capacitor is around 0.1 V. It is demonstrated that the variable reference + zero-sequence injection method is more effective in suppressing the low-frequency ripple of the capacitor voltage.

The phase current and its FFT analysis using the “variable reference” method are presented in Figure 8a and Figure 9a. The red line indicates the current analyzed for one cycle. The phase current exhibits a fundamental frequency of 2 Hz, with significant waveform distortion, resulting in a total harmonic distortion (THD) of 10.56%. When the “variable reference + zero-sequence injection” method is used, the waveform is a standard sinusoidal waveform, with a THD of 0.26%, as shown in Figure 9b. This shows that the “variable reference + zero-sequence injection” method has a better effect in improving phase current THD.

4. Verification of Experimental Results

To validate the theoretical analysis, an experimental prototype of the 4L-ANPC inverter has been constructed, shown in Figure 10. The experimental parameters are consistent with the simulation parameters. The proposed “variable reference + zero-sequence injection” method is implemented and validated using a digital chip TMS320F28379 from Texas Instruments (Dallas, TX, USA).

Figure 11 shows the measured three-phase line voltage, the phase current i_a, and the DC-link capacitor voltages U_c1, U_c2, and U_c3 of the 4L-ANPC inverter. The results are obtained with the application of the “variable reference” method. Figure 11a shows that at a modulation index of 0.3, the line voltage exhibits only 5 levels with voltage fluctuations. As the modulation index increases to 0.6 and 0.95, the line voltage extends to 7 levels with voltage fluctuations. However, with higher modulation indices, the load current waveform becomes increasingly distorted, while the capacitor voltages U_c1 and U_c3 remain balanced. Figure 11b demonstrates that the amplitude of the upper and lower capacitor voltage ripple increases with the modulation index. When the modulation index is 0.95, the upper and lower capacitor voltage ripple is around 20 V, the load current distortion is serious. The FFT analysis of the load current is shown in Figure 12. Its harmonics are mainly distributed near the switching frequency, and the highest harmonic peak is −15.60 dBA.

Figure 13 shows the measured three-phase line voltage, phase current i_a, and the capacitor voltages U_c1, U_c2, and U_c3 of the 4L-ANPC inverter. In this case, the 4L-ANPC inverter applies the “variable reference + zero-sequence injection” method. Compared to the variable reference method, Figure 13a shows that at a modulation index of 0.3, the line voltage exhibits still only 5 levels, but the voltage fluctuation disappears. Figure 13b shows that the amplitude of the capacitor voltage ripple increases only slightly with the modulation index. At a modulation index of 0.3, the DC capacitor voltage ripple is almost negligible. This demonstrates that the “variable reference + zero-sequence injection” method can suppress the low-frequency ripple of the capacitor voltage at any modulation index.

The FFT analysis of the load current is presented in Figure 14. When the load current maintains a standard sinusoidal waveform at a modulation index of 0.95, its harmonics are predominantly concentrated near the switching frequency, with the highest harmonic peak at −37.42 dBA. Additionally, compared to the “variable reference” method, the harmonic distribution is more uniform in Figure 14. The experimental results demonstrate that the “variable reference + zero-sequence injection” method is more effective in suppressing the low-frequency ripple in the capacitor voltage, thereby confirming the accuracy of the theoretical analysis.

To more intuitively assess the effectiveness of the “variable reference + zero-sequence injection” method in suppressing the low-frequency ripple of the capacitor voltage, a modulation index of 0.95 is used as an example. Relevant experimental data for each modulation method are compared and analyzed. Figure 15 presents the experimental results of capacitor voltages under different modulation methods. Figure 15a illustrates the transition from the conventional CBPWM method to the variable reference voltage balancing method, highlighting the change from unbalanced to balanced upper and lower capacitor voltages. Although the upper and lower capacitor voltages have been balanced at 1/3Udc, the ripple amplitude is still as high as 20 V, and the load current waveform is still heavily distorted. Figure 15b shows the experimental results of the 4L-ANPC inverter when switching from the conventional CBPWM method to the “variable reference + zero-sequence injection” method. The capacitor voltage ripples are less than 5 V, and the load current becomes a standard sinusoidal waveform.

Figure 16 displays the experimental results of the line voltage for various modulation methods. Figure 16a illustrates the transition from the conventional CBPWM method to the “variable reference + zero-sequence injection” method. In Figure 16a, the line voltage has only five levels, and there are obvious voltage fluctuations in the line voltage; whereas, the 4L-ANPC line voltage after the injection of the zero-sequence signal has seven levels, and the voltage fluctuations disappear because the low-frequency pulsations are suppressed. Figure 16b shows the transition from the “variable reference” method to the “variable reference + zero-sequence injection” method. Under the “variable reference” balancing method, the line voltage waveform has seven levels, and there are also significant voltage fluctuations in this waveform due to the large amplitude of the upper and lower capacitor voltages, which disappear after the injection of the zero-sequence signal. Figure 17 shows the experimental results of the capacitor voltages U_c1, U_c2, and U_c3 during two modulation methods. Figure 17a depicts the transition from the “variable reference + zero-sequence injection” method to the conventional CBPWM method, and then, back to the “variable reference + zero-sequence injection” method. Figure 17b illustrates the transition from the “variable reference” method to the “variable reference + zero-sequence injection” method, and then, back to the “variable reference” method. It can be found that the amplitude of the upper and lower capacitor voltages is too large under the “variable reference” balancing method. The experimental results indicate that the proposed “variable reference + zero-sequence injection” method effectively reduces load current distortion and suppresses the low-frequency ripple in the capacitor voltage of the 4L-ANPC inverter, regardless of the modulation method used.

5. Conclusions

In this paper, a straightforward zero-sequence injection method for the CBPWM of a 4L-ANPC inverter is proposed. The injected zero-sequence voltage is determined based on three reference voltage signals and the DC-link capacitor voltage. This method does not require predictive modeling or redundant switching to ascertain the zero-sequence voltage signal. Additionally, the paper elucidates the mechanism behind the upper and lower capacitor voltage imbalance in the four-level inverter and introduces the reference voltage balancing method employed. Furthermore, a theoretical analysis is conducted to explain how the “zero-sequence injection” method suppresses or eliminates the upper and lower capacitor voltage ripples. The method is combined with the variable reference voltage balancing control to achieve balanced upper and lower capacitor voltages and suppress their low-frequency voltage fluctuations as well. The experimental results of upper and lower capacitor voltages, phase currents, and line voltages across three methods—conventional CBPWM, “variable reference”, and “variable reference + zero-sequence injection”—are provided. These results demonstrate the effectiveness of the proposed method in mitigating low-frequency voltage fluctuations in the upper and lower capacitor voltages. Additionally, the suppression effect of the proposed method on the capacitor voltage ripple is compared across different modulation indices to verify the accuracy of the theoretical analysis.