Carrier Mobility Enhancement in Ultrathin-Body InGaAs-on-Insulator n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors Based on Dual-Gate Modulation

Abstract

As a promising candidate for More Moore technology, InGaAs-based n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) have attracted growing research interest, especially with InGaAs-on-insulator (InGaAs-OI) configurations aimed at alleviating the short channel effects. Correspondingly, the fabrication of an ultrathin InGaAs body becomes necessary for the full depletion of the channel, while the deteriorated semiconductor–insulator interface-related scattering could severely limit carrier mobility. This work focuses on the exploration of carrier mobility enhancement strategies for 8 nm body-based InGaAs-OI nMOSFETs. With the introduction of a bottom gate bias on the substrate side, the conduction band structure in the channel was modified, relocating the carrier wave function from the InGaAs/Al₂O₃ interface into the body. Resultantly, the channel mobility with an inversion layer carrier concentration of 1 × 10¹³ cm⁻² was increased by 62%, which benefits InGaAs-OI device application in monolithic 3D integration. The influence of the dual-gate bias from front gate and bottom gate on gate stability was also investigated, where it has been unveiled that the introduction of the positive bottom gate bias is also beneficial for gate stability with an alleviated orthogonal electric field.

1. Introduction

As the scaling down of conventional silicon-based devices becomes increasingly challenging, enormous efforts are dedicated to alternative channel materials and device structures to facilitate the continuous advancement of the metal-oxide-semiconductor field-effect transistor (MOSFET) technology [1,2,3,4,5]. Three five compounds (III-V compounds) material typified by InGaAs have attracted wide research interest due to their intrinsically higher electron mobility and the low effective mass of the carriers. Correspondingly, InGaAs nMOSFETs have been investigated, and various improvements have been made in the last few decades [6,7,8,9,10]. To suppress the short-channel effect and enable a large-scale and cost-effective integration with the silicon platform, device configuration of InGaAs-on-insulator (InGaAs-OI) has been developed [11,12,13,14,15,16]. And, to realize the fully-depleted (FD) operation mode for lower channel leakage and higher gate controllability, an ultrathin InGaAs body with a sub-10 nm thickness is preferred. Meanwhile, three-dimensional (3D) integration technology [17,18], including III-V-OI devices, is widely investigated to achieve lower power consumption and high performance. Developing ultrathin-body InGaAs-OI devices with low thermal budgets and process compatibility possibilities is urgent.

Previous research mainly focused on material preparation and device processing technologies. For the fabrication of a thin InGaAs layer on an insulator, the wafer bonding-based epitaxial transfer technique offers specific advantages in lattice quality for the InGaAs body, where InP is usually used for the growth substrate [7]. For the device fabrication, the formation of source and drain terminals, as well as the protection of the thin InGaAs film during processing, have posed critical challenges. Then, together with the more critical semiconductor–insulator interface-related scattering effects, carrier mobility could be largely limited and become the main barrier for device applications. The carrier mobility, on the other hand, would directly influence both the static and dynamic performance of the device, e.g., the conduction loss and the switching speed. Thus, to fulfill the merits of the thin InGaAs body-based nMOSFET, specific investigations on device processing technologies and channel conductivity boosting strategies should be conducted.

In this study, an InGaAs-OI nMOSFET with an ultrathin-body (UTB) InGaAs was demonstrated, where the direct wafer bonding (DWB) technique was adopted [19,20]. Meanwhile, junctionless source/drain fabrication technology was adopted, obtaining an on-to-off ratio over 3 × 10⁶ and a gate leakage current as low as 10⁻⁶ μA/μm. Then, this work focuses on the exploration of the carrier mobility enhancement strategy for 8 nm thick body-based InGaAs-OI nMOSFETs. With the introduction of bottom gate bias, the conduction band structure and thus the electron distribution in the thin body has been modified for the lower surface scattering effect, achieving a channel mobility of 377 cm²/V·s at an inversion layer carrier concentration (N_inv) of 1 × 10¹³ cm⁻², with an increase of 62%. Correspondingly, the output current was elevated with preserved gate controllability. As revealed in the TCAD simulations, the relocation of the carrier distribution from the InGaAs/Al₂O₃ interface into the body should have dominated carrier mobility boosting. Gate stability performance was also evaluated, which revealed that the introduction of the positive gate bias could simultaneously benefit the gate stability performance of UTB InGaAs-OI nMOSFETs.

2. Experiments

For the ultrathin InGaAs film preparation, an InGaAs film of 8 nm was firstly grown on a temporary substrate of InP via metal–organic vapor phase epitaxy, where the doping concentration of the InGaAs was controlled at ~10¹⁶ cm⁻³, while the In-to-Ga ratio was 53:47. An N-type Ge wafer with a resistivity of 10 ohm·cm was used as the target substrate. The InGaAs and Ge wafers were ultrasonically cleaned using an acetone solution to remove particles on the surface for 1 min. After rinsing in deionized water, both wafers were soaked in a diluted HCI solution of 10% for 30 s. The two wafers were finally rinsed in deionized water before the 50 nm Al₂O₃ deposition in atomic layer deposition (ALD). Subsequently, a direct wafer bonding technique was carried out to bond the InGaAs/InP wafer and Ge wafer together in air. After the post-annealing of 30 min at 300 °C in a vacuum and InP removal in a HCl solution, high-quality InGaAs-OI wafers were ultimately produced. The cross-sectional transmission electron microscope image of an 8 nm thick InGaAs-OI substrate is shown in Figure 1.

The gate-first process was utilized for the fabrication of UTB InGaAs-OI nMOSFETs, as presented in Figure 2. Firstly, the InGaAs-OI substrate was etched by a H₃PO₄:H₂O₂:H₂O solution to define the active areas of the nMOSFET. To fabricate the gate stacks, a NH₄OH solution and deionized water were employed to clean the InGaAs surface, where 15 nm Al₂O₃ was then deposited as the gate oxide in an ALD chamber at 300 °C using precursors of trimethylaluminum (TMA) and H₂O. Thereafter, post-deposition annealing at 400 °C for 30 min in a N₂ ambient was conducted [21,22]. Subsequently, tungsten was sputtered and patterned by a diluted H₂O₂ solution to form the gate electrode. The source and drain were fabricated by the self-aligned process of Ni evaporation and Ni-InGaAs metallization in a N₂ ambient at 400 °C for 1 min [23]. A subsequent Ni deposition and lift-off process was performed for the contact pads. Finally, the Al contact pad was thermally evaporated as the bottom gate. The buried oxide (BOX) thickness was 100 nm in InGaAs-OI nMOSFETs, which resulted from the DWB technique where the oxides from the two wafers were bonded.

3. Results and Discussion

Figure 3 presents the transfer and output characteristics of the 8 nm thick InGaAs-OI nMOSFETs with no bottom gate bias, where the channel width (W) and length (L) are 20 μm and 100 μm, respectively. It could be observed that the InGaAs-OI nMOSFET channel has an off-state leakage current below 10⁻⁶ μA/μm, while the on-state current could reach 3.38 μA/μm with a drain voltage (V_d) of 1 V. This contributes to an on-to-off ratio over 3 × 10⁶, verifying the excellent gate control in the InGaAs-OI nMOSFETs. The corresponding maximum transconductance (g_m) and subthreshold swing (SS) were calculated to be 0.1675 μS/μm and 138 mV/dec, respectively. The excellent gate controllability was also validated by the output current, where the channel current increases evidently with the gate bias and remains nearly consistent in the saturation region with a minor drain-induced barrier lowering effect.

In further characterizations, the bottom gate bias was introduced from the bottom of the substrate for the channel carrier distribution modulation [24,25]. Figure 4a shows the transfer characteristics of UTB InGaAs-OI nMOSFETs at various bottom gate biases and a constant V_d of 10 mV. An obvious on-current elevation could be observed where the bottom gate bias changes from negative to positive, suggesting a promoted channel carrier transportation capability. Capacitance–voltage curves at a frequency of 50 kHz and different bottom gate biases were also characterized. As presented in Figure 4b, negative threshold-voltage shifts could also be observed at higher bottom gate biases, agreeing well with the I-V curves. These I-V and C-V characteristics then facilitated the use of the split CV method in the extraction of mobility from the InGaAs-OI nMOSFETs with different bottom gate biases [26]. As the effect of inversion charge frequency response [27,28] may diminish the determination of carrier density in the inversion layer at a high frequency, a relatively lower frequency of 50 kHz was adopted in the carrier mobility calculation using the split CV method.

Based on the transfer and C-V characteristics as shown in Figure 4, the electron mobility of the InGaAs-OI nMOSFET under different bottom gate biases could be extracted based on the following formula:

$$q{N}_{inv}\left(V_{fg},V_{bg}\right)={{\displaystyle \int }}_{-\infty }^{V_{fg}}{\mathrm{C}}_{gc}d{V}_{fg}$$

(1)

$$\mu ={\displaystyle \frac{L}{W}}{\displaystyle \frac{I_d}{V_d}}{\displaystyle \frac{1}{q{N}_{inv}}}$$

(2)

where V_fg is the front gate voltage, V_bg is the bottom gate voltage, C_gc is the capacitance of gate to channel, and μ is the carrier mobility. The corresponding electron mobility results as calculated at different bottom gate biases are presented in Figure 5a. With the application of a positive bottom gate bias, the electron mobility was thoroughly enhanced, especially at higher N_inv. To give a direct comparison of the mobility characteristics without carrier concentration influence, the channel mobility values at the same carrier concentration were extracted and are presented in Figure 5b, where promotions on the channel mobility from the bottom gate can be directly observed.

For the analysis of the underlying mechanism of the electron mobility elevation, Sentaurus TCAD simulations were conducted for the numerical calculation of the electron distribution in the 8 nm thick InGaAs channel [29,30]. The InGaAs-OI structure is shown in Figure 6, with the 8 nm thick InGaAs of 10¹⁶ cm⁻³ and 100 nm thick Al₂O₃ as the buried oxide and Ge substrate of 10¹⁷ cm⁻³. Fifteen nanometers of Al₂O₃ was deposited on the InGaAs film as the front gate oxide. Front gate bias and back gate bias were employed by metal gates. Figure 6 gives the simulation results at different bottom gate biases with the same N_inv of 1 × 10¹³ cm⁻². It could be observed that, with the bottom gate bias changing from negative to positive, electrons in the InGaAs thin body were gradually redistributed with peak electron density moving from the InGaAs/Al₂O₃ interface into the InGaAs body. This redistribution could then suppress the interface-related scattering, on the one hand and facilitate the electron drift process with an alleviated crowding effect on the other hand. That is, in comparison to the state with electrons accumulated and localized at the interface, the uniform electron distribution in the relatively thicker channel region should be more beneficial for channel mobility. Meanwhile, the uniform distribution profile should have additional advantages in heat dissipation capability, which could then diminish the self-heating effect and also the corresponding phonon-scattering-related mobility degradations. Therefore, the relocation of the carrier wave function from the InGaAs/Al₂O₃ interface into the body should have contributed to the enhanced channel mobility, which also suggests a promising approach for channel mobility improvement via electron wave function modification.

Moreover, in this InGaAs-OI structure with a UTB InGaAs film, it could be expected that the bottom gate bias would introduce an extra electric field perpendicular to the carrier transport direction. This vertical electric field could induce carrier spilling or tunneling from the channel into the InGaAs/Al₂O₃ interface or the dielectric, which could then lead to gate stability problems [31,32]. Therefore, additional evaluations are needed on the influence of gate bias with the dual-gate configuration introduced in this work. As presented in Figure 7, a specific kink effect could be observed in the high-frequency (1 MHz) C-V measurements, which reveals the existence of the electron trapping process that could form an equivalent negative floating gate and lower the capacitance value. That is, with front gate bias increasing positively, the electron trapping could occur and cause the abrupt drop in capacitance as a result of the diminished inversion channel thickness. Then, with the increase in bottom gate bias in the positive direction, the kink position shifts to the right and becomes nearly eliminated at a bottom bias of 5 V. This should be attributed to the alleviation of the orthogonal electric field with the similar bias at the two opposite gate terminals, where then the electron trapping process, as assisted by the increasing front gate, bias is mitigated. Correspondingly, a moderate bottom gate bias should be chosen in consideration of the front gate bias, where two similar positive bias voltages are generally preferred. Therefore, considering that enough positive front gate bias is usually needed to guarantee the inversion and thus the turning of the channel, the introduction of a positive bottom gate bias, e.g., 5 V, would simultaneously benefit channel mobility and gate stability.

4. Conclusions

In this work, high-performance UTB InGaAs-OI nMOSFETs were fabricated based on direct wafer bonding technique and self-aligned gate-first process. By introducing the bottom gate terminal at the bottom of the substrate for the channel carrier distribution modulation, the transistor obtained elevated channel mobility and thus a larger output current with preserved gate controllability. A series of measurements and simulation results suggest that the migration of the electron wave function towards the InGaAs channel body from the InGaAs/Al₂O₃ interface with a more uniform electron distribution should have dominated the mobility boosting. Ultimately, together with the investigations on the gate stability dependence on the dual gate bias, it has been revealed that positive bottom gate bias could simultaneously contribute to higher gate stability, paving a specific way of channel engineering towards advanced InGaAs-OI nMOSFET technology.