A Memristor-Based Circuit with the Loser-Take-All Mechanism for Classification

Abstract

Traditional multi-class classification circuits mostly use the mechanism of winner-take-all. In this paper, a memristor-based classification circuit with the loser-take-all mechanism is designed. The winner-take-all mechanism selects the most active neuron or signal while suppressing others, whereas the loser-take-all mechanism suppresses the most active and amplifies weaker signals. The goal of the loser-take-all mechanism is to determine which class an item does not belong to, rather than to determine which class the item belongs to. The loser-take-all mechanism can use relatively undemanding criteria to correctly classify the majority of categories that are misclassified by the winner-take-all mechanism. The designed circuit includes input modules, control modules and suppression modules which realize the multi-classification function based on the loser-take-all mechanism. The simulation results in Cadence show that the circuit can be used to realize complicated classification applications. The memristor-based classification circuit with the loser-take-all mechanism can capture the subtle nuances of various categories and provide a flexible approach to classification tasks.

1. Introduction

Multi-class classification is a research hotspot in classification circuits. In traditional multi-class classification [1,2], the goal is to find an optimal decision boundary that maximizes the correct classification of classes. Loser-take-all is a mechanism used in various computational models and neural networks to identify the minor element among a group of competing elements [3]. The loser-take-all mechanism has broad applications, including image recognition [4], decision-making systems [5], and associative memory models [6,7,8,9,10,11,12]. In current research, few researchers utilize analog circuits for multi-class classification due to the limitations of circuit devices. Nonvolatile resistive memory devices have been invented based on biomaterial or conventional oxides; they provide a new approach for circuit design [13]. As a passive two-terminal device, memristor plays an essential role in analog circuits by advantages of its nanoscale size, non-linearity, memory function and other characteristics [14,15,16,17,18,19]. Benefiting from the dynamic characteristics of memristor, the simple hyperchaotic memristor circuit with attractor evolution and large-scale parameter permission was designed in [20]. The dynamic characteristics of memristors are highly similar to those of neural synapses, which provides conditions for realizing neuromorphic computing by building analog circuits [21,22,23,24,25]. With memristor as the core device, memristive neural network circuits have been implemented in various applications, such as operant conditioning and image recognition [26,27].

A number of studies of multi-class classification based on memristive circuits have been implemented so far. A memristor-based cascaded framework was proposed to improve specific target recognition in [28]. A circuit-based hybrid quantum convolutional neural network was proposed as an image classifier in [29]. In [30], an automatic sorting system was proposed to classify electronic components from waste printed circuit boards. In [31], an analog circuit was designed to remove noise in images and a digital image filtering method called median filtering was proposed. A complete design of a memristive network circuit was proposed in [32]. It can solve hardware acceleration of long short-term memory and improve the accuracy of network classification. However, most studies do not consider the loser-take-all mechanism in multi-class classification circuits.

The loser-take-all mechanism is a decision-making process where only one part emerges as the loser. For the loser-take-all mechanism, the neuron with the weakest activation becomes active while the stronger ones are suppressed. The mechanism plays a significant role in determining outcomes. In the manufacturing industry, a classification circuit with the loser-take-all mechanism can be used to classify and inspect different types of products. It can be employed to inspect electronic components, automotive parts, food packaging, etc., ensuring that the products meet standards and specifications. Products that can not meet the standards and specifications are rejected.

In this paper, a memristor-based classification circuit with the loser-take-all mechanism is designed to realize multi-class classification based on the loser-take-all mechanism. Compared with the works based on the winner-take-all mechanism, the method based on the loser-take-all mechanism has the following advantages: (1) Compared with the winner-take-all mechanism and the online Hebbian learning rule implemented in [33], the loser-take-all mechanism allows a larger number of neurons to remain active, encouraging more distributed and diverse representations which can be helpful in tasks requiring exploration or generating multiple hypotheses. (2) Compared with the winner-take-all mechanism for the memristor-based neural network proposed in [34], the loser-take-all mechanism avoids dominance by the strongest neuron and ensures that the weaker signals are given a chance to activate, which can be useful in scenarios where multiple inputs should be considered simultaneously. (3) Compared with the winner-take-all circuits in competitive neural networks designed in [35], the loser-take-all mechanism is useful for detecting rare or unexpected signals because it allows neurons that do not typically win competitions to become active. The comparison of the advantages and disadvantages of the loser-take-all and winner-take-all mechanism is shown in

Table 1. Comparison of the advantages and disadvantages of loser-take-all and winner-take-all mechanisms.

Mechanism	Advantages	Disadvantages
Loser-Take-All (LTA)	Diversity of Activation: LTA allows a larger number of neurons to remain active, encouraging more diverse representations.	Increased Complexity: LTA is more complex computationally, as it requires multiple neurons to remain active.
	Prevents Dominance: LTA avoids dominance by the strongest neuron and ensures that the weaker signals are given a chance to activate.	Less Noise Filtering: Since more neurons remain active, LTA can be more susceptible to noise and irrelevant stimuli, making it harder to converge on a single solution.
	Novelty Detection: LTA is useful for detecting rare or unexpected signals because it allows neurons that do not typically win competitions to become active.	Energy Inefficiency: Activating the weakest neurons can be computationally inefficient since the system might be processing less relevant or less informative signals, leading to wasted resources.
Winner-Take-All (WTA)	Sparse Representations: WTA enforces sparse coding which can be beneficial for efficiency as it reduces the number of active neurons.	Lack of Diversity: It often fails to capture diverse or parallel features as only the strongest neuron activate.
	Noise Reduction: By allowing only the most active neuron to respond, WTA reduces the influence of noisy or irrelevant inputs.	Over-Suppression: WTA may suppress valuable information contained in weaker signals, which can limit the system’s ability to process subtle or multi-faceted input patterns.
	Energy Saving: WTA promotes sparsity in neural activation, which reduces energy consumption and improves computational efficiency.	Local Optima: The competition may result in a suboptimal choice if the winning neuron is not truly representative of the best solution, particularly in complex or ambiguous situations.

.

Compared to prior research, the present study exhibits distinctive characteristics across the following aspects. First of all, the proposed memristor-based classification circuit with the loser-take-all mechanism utilizes the loser-take-all mechanism to classify signals. Compared with works [28,29,30], the circuit in this paper can realize faster decision-making and improve classification accuracy. In addition, the selective modules based on memristor make the threshold adjustable, allowing the circuit to be flexibly constructed according to different requirements, expanding the application range of the circuit. Finally, the input module can simplify the input signal and facilitate the subsequent recognition compared to the previous circuits [29,30,31]. Compared with works [29,30,31], the selective module can effectively eliminate the interference targets and improve the reliability of our circuit. Our work uses a simple analog circuit to realize the high-accuracy classification of different inputs.

This work is presented as follows: in Section 2, a threshold memristor model is introduced. The modules of circuit are exhibited in Section 3. The whole circuit and simulation results are introduced in Section 4. In Section 5, some conclusions are finally obtained.

2. Memristor Model with Threshold

Various memristors have been designed [36,37,38,39,40,41,42,43]. In this paper, a threshold memristor model based on AIST (AgInSbTe) is chosen; it prevents the boundary effect [44]. The model is described as

$$M\left(t\right)=R_{on}{\displaystyle \frac{w\left(t\right)}{D}}+R_{off}(1-{\displaystyle \frac{w\left(t\right)}{D}})$$

(1)

where $M\left(t\right)$ is the memristance, $R_{off}$ denotes highly doped resistance, $w\left(t\right)$ is the width of the high doped region, D is the full thickness of memristive material. $R_{on}$ is low-doped resistance. The derivative of the state variable $w\left(t\right)$ is

$${\displaystyle \frac{dw\left(t\right)}{dt}}=\left\{\begin{array}{cc}{\mu }_v{\displaystyle \frac{R_{ON}}{D}}{\displaystyle \frac{i_{off}}{i\left(t\right)-i_0}}f\left(w\left(t\right)\right),\hfill & v\left(t\right)>V_{T+}>0\hfill \\ 0,\hfill & V_{T-}⩽v\left(t\right)⩽V_{T+}\hfill \\ {\mu }_v{\displaystyle \frac{R_{ON}}{D}}{\displaystyle \frac{i\left(t\right)}{i_{on}}}f\left(w\left(t\right)\right),\hfill & v\left(t\right)<V_{T-}<0\hfill \end{array}\right.$$

(2)

where ${\mu }_v$ stands for the ionic mobility, $i_0$, $i_{on}$ and $i_{off}$ are constants. $V_{T+}$ and $V_{T-}$ are positive and negative threshold voltages, respectively. $f\left(w\right(t\left)\right)$ is given as a window function

$$f\left(w\left(t\right)\right)=1-{({\displaystyle \frac{2w\left(t\right)}{D}}-1)}^{2p}$$

(3)

These parameter settings of memristors in the circuit are shown in

Table 2. Parameters of memristors.

Parameters	Memristor 1	Memristor 2
$D\left(nm\right)$	3	3
$R_{init}(\Omega )$	2 k	2 k
$R_{OFF}(\Omega )$	5 k	100 k
$R_{ON}(\Omega )$	1 k	2 k
$V_{T+}\left(V\right)$	$0.5$	25
$V_{T-}\left(V\right)$	$-0.5$	$-25$
${\mu }_v\left(m^2{s}^{-1}{\Omega }^{-1}\right)$	1.6 $\times {10}^{-19}$	1.6 $\times {10}^{-18}$
$i_{on}\left(A\right)$	1	1
$i_{off}\left(A\right)$	1 $\times {10}^{-5}$	1 $\times {10}^{-5}$
$i_0\left(A\right)$	1 $\times {10}^{-4}$	1 $\times {10}^{-4}$
p	10	10

. $M_1$, $M_3$, $M_5$, $M_7$, $M_9$, $M_{11}$, $M_{13}$, $M_{15}$, $M_{17}$, $M_{28}-M_{32}$, $M_{34}-M_{38}$, $M_{40}-M_{44}$ in the circuit are Memristor 1 in Table 2. The other memristors in the circuit are Memristor 2 in Table 2.

The memristance is reduced if the positive voltage applied to the memristor is greater than $V_{T+}$. The memristance is increased if the negative voltage applied to the memristor is lesser than $V_{T-}$. The greater the positive voltage, the slower $w\left(t\right)$ increases, and the slower the memristance decreases. Figure 1 shows the curves of the memristance when these memristors are applied by different voltages. The pulse voltage and direct current voltage are designed to study the memristance change characteristics of Memristor 1 and Memristor 2, respectively. All the simulation processes in this paper are implemented by Cadence.

3. Modules of Circuit Design

3.1. Input Module

The input module is shown in Figure 2. The input module is used to filter out the noise interference in input signals. The input module can convert the complex target signal into an easily identifiable pulse signal. The module uses a simple circuit to process the initial image, which is convenient for subsequent detection and reduces the difficulty of classification. $I{N}_1$ is the input signal without processing. $OU{T}_1$ is the processed input signal. $C{M}_1$ is a voltage comparator. $Bu{f}_1$ is a buffer. $OU{T}_1$ changes from $V_1$ to 0 V when the input voltage $I{N}_1$ reaches 0 V from a positive voltage. The function of the output voltage of the input module is

$$V_{OUT1}=\left\{\begin{array}{cc}{V}_1,\hfill & V_{IN1}>0\hfill \\ 0,\hfill & V_{IN1}⩽0\hfill \end{array}\right.$$

(4)

The initial memristance of $M_1$ is $2\mathrm{k}\Omega$. If $V_{IN1}>0.5\mathrm{V}$, the memristance of $M_1$ decreases to $1\mathrm{k}\Omega$. If $V_{IN1}<-0.5\mathrm{V}$, the memristance of $M_1$ increases to $5\mathrm{k}\Omega$. If $R_1$, $R_2$, $V_1$ and $O{P}_1$ are constructed as a simple comparator. $O{P}_1$ outputs $V_1$ when the non-inverting input voltage of $O{P}_1$ is greater than the inverting input voltage of $O{P}_1$. $Bu{f}_1$ can reduce signal distortion during transmission by providing low output impedance. It improves the waveform of the signal and maintains signal integrity. The initial memristance of $M_2$ is $2\mathrm{k}\Omega$. The connection mode of $M_2$ is a reverse connection. When the applied voltage is greater than $V_{T+}$ in $M_2$, the memristance of $M_2$ increases from $2\mathrm{k}\Omega$ to $100\mathrm{k}\Omega$ in a short time. The voltage of $OU{T}_1$ is limited to a meager value. It can prevent excessive input voltage from damaging the circuit in this paper. The simulation results of the input module are shown in Figure 3. Input types 1 and 2 are triangle and trapezoid signals, respectively. Triangle and trapezoid signals become regular pulse signals after the filtration of the input module.

3.2. Voltage Control Module

The circuit of the voltage control module is shown in Figure 4. The voltage control module in the circuit reflects the principle of classification. The voltage control module is designed for classification based on the loser-take-all mechanism. Three input signals are randomly assigned together for classification. $I{N}_1$–$I{N}_9$ are randomly assigned to three groups. Voltage control Modules 1–9 are designed for primary classification by the loser-take-all mechanism. The output signals of primary classification are subjected to secondary classification. $I{N}_1$, $I{N}_2$ and $I{N}_3$ are inputs. $D_1$ is an OR gate. $C{M}_{10}$ and $C{M}_{11}$ are voltage comparators. $OU{T}_2$ is the output voltage of the voltage control module. The memristance of $M_{19}$ and $M_{20}$ is regulated by the output voltage of $C{M}_{10}$ and $C{M}_{11}$, respectively. The ports of $V_{-}$ in $C{M}_{10}$ and $C{M}_{11}$ are connected to ground. The ports of $V_{+}$ in $C{M}_{10}$ and $C{M}_{11}$ are connected to $I{N}_1$. $C{M}_{10}$ outputs the voltage of $V_{+}$ when the inverting port voltage exceeds the non-inverting port voltage. On the contrary, $C{M}_{10}$ outputs 0 V. The principle of $C{M}_{11}$ is the same as $C{M}_{10}$. The mathematical formula of $C{M}_{10}$ is as follows:

$$V_{CM10}=\left\{\begin{array}{cc}{V}_{IN1},\hfill & V_{IN1}<V_{IN2}\hfill \\ 0,\hfill & V_{IN1}⩾V_{IN2}\hfill \end{array}\right.$$

(5)

The mathematical formula of $C{M}_{11}$ is as follows:

$$V_{CM11}=\left\{\begin{array}{cc}{V}_{IN1},\hfill & V_{IN1}<V_{IN3}\hfill \\ 0,\hfill & V_{IN1}⩾V_{IN3}\hfill \end{array}\right.$$

(6)

M₁₉, $R_{21}$ and $O{P}_1$ are implemented as a basic amplifier. The mathematical formula is $V_{OP1}=R_{21}/M_{19}$. If the memristance of $M_{19}$ increases to $100\mathrm{k}\Omega$, $V_{OP1}$ drops to a very low value. The principle of $O{P}_2$ is the same as $O{P}_1$.

3.3. Selective Module

The selective module is shown in Figure 5. $D_{10}$ and $D_{11}$ are OR gates. $O{P}_{19}$–$O{P}_{21}$ are precision operational amplifiers. $C{M}_{28}$ and $C{M}_{29}$ are voltage comparators. $Bu{f}_{10}$ is a buffer. $OU{T}_2$ is the output voltage of the voltage control module. $OU{T}_3$ is the output voltage of the selective module. $M_{37}$, $R_{55}$ and $O{P}_{19}$ are implemented as a basic amplifier. The mathematical formula is $V_{OP19}=R_{55}/M_{37}$. The mathematical formula of $V_{OP20}$ is $V_{OP20}=R_{56}/M_{38}\times V_{10}$. The mathematical formula of $V_{OP21}$ is $V_{OP21}=R_{57}/M_{39}\times V_{11}$. $C{M}_{28}$ outputs $V_{OP19}$ when $V_{OP19}>V_{OP20}$. $C{M}_{29}$ outputs $V_{OP19}$ when $V_{OP19}<V_{OP21}$. The mathematical formula of $OU{T}_3$ is

$$OU{T}_3=\left\{\begin{array}{cc}{V}_{OP19},\hfill & V_{OP20}<V_{OP19}<V_{OP21}\hfill \\ 0,\hfill & V_{OP21}⩽V_{OP19}\mathrm{or}{V}_{OP19}⩽V_{OP20}\hfill \end{array}\right.$$

(7)

The selective module in the circuit receives the input signals from different voltage control modules. The input signals eliminated by voltage control modules can not output from the selective module. The selective module can protect the circuit against damage from excessive or inadequate voltage signals, thereby improving the reliability of the circuit. The output threshold of the circuit in this paper can be adjusted by the selective module. Adjustable voltage threshold can broaden the application range of the circuit.

3.4. Inhibition Module

The inhibition module is shown in Figure 6. The inhibition module in the circuit can inhibit the input signals by the loser-take-all mechanism. Relatively large input signals are inhibited, and the smallest input signals are the final output. Input signals in the inhibition module are from different selective modules. $C{M}_{30}$ and $C{M}_{31}$ are voltage comparators. $D_{12}$ is an AND gate. $O{P}_{22}$ is a precision operational amplifier. $S_1$ is a voltage-controlled switch. The inverting input of the voltage-controlled switch is grounded. $M_{42}$, $R_{62}$ and $O{P}_{22}$ are implemented as a basic amplifier. The mathematical formula is $V_{OP22}=R_{62}/M_{42}$. The mathematical formula of $S_1$ is

$$V_{S1}=\left\{\begin{array}{cc}{V}_{OP22},\hfill & V_{OP22}>0\hfill \\ 0,\hfill & V_{OP22}⩽0\hfill \end{array}\right.$$

(8)

The output voltage of the inhibition module is $V_{S1}$.

4. Circuit Design and Simulation Results

4.1. Memristor-Based Classification Circuit with the Loser-Take-All Mechanism

4.1.1. Diagram of the Complete Circuit

For a typical loser-take-all mechanism, the neurons in the network are interconnected and receive inputs from various sources. These inputs are processed, and the neuron with the lowest output is the “loser”. The network’s response is sparsified, meaning that only a small subset of neurons is activated. As shown in Figure 7, the memristor-based classification circuit with the loser-take-all mechanism in this paper contains nine inputs. $IN1$–$IN9$ are randomly divided into three groups. The loser-take-all mechanism means that the output signal occurs only when the corresponding input does not have the greatest value among all inputs. For three inputs, the random guessing of which class an input belongs to has an accuracy probability of only 1/3. In contrast, the random guessing of which class it does not belong to has an accuracy probability of 2/3. The loser-take-all mechanism improves classification accuracy by identifying which category the input does not belong to. In the primary classification, $P_1$–$P_6$ are classified out by the loser-take-all mechanism. $P_1$–$P_6$ do not belong to the greatest class in $IN1$–$IN9$. In the secondary classification, $S_1$–$S_4$ are classified by the loser-take-all mechanism. $S_1$–$S_4$ do not belong to the greatest class in $P_1$–$P_6$. $V_{OUT}$ is the final output in $S_1$–$S_4$.

4.1.2. Complete Circuit

The memristor-based classification circuit with the loser-take-all mechanism is shown in Figure 8, in which the input module, the voltage control module and the selective module are connected to each other. $I{N}_1$–$I{N}_9$ are different inputs. $V_{OUT}$ is the final output voltage.

4.2. Simulation Results and Analyses

The memristor-based classification circuit with the loser-take-all mechanism is simulated with Cadence 17.2. As shown in Figure 9, $I{N}_1$–$I{N}_9$ are nine inputs in the circuit. $I{N}_1$, $I{N}_2$ and $I{N}_3$ generate voltages of 18 V, 17 V and 16 V, respectively. $I{N}_4$, $I{N}_5$ and $I{N}_6$ generate voltages of 15 V, 14 V and 13 V, respectively. $I{N}_7$, $I{N}_8$ and $I{N}_9$ generate voltages of 12 V, 11 V and 10 V, respectively. The width of each pulse is 2 s, and the period is 4 s. $VO{P}_1$–$VO{P}_6$ are the results of the primary classification in $I{N}_1$, $I{N}_2$ and $I{N}_3$. $VO{P}_1$, $VO{P}_2$ and $VO{P}_4$ output the voltage of 0 V. $VO{P}_3$ outputs the input voltage of $I{N}_2$. $VO{P}_5$ and $VO{P}_6$ output the input voltage of $I{N}_3$. $I{N}_1$ is eliminated in the primary classification. $VO{P}_7$–$VO{P}_{12}$ are the results of the primary classification in $I{N}_4$, $I{N}_5$ and $I{N}_6$. $VO{P}_7$, $VO{P}_8$ and $VO{P}_{10}$ output the voltage of 0 V. $VO{P}_9$ outputs the input voltage of $I{N}_5$. $VO{P}_{11}$ and $VO{P}_{12}$ output the input voltage of $I{N}_6$. $I{N}_4$ is eliminated in the primary classification. $VO{P}_{13}$–$VO{P}_{18}$ are the results of the primary classification in $I{N}_7$, $I{N}_8$ and $I{N}_9$. $VO{P}_{13}$, $VO{P}_{14}$ and $VO{P}_{16}$ output the voltage of 0 V. $VO{P}_{15}$ outputs the input voltage of $I{N}_8$. $VO{P}_{17}$ and $VO{P}_{18}$ output the input voltage of $I{N}_9$. $I{N}_7$ is eliminated in the primary classification. The greatest values of the corresponding inputs are eliminated by the memristor-based classification circuit with the loser-take-all mechanism. At last, $I{N}_2$, $I{N}_3$, $I{N}_5$, $I{N}_6$, $I{N}_8$ and $I{N}_9$ are outputs of the primary classification. The simulation results of two inputs and four inputs are shown in Figure 10. $I{N}_1$ and $I{N}_2$ are the two inputs in the two-input simulation. $I{N}_1$ and $I{N}_2$ generate voltages of 10 V and 5 V, respectively. The width of each pulse is 2 s and the period is 5 s. The voltage of 5 V is the output based on the loser-take-all mechanism in the two-input simulation result. $I{N}_1$–$I{N}_4$ are the four inputs in the four-input simulation. $I{N}_1$, $I{N}_2$, $I{N}_3$ and $I{N}_4$ generate voltages of 10 V, 8 V, 5 V and 3 V, respectively. The voltage of 3 V is the output based on the loser-take-all mechanism in the four-input simulation result. As shown in Figure 11, $I{N}_1$–$I{N}_9$ are different inputs in the circuit. Classification Process 1 occurs from 0 s to 50 s. $I{N}_1$–$I{N}_9$ represent different voltage levels and perform Primary Classification 1 in the initial classification. In Classification Process 1, $I{N}_1$–$I{N}_9$ are 18 V-10 V, respectively. The nine inputs are classified into six outputs after Primary Classification 1. The six inputs are classified into the single output after Scondary Classification 1. $V_{OUT}$ outputs the voltage of 10 V. Classification Process 2 occurs from 50 s to 100 s. In Classification Process 2, $I{N}_1$–$I{N}_9$ are 1 V-9 V, respectively. $V_{OUT}$ outputs the voltage of 1 V.

The simulation results illustrate the application of the loser-take-all mechanism in this circuit. The smallest part can be activated in primary classification and secondary classification. In this circuit, $I{N}_1$–$I{N}_9$ undergo two rounds of classification. One of the nine inputs is ultimately activated based on the loser-take-all mechanism.

Monte Carlo Analysis

Figure 12 is the Monte Carlo analysis simulation results of inputs and outputs. The tolerance value of the resistance setting is $10\%$, and the simulation times are 50. Vsin is the additional sinusoidal interference signal. The DC bias voltage of the sinusoidal interference signal is 0 V, and the AC amplitude is 0.2 V. The frequency of the sinusoidal interference signal is 50 Hz. The simulation results of $V_{OUT}$ are relatively stable and consistent across different tolerance values. The simulation results show that the circuit designed in this paper can run stably under $10\%$ tolerance values.

The power consumption and area of a CMOS circuit depend on the specific implementation and manufacturing process. The method of making an integrated circuit into a compatible platform mentioned in [45,46,47] is used to analyze the circuit in this paper. The calculation area formula of a single memristor is $S_{ME}=4f^2$. $S_{ME}$ represents the area of a single memristor, and f represents half of the minimum distance between two metal wires. Under $0.45\mathsf{\mu }\mathrm{m}$ technology, the areas of the input module, the voltage control module and the selective module are $130.624\mathsf{\mu }{\mathrm{m}}^2$, $80.032\mathsf{\mu }{\mathrm{m}}^2$ and $143.032\mathsf{\mu }{\mathrm{m}}^2$, respectively. Therefore, the area of the circuit in Figure 8 is about $610.48\mathsf{\mu }{\mathrm{m}}^2$. Generally, the area and power consumption decrease with increasing integration density. In [48], the simulation report from Cadence shows that the average power consumption of the resistors and CMOS are 9.79 mW and 2.27 mW, respectively. The average power consumption of the voltage sources and capacitances are $39.2\mathsf{\mu }\mathrm{W}$ and 8.58 pW, respectively. In this paper, the power consumption of resistors and CMOS is considered in the majority. As shown in

Table 3. Comparison with several different papers. The symbol √ indicates that a work has this feature, while the symbol × indicates that the work does not have this feature.

Work	Multiple Recognition Mothod	Signal Processing	Elimination of Interference Signal	Simple Construction	Loser-Take-All
[28]	√	×	√	√	×
[29]	√	×	√	√	×
[30]	√	√	√	×	×
[31]	√	√	√	√	×
[32]	√	×	√	√	×
This work	√	√	√	√	√

, the proposed circuit is compared with different circuits in area and power consumption. In this work, the circuit implements the functions of multiple recognition, signal processing, elimination of interference signal, simple construction and loser-take-all mechanism in classification circuits. Compared with other circuits [28,29,30,31,32], the proposed circuit can effectively operate with lower power consumption and smaller circuit area.

5. Conclusions

In this paper, the memristor-based classification circuit with the loser-take-all mechanism is designed; it can be used for multi-class classification. The circuit is designed for multi-class classification, and the input signals of the circuit include nine signals. The circuit utilizes input modules, voltage control modules, and selective modules to realize the loser-take-all mechanism. Interference signals can be eliminated when the identified signal passes through the input modules. Voltage control modules and selective modules can handle the processed inputs. The final output signals are the classification results of the loser-take-all mechanism. Theoretical analysis and simulation results demonstrate that the circuit achieves multi-class classification based on the loser-take-all mechanism. The stability and robustness of the circuit are verified through Monte Carlo simulation. Additionally, the designed circuit exhibits low power consumption and small area. The design of the memristor-based classification circuit with the loser-take-all mechanism provides valuable insights for the advancement of hardware multi-class classification circuits.