Doherty Power Amplifier Design via Differential Combining

Abstract

This paper introduces a novel differential combiner designed to effectively address parasitic capacitances of transistors used in power amplifier (PA) designs with precise compensation at a specified frequency. The combiner consists of a $\lambda /4$ transmission line with an integrated capacitor of value $2C_{OUT}$ at its midpoint, which ensures accurate cancellation of parasitic effects. This design connects the drain pins of two transistors, which are considered identical in this configuration. By eliminating the need for complex parasitic compensation techniques, this method significantly simplifies the design process of Doherty Power Amplifiers (DPAs). Extensive simulations validate the effectiveness of this approach, highlighting its potential as a versatile and straightforward solution for next-generation communication systems.

1. Introduction

The increasing demand for higher data rates and broader bandwidths in modern communication systems, particularly at millimeter-wave (mmW) frequencies, has driven the need for efficient and reliable power amplifiers (PAs) [1,2]. As frequencies rise, the parasitic effects of transistor output capacitances become more pronounced, leading to challenges in maintaining the PA performance. These parasites can degrade the amplifier’s efficiency and output power, making effective compensation essential. Traditional design approaches often struggle to address these parasitic effects across varying frequencies, limiting the versatility and efficiency of the resulting amplifiers.

On the other hand, achieving high output power at very high frequencies, particularly in the millimeter-wave (mmWave) spectrum, is a formidable challenge, primarily due to the limitations in transistor technology at these frequencies. As the operating frequency increases, the intrinsic gain of transistors diminishes, requiring innovative circuit topologies and design techniques to compensate. Additionally, the physical scaling of transistors to operate at higher frequencies often results in reduced power handling, making it difficult to achieve the desired output power levels. Moreover, the efficiency of power amplifiers tends to decrease as frequency rises, necessitating careful design to balance power output with efficiency. This challenge is compounded by the stringent demands of modern communication systems, which require power amplifiers that can deliver both high power and wide bandwidth, pushing the limits of current design approaches.

In power amplifier design, using parallel combining structures to increase power comes with some issues. Parasitic elements like inductances and capacitances can cause problems with phase and impedance, which can reduce efficiency and stability. Matching networks help address these issues, but add complexity and may cause extra losses. Stacked configurations, where transistors are layered on top of each other, have their own set of problems. Managing voltage distribution is tough, and uneven voltage sharing can lead to device failures or inefficiency. Additionally, simulating these stacked structures is challenging, even with advanced tools, due to the complex interactions between layers [3,4,5,6,7]. Both methods require careful design to work effectively and reliably.

In response to the challenges posed by parasitic capacitances at high frequencies, this work presents a novel differential combiner that effectively compensates for these capacitances at any chosen frequency. By integrating a capacitor with a value of $2C_{OUT}$ at the midpoint of a $\lambda /4$ transmission line, the proposed design ensures precise capacitance cancellation, significantly simplifying the design of Doherty Power Amplifiers (DPAs). This approach not only eliminates the need for complex parasitic compensation techniques, but also enhances the applicability of the design across a wide range of frequencies, including but not limited to mmWave bands. The proposed combiner has been rigorously validated through simulation, demonstrating good performance and highlighting its potential as a versatile and efficient solution for next-generation communication systems [8,9,10]. A DPA was designed and simulated using the proposed combiner, showing competitive results alongside a simplified approach.

Table 1. Comparison with state-of-the-art MMIC DPAs.

Ref	[8]	[9]	[10]	[11]	This Work (Sim.)
BW (GHz)	24–28	24–28	28	27.5–29.5	30–34
${\mathbf{PAE}}_{\mathbf{6}\mathbf{dB}}$ (%)	14–32	18.1–30.1	31	21–24	14–28
${\mathbf{PAE}}_{\mathbf{sat}}$ (%)	23–41	27.8–36.8	42	24–34	24–37
${\mathbf{P}}_{\mathbf{OUT}}$ (dBm)	34–36	35.4–36	26.5	32–33	36.5–37
S. Gain (dB)	11–13	8–11	11.8	8–12	11–14

shows a comparison between the designed DPA and some state-of-the-art DPAs.

2. Proposed Combiner

In [11], a differential combiner was proposed to address the transistors’ output capacitance by summing the currents from each transistor at a specific chosen frequency. While this method is highly effective at relatively high frequencies, its application becomes less appropriate for frequencies outside this range, limiting its versatility. Thus, the main disadvantage of the work in [11] is its limitation when implemented at relatively low frequencies. The load of one of the transistors is frequency-dependent, which significantly impacts the transistor’s load impedances at low frequencies. In this context, the remaining imaginary part in the work shown in [11] affects the desired load modulation expected in DPAs. In contrast, this new combiner theoretically has the ability to eliminate that frequency dependence at the design frequency, allowing it to be used even at relatively low frequencies. The approach presented in this paper builds on and complements this work by enabling compensation across a broader spectrum, theoretically allowing for application at any chosen frequency. This enhancement significantly expands design flexibility and adaptability, making it suitable for a wide range of frequency applications.

In this work, we introduce a new differential combiner that effectively compensates for these capacitances at any chosen frequency, thereby addressing the limitations of the previous design. This is achieved by adding a capacitor with a value of $2C_{OUT}$ exactly at the midpoint of the $\lambda /4$ transmission line proposed in [11]. This innovative approach allows for precise capacitance cancellation, independent of the operating frequency, thereby broadening the combiner’s applicability to a wider range of designs, including those with varying frequency requirements. The proposed combiner is depicted in Figure 1a, where $C_{OUT}$ represents the output capacitance of the transistor used. The simple yet effective addition of this capacitor ensures that the combiner can be employed in various high-frequency applications.

Furthermore, the proposed combiner structure offers additional benefits when the network is loaded with a resistor R, as illustrated in Figure 1. Under these conditions, the load seen at each transistor’s current reference plane becomes $2R$. This characteristic makes the combiner particularly advantageous for use with transistors that require high load impedance, which is a common scenario in millimeter-wave (mmW) applications. This feature not only simplifies the design process for such systems, but also enhances performance by ensuring that the load impedance is optimally matched to the transistors’ requirements.

To validate the functionality of the proposed combiner, we refer to the equivalent circuit presented in Figure 1b. The chosen frequency is called f and $\omega =2\pi f$. Using the ABCD matrix formulation for each network element, the following relationship is obtained for the drain voltages and currents of each device, here represented by $V_1$, $V_2$, $I_1$ and $I_2$:

$$\left[\begin{array}{c}{V}_1\\ I_1\end{array}\right]={\left[\left[\begin{array}{cc}1& 0\\ j\omega C_{OUT}& 1\end{array}\right]\left[\begin{array}{cc}{\displaystyle \frac{1}{\sqrt{2}}}& j{\displaystyle \frac{Z_0}{\sqrt{2}}}\\ j{\displaystyle \frac{1}{\sqrt{2}{Z}_0}}& {\displaystyle \frac{1}{\sqrt{2}}}\end{array}\right]\left[\begin{array}{cc}1& 0\\ j\omega C_{OUT}& 1\end{array}\right]\right]}^2\left[\begin{array}{cc}1& 0\\ {\displaystyle \frac{1}{R}}& 1\end{array}\right]\left[\begin{array}{c}{V}_2\\ -I_2\end{array}\right]$$

(1)

Thus,

$$\left[\begin{array}{c}{V}_1\\ I_1\end{array}\right]={\left[\begin{array}{cc}{\displaystyle \frac{1}{\sqrt{2}}}\left(1-\omega C_{OUT}{Z}_0\right)& j{\displaystyle \frac{1}{\sqrt{2}}}{Z}_0\\ j{\displaystyle \frac{1}{\sqrt{2}}}\left(2\omega C_{OUT}-{\omega }^2{C}_{OUT}^2{Z}_0+{\displaystyle \frac{1}{Z_0}}\right)& {\displaystyle \frac{1}{\sqrt{2}}}\left(1-\omega C_{OUT}{Z}_0\right)\end{array}\right]}^2\left[\begin{array}{cc}1& 0\\ {\displaystyle \frac{1}{R}}& 1\end{array}\right]\left[\begin{array}{c}{V}_2\\ -I_2\end{array}\right].$$

(2)

Specifically, by choosing the characteristic impedance $Z_0$ of the $\lambda /8$ transmission lines to match the impedance of the output capacitance $C_{OUT}$, such that $Z_0={\left(\omega C_{OUT}\right)}^{-1}$, the resulting ABCD matrix simplifies significantly,

$$\left[\begin{array}{c}{V}_1\\ I_1\end{array}\right]=\left[\begin{array}{cc}-1& 0\\ 0& -1\end{array}\right]\left[\begin{array}{cc}1& 0\\ {\displaystyle \frac{1}{R}}& 1\end{array}\right]\left[\begin{array}{c}{V}_2\\ -I_2\end{array}\right]$$

(3)

and, therefore,

$$\left[\begin{array}{c}{V}_1\\ I_1\end{array}\right]=\left[\begin{array}{cc}-1& 0\\ -{\displaystyle \frac{1}{R}}& -1\end{array}\right]\left[\begin{array}{c}{V}_2\\ -I_2\end{array}\right].$$

(4)

By transforming the resulting ABCD matrix into its correspondent Z matrix, (4) can be written as

$$\left[\begin{array}{c}{V}_1\\ V_2\end{array}\right]=R\left[\begin{array}{cc}1& -1\\ -1& 1\end{array}\right]\left[\begin{array}{c}{I}_1\\ I_2\end{array}\right].$$

(5)

Note that if $I_2=-I_1$, the impedance seen by the current generators is exactly $2R$ (i.e., $Z_1=Z_2=2R$). This demonstrates the combiner’s ability to cancel out the effect of the parasitic $C_{OUT}$ at any chosen frequency.

However, it is important to note that the practical implementation of this combiner is subject to certain constraints. One such limitation arises when the characteristic impedance $Z_0$ reaches values that are impractically high or low, which can occur depending on the relative permittivity (${ϵ}_r$) of the substrate. Depending on ${ϵ}_r$, the resulting transmission line dimensions may become physically unmanageable, making implementation difficult. Despite this, the proposed combiner remains a highly effective solution within the practical range of $Z_0$, offering significant improvements in design flexibility and performance over existing combiners.

3. DPA Design

After understanding the capabilities of the proposed combiner, it can be applied to design a DPA using a straightforward structure. This structure is depicted in Figure 2. In this design, the main and peak amplifiers are formed by two devices combined by using the proposed combiner. If the optimal load for each transistor is $R_{opt}$, then the characteristic impedance of the impedance inverter is defined as $R_{opt}/2$, and the common load of the DPA is $R_{opt}/4$ [11]. The selected device is a $4\times 50$μm from GaN-on-SiC MMIC Wolfspeed G28v5 process with 0.15 μm gate length.

For this device, $I_{max}=0.25$ A, $V_k=3$ V, $V_{DD}=28$ V, and $C_{OUT}=76$ fF. The chosen frequency for this design is $f=32$ GHz. Thus, the characteristic impedance for both transmission lines in the combiner is

$$Z_0={\displaystyle \frac{1}{\omega C_{OUT}}}=65.3\Omega$$

(6)

where the capacitance between both lines is $2C_{OUT}=152$ fF. Additionally, with $R_{opt}=200\Omega$, the impedance inverter’s characteristic impedance is $R_{opt}/2=100\Omega$ and the common load is $R_{opt}/4=50\Omega$.

To evaluate the concept, a DPA using ideal components (transmission lines, capacitors, etc.) and drivers is simulated. Figure 3 shows the simulated drain efficiency versus output power and the load modulation effect for the main and peak devices (i.e., $Z_1$ and $Z_2$). The simulation indicates a potential bandwidth of 4 GHz for the DPA. Note that the most optimal load modulation is achieved at 32 GHz, the chosen frequency.

The input matching networks are designed to maintain circuit stability and enable broadband performance with optimized gain. The Wilkinson divider at the input is configured with an uneven division ratio to enhance load modulation effects, while the other two Wilkinson dividers are designed for an equal power split.

In the DPA version incorporating real transmission lines, a 100 $\Omega$ impedance inverter was synthesized using a four-section structure. This approach was necessary because a 100-ohm impedance results in a very narrow width in the employed technology. Consequently, an adjustment was required in the delay at the input of the main amplifier cell to ensure proper phase alignment. Additionally, bias tees were designed utilizing high impedance transmission lines, characterized by narrow lines. Circuit stability was maintained with the inclusion of a series resistor at the gate of each device, complemented by an additional resistor within the bias tee structure. The driver amplifier was designed with an input matching network similar to that of the main and peak amplifiers, and an output matching network (OMN) was implemented to match the 50-ohm impedance of the dividers at the input of the main and peak cells. The preamplifier (driver) at the peak branch has been biased at class C, while the peak cell was kept in Class AB. Figure 4 shows the schematic of the obtained DPA. The nominal value of the capacitor between lines in the combiner structure changes due to the non-ideal characteristics of real capacitors, which introduce parasitic effects that alter the effective capacitance. This variation must be accounted for in the design to ensure proper combiner performance. The DPA layout is shown in Figure 5 with a chip size of 4.6 × 3.6 mm, where the applied voltages to any stage of the circuit are indicated.

Simulation results for the 30 to 34 GHz bandwidth reveal that the amplifier achieves a Power Added Efficiency (PAE) at 6 dB Output Power Back Off (OBO) ranging between 14% and 28%, indicating a robust performance across the frequency range. At saturation, the PAE improves significantly, reaching between 24% and 37%, demonstrating the amplifier’s efficiency under peak conditions. The gain at saturation consistently exceeds 11 dB, which is crucial for maintaining signal integrity and amplification quality. The output power surpasses 36.5 dBm, equivalent to over 4.47 W, reflecting the amplifier’s capability to deliver substantial power levels for high-demand applications.

The efficiency and gain profiles as functions of output power are shown in Figure 6a and Figure 6b, respectively. These figures illustrate how the amplifier’s performance evolves with varying output power, providing insight into its operational efficiency and amplification characteristics. Figure 7 presents the results across the entire frequency range, highlighting the amplifier’s ability to maintain performance consistency over its operational bandwidth.

In addition, Figure 8 provides a detailed view of the gain and PAE profiles specifically at 32 GHz, which is the center frequency of the design. This figure also includes fundamental load modulation performance, demonstrating how well the amplifier handles load modulation and maintains efficiency. The detailed analysis confirms that the proposed design not only achieves high performance, but also provides effective load modulation, making it well-suited for practical high-frequency applications.

The performance of the newly designed mmW DPA was tested using the Keysight ADS 2024 DPD Explorer simulation tool. The simulation involved a 100 MHz 5G NR signal with a carrier frequency of 32 GHz, a Peak-to-Average Power Ratio (PAPR) of 9 dB, and an available power of 12 dBm. Results, as depicted in Figure 9, compare the power spectral density of the PA’s output with and without the application of Digital Predistortion (DPD). Incorporating DPD, using a Generalized Memory Polinomial (GPM) model with a memory depth of 3 and order 7, significantly improved the Adjacent Channel Leakage Ratio (ACLR), raising it from 28.5 dBc to 46.3 dBc. The Error Vector Magnitude (EVM) was improved from −22 dB to −44.6 dB. The average output power simulated was 27.4 dBm, and the PAE averaged 21.9%.

Overall, the simulation results validate the effectiveness of the proposed design, showing that the amplifier maintains excellent performance metrics across a wide bandwidth and operational conditions. This robustness in efficiency, gain, and power output underscores the amplifier’s suitability for advanced high-frequency applications, including those in the mmW range.

4. Conclusions

In conclusion, this work introduces a novel differential combiner that effectively compensates for transistor output capacitances at any chosen frequency, overcoming the limitations of previous designs. By incorporating a capacitor with a value of $2C_{OUT}$ into the midpoint of the $\lambda /4$ transmission line, the proposed combiner achieves precise capacitance cancellation, making it suitable for high-frequency applications with high load impedances. This innovation greatly simplifies the design process for DPAs, eliminating the need for complex parasitic compensation and making it applicable not just for millimeter-wave frequencies but for any design frequency. The DPA design leveraging this combiner demonstrates impressive performance, with simulation results showing a 6 dB OBO PAE ranging from 14% to 28%, and up to 37% at saturation, while maintaining a gain above 11 dB and output power exceeding 36.5 dBm. The comprehensive simulation results validate the effectiveness of the proposed design, showing a potential bandwidth of 4 GHz and optimal performance at 32 GHz.