A Tight Load Regulation Hysteretic Boost Converter with Compact and Energy-Efficient Anti-Phase Emulated Current Control ^†

Abstract

This paper presents a novel, compact, and energy-efficient hysteretic boost converter that employs an anti-phase AC-coupling emulated current control. The proposed scheme utilizes a two-transistor current emulator and a comparator, which allow for fast transient responses and tight closed-loop regulations. This converter was fabricated using a 180 nm CMOS process and was capable of regulating a 5 V output with a 400 mA load capacity from an input voltage range of 2.7 V to 4.5 V. The experimental results demonstrate that the proposed anti-phase AC-coupling emulated current controlling and single hysteretic comparator controlling scheme show lower power/circuit complexity and better static and transient performance. Specifically, under load transitions ranging from 0 mA to 300 mA, the converter exhibits over/undershoot voltages of 38 mV and −42 mV, respectively. Furthermore, the measured load and line regulation performances are 5 mV/A and 2.3 mV/V, respectively. Overall, this study offers a practical and efficient solution for boosting voltage levels while maintaining stable and precise regulation.

1. Introduction

In power electronic applications, boost converters are commonly used to step up the input voltage to meet specific load requirements. They are widely utilized in renewable energy systems (such as solar inverters), electric vehicle chargers, and portable electronic devices. These applications require efficient voltage conversion and stable output to ensure the proper operation and longevity of the equipment. Portable electronic devices, such as smartphones and tablet computers, rely on batteries as their primary power sources. To prolong service time, a high-performance power management integrated circuit (PMIC) is an essential component [1,2,3]. With the rapidly increasing computational demands of these devices, the regulator must exhibit several key characteristics [3,4,5,6], including the following: (1) a high conversion efficiency across a wide load range, (2) a fast transient response to large load changes, and (3) a compact chip area along with a simplified architecture to meet the requirements of handheld devices.

Ripple-based control regulators, characterized by high efficiency, fast transient response, and simple structure, are well-suited for compact and energy-efficient applications [6]. Among various control schemes, the hysteretic control scheme is particularly favored in high-performance converter designs due to its ease of implementation and inherent pulse-frequency modulation function in discontinuous conduction mode (DCM) [6,7,8]. Figure 1 illustrates the simplest structure of a voltage-mode hysteretic control for a buck converter. The control circuit utilizes only a hysteretic comparator, without requiring an error amplifier or an external clock signal generator. However, to enhance the noise margin and stabilize the system, a large capacitor with significant equivalent series resistance (ESR) is necessary, which unfortunately degrades overall efficiency.

A current-mode (CM) hysteretic control, as shown in Figure 2a, senses the inductor current ripple and combines it with V_FB to form the feedback voltage V_SEN [8,9,10]. The ESR has a minimal impact on the system’s stability, and overall efficiency is further improved by using a small ESR. Figure 2b depicts a typical implementation of the current sensor using an RC network across the inductor. The voltage across the capacitor captures the inductor current ripple and adds it to Vo. By appropriately adjusting the ratio between the parallel RC network and the inductor, a significant ripple voltage can be effectively generated. While the feedback voltage V_SEN indirectly regulates Vo, a larger inductor series resistance (DCR) can introduce static error in the output voltage and degrade the load regulation performance. The work in [10] proposes a quasi-V² hysteretic control to overcome this drawback, but it introduces an error amplifier, compromising circuit simplicity. Another approach, presented in [11], introduces a method of digital hysteretic average current control in a non-inverting buck-boost converter to improve the reference transient performance and achieve smooth mode transitions. Additionally, [12] presents a time-based dual-mode control asynchronous boost converter, enabling a lower peak current and high integration for improved efficiency.

Meanwhile, different converter topologies present distinct implementation difficulties for CM hysteretic control. As shown in Figure 3, CM hysteretic control can be easily applied in the buck converter since the inductor current i_L and the output voltage ripples are in phase [13]. However, in a typical boost converter, the output capacitor current i_C is related to the inductor current in discontinuity. As a result, the output voltage ripples can only be indirectly utilized and require a complex circuit to combine the output voltage and the anti-phase inductor current.

Figure 4 illustrates several CM techniques for dc-dc converters [14]. An RC-based dc resistance (DCR) current sensor can accurately replicate the waveform of the inductor current with the fastest sensing response when the time constant of an RC network aligns with that of the inductor (L) [15]. However, in boost converters, the sensing gain is small, and the sensing output is often out of phase with the inductor waveform due to the reversed position of the inductor compared to buck converters. Despite this limitation, a SenseFET-based current sensor allows for in-phase current sensing across various converter topologies. Alternatively, integrating a feedforward-path current sensor with an operational transconductance amplifier (OTA) can improve sensing response time by eliminating the feedback loop, thus avoiding stability issues [16,17,18]. However, the nonlinearity of the transconductance (GM) may compromise sensing accuracy when dealing with a wide range of sensing currents.

Figure 5 illustrates two variations in previously documented hysteretic controlled boost converters. In Figure 5a [19], a current-mode hysteretic inner loop is established by monitoring the inductor current, and the output is regulated by an error amplifier that governs the inner loop. This setup achieves decent regulation due to the high-gain amplifier; however, its compensation capacitor may significantly impair transient responses, and the current sensor adds to the design’s complexity and the power budget. In Figure 5b [20], a design is presented that combines the output voltage and inductor current information using three transconductance (gm) stages. In this configuration, as the anti-phase inductor current is superimposed onto the output voltage, regulation is attainable, and fast responses are achieved through zeroth-order control, which enhances transient response at the expense of additional inductor energy and circuit complexity.

From the literature review above, an area-efficient current-mode (CM) hysteretic control boost converter with superior regulation performance, fast transient response, and compact structure is preferred. In this paper, we propose a simple anti-phase AC-coupling current emulator, which effectively combines the output voltage and anti-phase inductor current in the boost converter. Additionally, we introduce a high-speed hysteresis window tunable comparator, which is adaptively adjusted using a phase-locked loop (PLL) to achieve a pseudo-fixed switching frequency over a wide range of operating conditions. This design aims to provide fast response and stable and precise regulation.

The rest of this article is organized as follows. Section 2 provides an explanation of the operational principle and circuit implementation of the proposed scheme. In Section 3, the measurement results are presented, followed by the discussion in Section 4.

Table A1. Meanings of main abbreviations.

Abbreviations	Meaning
DCR	Inductor series resistance
PLL	Phase-locked loop
CM	current-mode
PWM	Pulse width modulation
OTA	Operational transconductance amplifier
GM	Transconductance
PFD	Phase-frequency detector

and

Table A2. Meanings of main variables.

Symbol	Meaning
VIN	The input voltage of the system
VO	The output voltage of the system
IL(iL)	The inductor current
IO(iO)	The output current
VREF	Reference voltage
VFB	Output feedback voltage
CLKREF	System clock
VRAMP	The output voltage of the proposed anti-phase current emulator, which includes the information of the inductor current
VHW	Hysteretic band window
fsw	Switching frequency

in Appendix A list the meanings of the main abbreviations and variables appearing in the text.

2. Architecture and Circuit Implementation

2.1. System Architecture

The proposed boost converter system architecture is illustrated in Figure 6 and encompasses an anti-phase AC-coupling current emulator, a hysteresis window tunable comparator, a boost power stage, and a frequency regulation phase-locked loop (PLL). The portion enclosed in the green dotted box represents the suggested anti-phase AC-coupling current emulator. This emulator is composed of a simple Gm stage consisting of M1, M2, and R_Z1, which translates the voltage across the inductor into an anti-phase current. Capacitor C_Z2 integrates the anti-phase current to generate a ramp signal V_RAMP that is out of phase with the inductor current I_L. Instead of conventionally summing the output voltage V_O and the inductor current I_L, the reference V_REF is directly subtracted from the anti-phase I_L information, which then regulates the feedback V_FB using a comparator. The effective implementation of this approach reduces circuit complexity and power consumption due to the ease with which the anti-phase I_L can be obtained using the proposed current emulator. Additionally, the hysteretic window of the comparator is adaptively adjusted using a PLL, resulting in a pseudo-fixed switching frequency across a wide range of operating conditions.

Figure 7 illustrates the operating waveforms of the proposed converter. In Figure 7, V_RAMP holds an average value of V_REF and the ramp is in inverse phase to I_L. The transconductance of the Gm stage approximately equals to 1/R_Z1, so the effective reference voltage V_RAMP can be expressed as follows:

$$V_{RAMP}=\left\{\begin{array}{ll}{V}_{RAMP}\left(0\right)-{\displaystyle \frac{V_{IN}{R}_1}{R_{Z1}{C}_{Z2}(R_1+R_2)}}\cdot t& 0\le t\le D{T}_S\\ V_{RAMP}\left(D{T}_S\right)-{\displaystyle \frac{(V_{IN}-V_O)R_1}{R_{Z1}{C}_{Z2}((R_1+R_2))}}\left(t-D{T}_S\right)& D{T}_S\le t\le T_S\end{array}\right..$$

(1)

and the proportionality coefficient K is calculated as follows:

$$K={\displaystyle \frac{R_1}{\left(R_1+R_2\right)C_{Z2}{R}_{Z1}}}$$

(2)

When the high-side power switch MP turns on, I_L decreases and V_RAMP increases in the opposite direction until the feedback voltage V_FB reaches the upper hysteretic window V_H, which can be expressed as follows:

$$V_H=V_{RAMP}+{\displaystyle \raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}{V}_{HW}$$

(3)

V_HW is the hysteretic band window. On the other hand, when the low-side power switch MN turns on, I_L rises and V_RAMP falls until V_FB reaches the lower hysteretic window V_L and it can be expressed as follows:

$$V_L=V_{RAMP}-{\displaystyle \raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}{V}_{HW}$$

(4)

Consequently, the feedback voltage V_FB strictly stays within the hysteretic window V_HW, and its average voltage is tightly regulated by the reference voltage V_REF. Under normal operating conditions, the converter’s switching frequency will vary with input voltage, as expressed by the following relationship:

$$f_{SW}\approx {\displaystyle \frac{R_1{V}_{IN}(V_O-V_{IN})}{V_{HW}{V}_O(R_1+R_2)C_{Z2}{R}_{Z1}}}$$

(5)

A PLL is used to lock the converter’s switching frequency to the fixed frequency of the reference clock CLK_REF. The PLL compares the reference clock CLK_REF with the duty signal PWM, it then sends the comparison result back to adjust the window size of the hysteretic comparator. According to (5), as the input voltage increases and V_O remains constant, the comparator should increase V_HW to maintain a constant frequency.

Meanwhile, the proposed current emulator exhibits favorable regulation performance. As shown in Figure 8, a static error exists in the voltage V_GMO due to a non-zero inductor DCR. The capacitor C_Z1 effectively decouples the error from V_GM and provides the capacitively coupling AC voltage V_SEN. Thereby, the emulated voltage V_RAMP is strictly equal to reference voltage V_REF, neglecting the ripple voltage. The proposed boost converter supplies a tightly regulated output voltage V_O and achieves a superior load/line regulation performance.

Figure 9 presents the load-transient waveforms of two different control schemes, the conventional V_O-I_L summing scheme and the proposed anti-phase AC-coupling emulated current control. The figure illustrates that the ripples of V_RAMP consistently exhibit an inverse phase to that of I_L. When the load increases, V_O initially decreases, necessitating a further decrease of V_RAMP to initiate a change in the comparator output. This relationship indicates that deeper V_RAMP dips correspond to higher I_L peaks, enabling the proposed scheme to promptly respond to load changes and demonstrate enhanced performance in terms of overshoot and undershoot. In comparison to the V_O-I_L summing scheme, the proposed approach achieves both rapid responses and precise regulations. The direct summation of V_O and I_L in the conventional scheme leads to regulation errors dependent on I_L. For instance, when considering a practical inductor with a non-zero DCR, the average voltage across the inductor equals I_L multiplied by the DCR, resulting in a non-zero error in the summing result of V_O and I_L. In contrast, the proposed scheme capacitively couples V_RAMP to I_L, ensuring that the average value of V_RAMP always equals V_REF. As a result, the static error induced by DCR is eliminated, leading to significantly improved regulation performance. The proposed scheme simplifies the control system by only requiring a simple current emulator and a comparator for closed-loop regulation. This eliminates the need for additional control circuits, enabling fast responses and straightforward frequency compensations.

2.2. Stability Analyses

To stabilize the system, the small-signal modeling for the proposed hysteretic boost converter is analyzed. The work in [21] carefully establishes the large-signal model of the CM hysteretic control boost converter and analyzes its characteristics. Based on this, it derives the small-signal transfer function of the CM hysteretic control boost converter, and the function is expressed as follows:

$$V_O(s)={\displaystyle \frac{\frac{V_{IN}(s)}{1-D}+R_O(1-D)\left(1-\frac{sL}{{\left(1-D\right)}^2{R}_O}\right)I_L(s)}{2+s{R}_O{C}_O}}$$

(6)

Since the control signal tightly controls the average value of the inductor current and [21] utilizes a current-sensing circuit to replicate the inductor current, the control voltage V_C can be derived as follows:

$$V_C=I_L{R}_S$$

(7)

where R_S is the sensing resistor. Substituting (7) into (6) and neglecting the input voltage, the control-to-output transfer function is shown in (8) as follows:

$$G_{vc}={\displaystyle \frac{V_O(s)}{V_C(s)}}={\displaystyle \frac{\frac{R_O(1-D)}{R_S}\cdot \left(1-\frac{sL}{{\left(1-D\right)}^2{R}_O}\right)}{2+s{R}_O{C}_O}}$$

(8)

For the proposed boost converter, the inductor current is achieved through the anti-phase AC-coupling current emulator and works the same as the typical CM hysteretic control. Figure 10 simplifies the block diagram of the proposed hysteretic boost converter. Rg is the output resistor of the Gm stage. The Gm stage, C_Z1, and C_Z2 help obtain the inductor current information. The relationship between I_L and V_C is derived as follows:

$$V_C=I_L·{\displaystyle \frac{s^2\cdot C_{Z1}{R}_{\mathrm{g}}{R}_{Z2}L{R}_1{G}_m}{s^2\cdot C_{Z1}{C}_{Z2}{R}_{\mathrm{g}}{R}_{Z2}+s\cdot \left(C_{Z1}{R}_{\mathrm{g}}+C_{Z2}{R}_{Z2}+C_{Z1}{R}_{Z2}\right)+1}}·{\displaystyle \frac{1}{\left(R_1+R_2\right)}}$$

(9)

Substituting (9) into (6), the control-to-output transfer function for the proposed hysteretic boost converter is given by the following:

$$G_{vc}={\displaystyle \frac{V_O}{V_C}}=\left({\displaystyle \frac{R_1+R_2}{1-D}}\right)·{\displaystyle \frac{\left[R_O{\left(1-D\right)}^2-sL\right]}{2+s{C}_O{R}_O}}·{\displaystyle \frac{s^2\cdot C_{Z1}{C}_{Z2}{R}_g{R}_{Z2}+s\cdot \left(C_{Z1}{R}_g+C_{Z2}{R}_{Z2}+C_{Z1}{R}_{Z2}\right)+1}{s^2\cdot C_{Z1}{R}_g{R}_{Z2}L{R}_1{G}_m}}$$

(10)

Equation (10) reveals that the system is characterized by a right-half-plane zero along with two left-half-plane poles. The bode plot depicted in Figure 11 showcases the control-to-output transfer function of the proposed hysteretic control through both analytical derivation and simulation using SIMPLIS. The simulated waveforms of the gain and phase exhibit close alignment with the analytical model at medium to high frequencies. However, discrepancies emerge at lower frequencies due to limitations within the SIMPLIS simulation tool, particularly affecting the accuracy of phase simulation. Despite this, the inaccuracies in low-frequency phase simulation do not detrimentally impact the loop analysis of the converter.

The introduction of AC-coupling capacitors C_Z1 and C_Z2 causes the system’s phase to initially dip below zero, with further exacerbation from the existence of the right-half-plane zero. As the frequency surpasses about 2 kHz, the phase trajectory begins to ascend due to the presence of two left-half-plane zeros. To ensure system stability, compensatory measures must be taken by introducing an additional left-half-plane zero to enhance the phase margin. Consequently, a small capacitor C_f is incorporated in parallel with feedback resistor R_f2 to introduce this desired left-half-plane zero, as illustrated in Figure 10.

The Bode Diagrams presented in Figure 11 and Figure 12 demonstrate the closed-loop response of the proposed hysteretic control under heavy loads. The phase margin proves slightly insufficient, rendering the system more prone to oscillations during heavy load transients.

2.3. Circuit Implementation

In this particular design, a frequency regulation PLL is utilized to synchronize the switching frequency with the desired CLK_ref across a broad operating range. The PLL comprises a phase-frequency detector (PFD), an up-down counter, and a tunable comparator with a hysteretic window. The circuit implementation of the frequency regulation loop is depicted in Figure 13a, while Figure 13b illustrates the simulated waveforms. When the PWM switching frequency exceeds the reference frequency CLK_ref, the PFD generates a “DN” signal to the up–down counter, prompting a decrease in the control word HYS [4:0]. Consequently, the reduced HYS [4:0] value widens the hysteretic window, causing the switching frequency to decrease until it aligns with the desired CLK_ref. Conversely, if the PWM switching frequency falls below the reference frequency CLK_ref, the PFD issues an “UP” signal to the up–down counter, resulting in an increase in the control word HYS [4:0]. This adjustment in HYS [4:0] mandates a narrower hysteretic window, causing the switching frequency to increase, almost reaching CLK_ref.

The proposed high-speed hysteretic window tunable comparator [22,23] is illustrated in Figure 14. In the cases where the V_O switching ripples exhibit an inverse relationship to the I_L, a narrow hysteretic window is desired for the fixed frequency operation across a wide operating range, particularly when handling heavy loads. To address this requirement, the designed comparator incorporates a hysteretic window ranging from 3 mV to 20 mV while ensuring fast response even at the 3 mV hysteretic window. The comparator configuration consists of a power-efficient nested-current-mirror pre-amplifier, a 5-bit hysteretic tunable latch, and a self-biased differential amplifier. For maintaining swift comparison within the 3 mV hysteretic window, the adoption of a high-speed high-gain pre-amplifier becomes essential. In this context, a nested-current-mirror pre-amplifier is employed to achieve reasonable gain with low power consumption. As depicted within the dashed box, three cascaded current mirrors (M4-M9) establish a current amplification of 3 × 4 × 6 = 72 times for path 1. However, it is important to note that the current consumptions of these current mirrors are summed rather than multiplied, resulting in a significant enhancement in current efficiency. The design strategy involves selecting the mirroring ratio of M4–M5 to strike a balance between gain, offset, and speed, whereas that of M6-M7 is chosen to improve overall gain, and that of M8-M9 is determined to enhance the slew rate. As a result, this design achieves approximately 12.4 times greater efficiency compared to traditional differential amplifiers. Following the pre-amplifier, a hysteretic tunable latch is incorporated. The presence of a positive feedback loop accelerates the comparison operation, and the digitally controlled resistor R_HYS generates the desired hysteretic window. In this case, R_HYS is designed to provide a 5-bit uniformly spaced hysteretic window with a step size of 0.5 mV. Finally, a high-speed self-biased differential amplifier amplifies the output of the latch and delivers the final comparison result.

The comparator’s high-speed and high-gain characteristics, along with the precise hysteretic steps, contribute to its ability to facilitate accurate converter switching operations and tightly regulate switching frequencies. It is worth noting that the 0.5 mV hysteretic step ensures that the converter switching frequency remains within ±0.2% of the target reference frequency, as will be demonstrated.

3. Measure Results

Using a 180 nm CMOS process, we successfully implemented and validated the proposed hysteretic boost converter. The layout and die photograph of the prototype, occupying an approximate chip area of 1.24 mm², are presented in Figure 15.

The prototype is designed to operate within an input voltage range of 2.7 V to 4.5 V, providing a stable output at 5 V with a load current capacity of up to 400 mA. Load-transient responses were evaluated by varying the load from 0 mA to 300 mA at a 3.3 V input, as illustrated in Figure 16. Observing the figure, the output voltage (V_O) exhibits undershoot and overshoot values of −42 mV and 38 mV, respectively, with corresponding settling times of 124 μs and 104 μs at 0.1%. Further examination of the magnified sections below reveals that despite load current fluctuations of approximately 500 mA, the output voltage regulation errors remain insignificant. The impact of inductor DC resistance (DCR) on load-dependent regulation errors is effectively mitigated, and the waveforms of the load current indicate minimal peaking, demonstrating robust stability margins and well-optimized loop parameters.

Figure 17 presents the line-transient responses measured under a load current of 300 mA. The observed V_O under/overshoot voltages of −14 mV and 10 mV occur as the supply fluctuates between 3 V and 3.6 V. Additionally, Figure 18a illustrates the measured load and line regulation performances. Specifically, the converter demonstrates a load regulation of 5 mV/A at an input of 3.3 V and a line regulation of 2.3 mV/V with a load current of 300 mA. Furthermore, Figure 18b provides a comprehensive overview of the converter’s efficiency and switching frequency across the entire load range. Notably, the converter achieves a peak efficiency of 95.3% while tightly maintaining the switching frequency within ±0.2% of 600 kHz throughout the load range.

4. Discussion

This paper introduces an energy-efficient hysteretic boost converter that incorporates the proposed anti-phase AC-coupling emulated current control and a hysteretic comparator control. The converter utilizes a two-transistor current emulator and a hysteretic comparator to achieve rapid transient responses and precise closed-loop regulations. By adopting this simple scheme, the need for additional control circuits is eliminated, resulting in reduced power consumption and simplified frequency compensation. Additionally, the proposed high-speed high-gain hysteretic tunable comparator allows for a consistent switching frequency of 600 kHz across the entire load range. Experimental results obtained from the prototype, which operates at a quiescent current of 50 μA, demonstrate undershoot and overshoot voltages of −42 mV and 38 mV, respectively, during load transitions ranging from 0 mA to 300 mA. Furthermore, the measured load regulation performance is 5 mV/A, while the line regulation performance stands at 2.3 mV/V.

The performance summary presented in

Table 1. Comparison of state-of-the-art boost converters.

	[12] TIE2020	[18] JSSC2021	[14] TPE2022	[6] TCASI2023	This
Process	0.13 µm	0.18 µm	0.18 µm	0.18 µm	0.18 µm
Chip area (mm2)	1.7	1.67	1.46	6.24	1.24
Frequency (Hz)	1.5 M	10 M	15 M~25 M	2 M	600 ± 0.2% k
Input Voltage (V)	2.5~5.5	1.8–3.2 V	1.8~2.4	2.5–4.4	2.7~4.5
Output (V) Voltage (V)	12	3–4.2 V	3.3	5	5
Load (mA) Current (mA)	0~600	5–800	100~500	10–1000	400
Peak (%) Efficiency (%)	91	94.5	91.5	95.2	95.3
Load Regulation (mV/mA)	NA	0.022	NA	0.032	0.005
Line Regulation (mV/V)	NA	−125/135	−105/115 (100–500 mA)	−41/56	−42/38 (0–300 mA)

compares the outcomes of the proposed work with those of the prior state-of-the-art boost converters. We can see that our chip has a much smaller area compared to the other models while achieving the highest peak efficiency, the lowest load regulation, and relatively lower line regulation. However, the switching frequency is only 600 kHz, much lower than the other models, and its load current range is also smaller. Therefore, further optimization and improvement are needed in applications requiring high frequency and a large load current.

The current control scheme based on anti-phase AC coupling and the single-lag comparator control method proposed in this study not only achieves innovation in the control algorithm but also demonstrates superior performance through experimental validation in practical applications. This scheme successfully reduces power loss and chip area, simplifies circuit design, and provides high-precision, fast-response voltage regulation. These characteristics make the BOOST converter highly suitable for various applications that require an efficient and stable power supply. For instance, in the battery management system of electric vehicles, the proposed BOOST converter control scheme can effectively enhance energy conversion efficiency, reduce power losses, and thus extend the battery’s lifespan. Furthermore, renewable energy systems, such as photovoltaic power generation systems, can leverage this control scheme to optimize the power conversion process, improving the overall energy utilization of the system. Additionally, the scheme is applicable to various portable devices, where it can provide stable and reliable power support in cases requiring precise and rapid voltage regulation.

By integrating this control method into practical applications, the system’s performance can be significantly enhanced while overall costs are reduced. Based on this scheme, there is potential for its application in a broader range of scenarios in the future, such as applications with higher input voltage ranges, higher switching frequency, or adaptive improvements under varying load conditions. Given its low power consumption and high performance, this approach can offer a new technological pathway for efficient power supply design, with practical benefits across various fields.