A Wideband dB-Linear Analog Baseband for a Millimeter-Wave Receiver with Error Compensation in 40 nm CMOS Technology

Abstract

This paper presents a low power wideband dB-linear analog baseband (ABB) circuit for a millimeter-wave (mmW) wireless receiver in 40 nm CMOS technology. The proposed ABB system consists of a multi-stage variable gain amplifier (VGA) and a low-pass filter (LPF). The 5-stage VGA is composed of two variable gain units followed by three fixed gain units with DC offset cancellation (DCOC). The first variable gain unit with a self-compensated transistor pair and compact active inductor load is designed for dB-linear functionality and bandwidth extension, respectively. Moreover, a proposed error compensation method is applied to the second cascaded variable gain unit for further dB-linear gain error correction. A 4th-order Butterworth transconductance-capacitance (Gm-C) LPF with flipped source follower (FSF) as an input transconductance stage for linearity enhancement is designed after the VGA stage. The prototype chip is implemented, and measurement results show a dB-linear gain range from −18 to 26 dB with less than 0.5 dB-linear gain error with a bandwidth of 4 GHz. The VGA and LPF consume 8.3 mW and 3 mW, respectively, under a 1 V power supply, while the entire ABB occupies an area of 0.94 mm² with an active core area of only 0.045 mm².

1. Introduction

Fifth-generation (5G) wireless communication operating in the millimeter-wave (mmW) band is highly sought after since it can provide a wider bandwidth and support significantly higher data rates [1,2]. The analog baseband (ABB), one of the primary gain stages in the receiver system, as shown in Figure 1, consists of a variable gain amplifier (VGA) and a low-pass filter (LPF) [3]. To achieve the desired dynamic range of receiver, both the RF front end and the ABB stage need to have a wide and fine gain tuning capability. The RF front end usually provides coarse gain tuning only, whereas a fine gain tuning capability with a sufficiently wide gain tuning range for the demands of high transmission data is achieved by a VGA with a wide bandwidth rates [4,5,6,7]. The ABB has both a high and low gain mode, where the output signal saturation can be reached in high gain mode without any gain monitor as presented in most of the published literature [5,6,7,8]. An automatic gain control (AGC) with fast and accurate tuning is essential to regulate the gain and prevent the output signal from saturating the followed analog-to-digital converter (ADC) stage. The VGA with linear-in dB adjustment is desired to satisfy such a requirement [8,9,10,11]. Moreover, a LPF after the VGA is generally required to provide filtering functions to reduce output noise before connecting the ADC stage [12]. The design specifications for the ABB system are shown in

Table 1. Design specifications for the ABB system.

CMOS technology	40 nm CMOS
Characteristic	dB-linear, wideband
Gain range (dB)	≥40 dB
Bandwidth (GHz)	≥2 GHz
dB-linear gain error (dB)	≤±1 dB
Out of band rejection (dB)	>20 dB (at twice the bandwidth)

.

Several CMOS ABB systems have been presented in [13,14,15]. The ABB system in [13] uses a combination of a trans-impedance amplifier (TIA), a LPF, and a programmable gain amplifier (PGA) to provide a gain range of 20 dB and a bandwidth of 915 MHz, at a power under 9.5 mW DC. The design in [14] features a four-stage topology comprising a G_m-cell-based coarse gain step tuning amplifier, a current-mode type II Chebyshev filter, a current-mode fine gain step tuning amplifier, and a TIA. This circuit achieves a gain adjustable range of 3–31 dB with 1 GHz of bandwidth but consumes 32 mW. In [15], the ABB is implemented by two second-order LPF stages and one first-order LPF stage, offering a gain range of 0–40 dB with a 1 GHz bandwidth and an 18 mW power consumption. It is worth noting that these ABB systems achieve a large gain tuning range and filtering function, but with limited bandwidth of less than 1 GHz, and a lack of a dB-linear characteristics, which would constrain their applications for high-rate mmW communications receivers. Thus, a VGA with wideband and dB-linear characteristics is one of the key factors for mmW receiver systems. However, the bandwidth of conventional amplifiers is constrained by the parasitic capacitance at the output nodes. Therefore, various bandwidth extension techniques have been published to achieve a wide bandwidth, including the inductive peaking technique, gate-peaking technique, RC-degeneration technique, active feedback technique, and modified Cherry–Hooper topology [6,7,8,9,16,17,18,19].

Generally, dB-linear VGA circuit topologies are classified into two categories [16]. Figure 2 shows four existing dB-linear VGA topologies. The closed-loop VGA architecture employing discrete digital control known as PGA [20] is shown in Figure 2a, while the analog controlled VGA is illustrated in Figure 2b–d. PGAs typically provide dB-linear gain control through large resistor and switch arrays to achieve a wide dynamic range, low dB-linear gain error, and precise gain steps at the cost of a large die area. Additionally, PGAs with closed-loop architecture have limited bandwidth and the issue of instability [20,21,22,23,24].

Therefore, the analog controlled dB-linear VGA is preferred due to its accurate continuous gain tuning, small die area and high frequency operation capability [16,17,18,19]. Figure 2b illustrates an area-efficient inductorless VGA based on current-steering architecture [17]. A stagger-tuned switching architecture was presented for CMOS exponential function generation with a current ratio generator to realize the approximation function in the current domain. This design achieves a 40 dB gain tuning range with less than ± 1 dB gain error and 5 GHz bandwidth. Figure 2c presents a Gilbert-cell-based VGA, which utilizes the shifting of concave and convex functions derived from an original negative pseudo-exponential generator to generate two additional exponentially related control signals [18]. It achieves a performance of a 51 dB gain range, a gain error within ± 1 dB, and a bandwidth of 7 GHz. Although these VGAs achieve wideband dB-linear performance, they rely on additional exponential generation circuits to realize the dB-linear behavior. Such circuits are typically implemented using two approaches: one relies on the exponential relationship inherently produced by bipolar junction transistors (BJT) or threshold transistors to implement the control circuitry [25,26,27], and the other employs exponential approximate methods using the square-law behavior of transistors to implement a pseudo-exponential function based on the Taylor series, etc. [28,29,30]. Although these exponential generators can achieve a well-performing dB-linear VGA, the additional exponential generation circuits not only increase the complexity of the design but also lead to a higher power consumption, a larger area, and increased noise.

Figure 2d shows a dB-linear VGA by utilizing the exponential I-V relationship based on MOS transistors operating in the subthreshold region [19]. This technique simplifies circuit complexity without an additional exponential generator at the cost of a narrow tuning range of the transistor in the subthreshold region, which limits the achievable dB-linear gain range.

In this paper, a low power ABB prototype design for mmW wireless communication is presented, where analog controlled dB-linear VGAs based on a self-compensated transistor, an active inductor, and a folding Gilbert structure are proposed. Without any additional exponential generator circuits, the proposed ABB design achieves a wide bandwidth, low power consumption, and dB-linear characteristics with a compact area. An error compensation method is also presented to reduce the dB-linear gain error and further improve the dB-linear accuracy. A 4th-order Butterworth LPF for out-of-band (OOB) rejection and the neutralization capacitor technique for stability boosting are designed, respectively.

The remainder of this paper is organized as follows. Section 2 presents the architecture of the proposed ABB system and detailed circuit design details are presented in Section 3. Section 4 shows the measurement results of the proposed ABB with a performance comparison. Finally, the paper is concluded with a summary in Section 5.

2. Analog Baseband Architecture

Figure 3 illustrates the complete structure of the proposed fully differential wideband dB-linear ABB system, which consists of two variable gain units, a 3-stage fixed gain amplifier (FGA) unit, a 4th-order Butterworth LPF, a DC offset cancellation (DCOC) network, and an output buffer for testing purposes only. The two distinct variable gain units are proposed to achieve wideband and precise dB-linear performance followed by a 3-stage FGA unit for sufficient voltage gain with a DCOC network for the DC offset correction after FGA stage 1. Finally, the filter used the transconductance-capacitance (G_m-C) structure to achieve wideband characteristics, and a 4th-order low-pass Butterworth transfer function is implemented through two cascaded biquadratic cells. For stand-alone RF testing purposes, a 100 Ω resistor is placed across the ABB differential inputs to achieve input impedance matching. Similarly, the output impedance of the output buffer stage is matched to a 100 Ω differential. The output buffer shown in Figure 3 used a simple resistance-loaded common source structure to match the output impedance to a 100 Ω differential.

In general, the overall noise performance of the receiver is primarily determined by the first stage, while the linearity of the system depends on the subsequent stages. Therefore, linearity is the main concern for the ABB design since it is placed at the last stage of the receiver system. The first variable gain unit has low gain due to its wideband and dB-linear characteristics, which result in high linearity. For this reason, unit 1 is positioned at the front end to attenuate the input signal. In contrast, the FGA stage exhibits poor linearity because of its higher gain, so it is placed behind the variable gain unit. A filter is placed at the final stage to minimize noise before the signal reaches the ADC input.

3. Detailed Circuit Designs of the Analog Baseband

3.1. dB-Linear Variable Gain Unit Core

Figure 4 shows the schematic of core unit 1, which employs a fully differential pair with self-compensated transistors and an active inductor load [31]. The active inductor, realized by a diode-connected transistor with the gate connected to a series resistor, serves as a load to resonate out the output capacitor to extend the bandwidth. Compared to a traditional passive inductor load, the active inductor occupies a compact area without additional power consumption. Figure 4 also shows the inductive output provided by a source follower and its equivalent network. Taking the gate-source parasitic capacitance into consideration, the output impedance seen from the source node of M_L can be expressed as [32]:

$$Z_{out}=R_S{C}_{GS}s+1/(g_m+C_{GS}s)$$

(1)

$$Z_{out}-{\displaystyle \frac{1}{g_m}}=C_{GS}s(R_S-{\displaystyle \frac{1}{g_m}})/(g_m+C_{GS}s)$$

(2)

The output impedance is approximately equal to 1/g_m, with C_GS acting as an open circuit and M_L acting as a diode-connected transistor at low frequency. At high frequency, the output impedance is approximately equal to R_S. Then, an inductive behavior can be realized. The output impedance can be modeled as a lossy inductor in series with a resistor, and inductance can be obtained by derivation as

$$L={\displaystyle \frac{C_{gs}}{g_m}}\left(R_S-{\displaystyle \frac{1}{g_m}}\right)$$

(3)

If R_S >> 1/g_m, the inductance of the active inductor can be given by:

$$L=R_S{C}_{gs}/g_m$$

(4)

Therefore, the value of the inductor can be adjusted by adjusting the value of the resistor and the size of the MOS transistor.

In this design, the differential input pair transistors of M_1,2 operate in the triode region instead of saturation, while the tail current source transistor M₅ operates in the saturation region, maintaining a constant current flow, which results in a fixed V_GS value of transistor M_3,4. To maintain a constant current value, the source voltage of M_1,2 is adjusted corresponding to the gate voltage of M_1,2. Thus, the drain current for the MOS transistor working in the triode region can be given by

$$I_D=K\left[(V_{GS}-V_{TH}\right)V_{DS}-{\displaystyle \frac{1}{2}}{V}_{DS}^2]$$

(5)

where $K=\mu C_{ox}W/L$. Thus, $V_S$ can be expressed:

$$V_S=\left(V_G-V_{TH}\right)\pm \sqrt{{\left(V_G-V_D-V_{TH}\right)}^2+{\displaystyle \frac{2I_D}{K}}}$$

(6)

As the overdrive voltage $V_{ov}=(V_G-V_D-V_{TH})>0$, only the one with the minus sign is applicable, obtaining

$$V_{DS}=-\left(V_G-V_D-V_{TH}\right)+\sqrt{{\left(V_G-V_D-V_{TH}\right)}^2+{\displaystyle \frac{2I_D}{K}}}$$

(7)

the transconductances of M_1,2 can be expressed as follows:

$$g_{m1,2}=\partial I_D/\partial V_{GS}=K{V}_{DS}=K\left[-\left(V_G-V_D-V_{TH}\right)+\sqrt{{\left(V_G-V_D-V_{TH}\right)}^2+{\displaystyle \frac{2I_D}{K}}}\right]$$

(8)

Thus, it can be simplified in the form of

$$g_{m1,2}=A\left(-x+\sqrt{x^2+1}\right)$$

(9)

where $A=K/\sqrt{2I_D/K}$ and $x=\left(V_G-V_D-V_{TH}\right)/\sqrt{2I_D/K}$. According to the Taylor expansion $\sqrt{x^2+1}\approx 1+x^2/2$, the expression for g_m can be written as:

$$g_m\approx A{e}^{-x}=A{e}^{-V_G/\sqrt{2I_D/K}}\times e^{\left(V_D+V_{TH}\right)/\sqrt{2I_D/K}}$$

(10)

It is evident that A, K, and V_D are constant values. Consequently, this equation can be succinctly expressed as follows:

$$g_m\approx C_1{e}^{-V_G/\sqrt{2I_D/K}}$$

(11)

Given that $C_1=K\prime e^{\left(V_D+V_{TH}\right)/\sqrt{2I_D/K}}$, the relationship between the gate voltage of the input transistor and its transconductance in dB-linear scale can be obtained. However, because some higher order terms are ignored in the equivalence process, the pseudo-exponential relationship between g_m and V_G still admits error compared with the ideal exponential function [33]. Meanwhile, output resistance is also a key factor for the dB-linear characteristics. When the differential pair transistors are operating in the triode region, their output resistance can be expressed by the following equation:

$$r_{ds1}={\displaystyle \frac{\partial V_{DS1}}{\partial I_D}}={\displaystyle \frac{1}{g_{ds1}}}={\displaystyle \frac{1}{\left[K\left(V_{GS}-V_{TH}-V_{DS}\right)\right]}}={\displaystyle \frac{1}{x\sqrt{2I_{D}K}}}$$

(12)

Since the load of unit 1 can be simplified as a diode-connected transistor. Consequently, the output resistance of unit 1 can be given by:

$$R_{\mathrm{out}}={\displaystyle \frac{1}{g_{ds1}+g_{m3}}}={\displaystyle \frac{1}{\left(\sqrt{K_3/K_1}+x\right)\sqrt{2I_D{K}_1}}}={\displaystyle \frac{1}{K_1\left(V_{CTRL}+C_2\right)}}$$

(13)

where $C_2=\sqrt{2I_D{K}_3}/K_1-\left(V_D+V_{TH}\right)$. From (13), it can be derived that there is an inverse proportion between the gate voltage of the input transistor and the output resistance of unit 1. This inverse relationship is only approximately equivalent to the exponential relationship in a very narrow range, so output resistance will also cause dB-linear gain errors. In [34], the dB-linear gain error caused by the output resistance is reduced through adjusting the value of K₃/K₁. However, this method still presents significant dB-linear gain errors, especially cascading two identical unit 1s.

To address this issue, this paper presents an error compensation method to achieve lower dB-linear gain error. The schematic of core unit 2 is illustrated in Figure 5 as an improved folding Gilbert unit. In response to the inverse proportionality between the output resistance and control voltage of unit 1, the Gilbert unit with a linear relationship between control voltage and gain is selected to mitigate this inverse proportionality. Moreover, an additional tail current transistor M₁₁ is incorporated into the traditional folding Gilbert structure. This integration introduces a constant term into the over gain expression, contributing to an improved error compensation for dB-linear gain. The over gain expression of the improved folding Gilbert unit can be expressed as follows:

$$A_v=G_m{R}_L=C_3\left(V_{CTRL}-C_4\right)$$

(14)

where $C_3=R_{1,2}\sqrt{K_{1,3}{K}_{9,10}/2}\sqrt{{(W/L)}_{5,6}/{(W/L)}_{7,8}}$ and $C_4=\sqrt{{(W/L)}_{11}/{(W/L)}_8}\left(V_{VDD}-V_{Bias}-V_{TH6}\right)+V_{Bias}$. Based on Equations (11), (13) and (14), the gain expression of cascade of unit 1 and unit 2 (Node B in Figure 3) can be expressed as follows:

$$A_{total}\approx {\displaystyle \frac{C_1{e}^{–V_G/\sqrt{2I_D/K}}}{K_1\left(V_{CTRL}+C_2\right)}}\times C_3\left(V_{CTRL}-C_4\right)$$

(15)

where $V_G=V_{CTRL}$. By adjusting the size of transistor M₁₁ in unit 2 to keep C₂ = −C₄, the gain expression can be expressed as follows:

$$A_{total}\approx {\displaystyle \frac{C_1{C}_3{e}^{–V_{CTRL}/\sqrt{2I_D/K}}}{K_1}}$$

(16)

As can be seen from (16), C₁, C₃, I_D, and K are constant terms, so the VGA control voltage V_CTRL and the overall gain $A_{total}$ present a dB-linear relationship with error compensation.

From (10), the dB-linear error stemming from the output impedance of unit 1 can be compensated, and the overall gain exhibits a dB-linear relationship with the control voltage. To optimize error compensation in the proposed design, the gain characteristics of unit 1 (Node A in Figure 3) remain constant. Subsequently, the gain characteristics of unit 2 and cascaded unit 1 and 2 (VGA_cascade, Node B in Figure 3) are simulated with different widths of M₁₁. The simulation results of the gain characteristics shown in Figure 6a and the gain error results shown in Figure 6b, indicate that the optimal error compensation effect can be achieved when the width of M₁₁ is set to 31.5 μm. Then the gain range of unit 1 is about –18~4 dB, and the gain range of optimized unit 2 is about –19~4 dB. The gain range of the VGA_cascade is about –38~7 dB after compensation and the dB-linear error of the optimized VGA_cascade is only ±0.3 dB.

In order to verify the effectiveness of the proposed error compensation method, the gain range and the gain error were simulated with and without the error compensation method (without error compensation is a cascade of two unit 1 stages). Figure 7a shows the simulated gain curve and the ideal gain curve with and without the proposed error compensation method, and a more obvious dB-linear relationship can be seen in the gain curve with the compensation method. Figure 7b shows the dB-linear gain error with and without the proposed error compensation method. The simulation result without the error compensation method shows that the dB-linear gain error reaches ±1.8 dB, while the dB-linear gain with the error compensation method is reduced to ±0.3 dB—an improvement of more than 80%. In comparison, even the optimized two-stage unit 1 cascade in [34] results in a dB-linear gain error of ±1 dB. These results demonstrate that the proposed error compensation method effectively minimizes the dB-linear gain error within a gain range of 45 dB.

The gain control mechanism of the dB-linear system can be severely hampered by circuit mismatches and PVT variations. In order to verify the robustness of the proposed dB-linear VGA, PVT and Monte Carlo simulations are performed. Figure 8 shows the dB-linear gain error at different process corners (TT, FF, SS, SF, and FS), at temperatures of (–40 °C, 27 °C, and 125 °C), and at power supply voltages under ±10% fluctuation: 0.9 V, 1 V, and 1.1 V, respectively. It can be observed that the dB-linear gain error exhibits small variation, maintaining itself within ±1 dB with the variations of temperatures or process corners. In addition, the dB-linear gain error is still within the ±1.5 dB range even under extreme conditions where both process corners, temperatures, and power supply voltages vary simultaneously.

To further verify the effects of process corners and mismatches, Monte Carlo simulations were performed. A total of 100 random simulations were performed at a normal power supply voltage (1 V) and temperature (27 °C) and the same bias voltage environment as before. Figure 9a shows the dB-linear gain error curve obtained by 100 random simulations. It can be seen that the most of dB-linear gain error is within ±1 dB, and the maximum dB-linear gain error is ±1.4 dB. Figure 9b shows the normal distribution statistics of the maximum dB-linear gain error obtained by 100 simulations. It can be seen that 72% of the time the maximum dB-linear gain error is less than ±0.5 dB, and 92% of the time the maximum dB-linear gain error is less than ±1 dB with an average maximum gain error of 0.392 dB and a standard deviation of 0.306 dB.

3.2. Fixed Gain Amplifier

As depicted in Figure 6, the gain of VGA_cascade primarily exhibits negative characteristics owing to its wideband and dB-linear characteristics. Therefore, cascading several FGA units is necessary to achieve enough gain. If each FGA unit is identical and has a bandwidth of BW_c, the overall bandwidth of n cascaded stages BW_tot is [35]:

$$B{W}_{tot}=B{W}_c\sqrt[m]{2^{1/n}-1}$$

(17)

where m is equal to 2 for 1st-order stages. The gain of each FGA stage is defined as A_c in dB and A_tot is for the total gain. Then, the required gain-bandwidth product GBW_c (dB·GHz) of each FGA stage can be written as:

$$GB{W}_c={\displaystyle \frac{GB{W}_{tot}}{n\times \sqrt[m]{2^{1/n}-1}}}$$

(18)

If A_tot = 30 dB and BW_tot = 4 GHz represent the design requirements for a cascade of n first-order gain stages, the A_c, BW_c, and GBW_c are as shown in

Table 2. Required stage A_c, BW_c, and GBW_c as a function of n.

n	1	2	3	4	5	6
Ac (dB)	30	15	10	7.5	6	5
BWc (GHz)	4	6.2	7.8	9.2	10.4	11.4
GBWc (dB·GHz)	120	93	78	69	62.4	57

.

It can be seen that higher the cascaded stages, the fewer the gain bandwidth product requirements. Therefore, taking the trade-off between the gain and accumulation of noise into account, three stages are selected as the optimum FGA stage to achieve the desired overall gain and bandwidth. Figure 10a depicts the topology of the FGA stage where the fully differential pair with the PMOS current source as the active load is employed. Additionally, a common mode feedback (CMFB) circuit is integrated to ensure the stability of the output DC point. The schematic diagram of the CMFB circuit is shown in Figure 10b, and it adopts a two-stage operational amplifier with folded cascade structure.

The three-stage FGA uses the same design and fixes the output common-mode voltage at 0.7 V via the CMFB circuit. The frequency response of the FGA is shown in Figure 11, and it can be seen that each stage of FGA can provide a gain of 11.7 dB with a 13 GHz bandwidth.

3.3. Low-Pass Filter

To enhance OOB noise rejection in mmW communication systems, the ABB system utilized a 4th-order Butterworth LPF. The filter is composed by the cascade of two biquadratic cells [36]. The cascade alternates NMOS and PMOS type inputs, restoring the input/output common mode voltage. The first cell utilizes a NMOS, achieving a lower quality factor (Q = 0.504). This configuration provides sharp filtering of the input signal, effectively attenuating high-frequency components at the input of the second cell, which exhibits a higher quality factor (Q = 1.307). As a result, this design enhances in-band linearity, albeit at the expense of a slight increase in in-band integrated noise. The topology of the 1st NMOS biquadratic cell and 2nd PMOS biquadratic cell are depicted in Figure 12.

The biquadratic cell utilizes a pseudo-differential structure and the flipped source follower (FSF) structure as the transconductance stage to enhance linearity. FSF incorporates local negative feedback based on the traditional source follower, thus endowing it with higher linearity. The output resistance of the FSF structure can be written as:

$$Z_{out}={\displaystyle \frac{r_{o2}}{g_{m1}{g}_{m2}{r}_{o1}{r}_{o2}+g_{m2}{r}_{o2}+1}}\approx {\displaystyle \frac{1}{g_{m1}{g}_{m2}{r}_{o1}}}$$

(19)

Compared to the output resistance of a source follower, the output resistance of the FSF is reduced, resulting in stronger load-driving. The transfer function of the FSF cell can be written as [37]:

$$T\left(s\right)\cong {\displaystyle \frac{1}{s^2\frac{C_1{C}_2}{g_{m1}{g}_{m2}}+s\frac{C_1}{g_{m1}}+1}}$$

(20)

The frequency characteristic and quality factor of the filter are written as:

$${\omega }_n\cong \sqrt{g_{m1}{g}_{m2}/C_1{C}_2}$$

(21)

$$Q\cong \sqrt{g_{m1}{C}_2/g_{m2}{C}_1}$$

(22)

Based on the required cutoff frequency and Q value, design-related parameters can be calculated. The frequency response of the LPF is shown in Figure 13, indicating that the loss of LPF is only –3.5 dB, and its bandwidth reaches 5 GHz.

When the operating frequency reaches several GHz, the Cgs of the input transistor would affect the stability of the system. Therefore, the neutralization capacitor technique is employed to enhance the stability of the filter. Figure 14 compares the Z₁₁ and K_f with and without MOS neutralization capacitors, where it can be seen that the Z₁₁ and K_f of the filter become more stable with MOS neutralization capacitors.

3.4. DCOC Network

Due to variations in the output DC operating point of the VGA unit caused by gain adjustments, the AC coupling is employed to establish the correct DC operating point, as illustrated in Figure 3. The output DC voltage of unit 1 varies between 70 mV and 140 mV, and the output DC voltage of unit 2 varies between 640 mV and 945 mV. In the FGA stage, the output common mode point aligns with the input common mode point, allowing for direct cascading. To mitigate the effects of DC offset, a DCOC network is implemented. This DCOC network not only eliminates DC offset but also provides active negative feedback, thereby extending the bandwidth simultaneously [38]. By adjusting the voltage of V_{FB_bias} as shown in Figure 3, the intensity of the active feedback can be regulated to achieve a balance between the bandwidth and gain flatness. The influence of different feedback intensities on the frequency response is shown in Figure 15. As V_{FB_bias} increases from 450 mV to 550 mV, the gain gradually decreases, while the bandwidth gradually increases, resulting in the emergence of a gain peak. Therefore, 500 mV is chosen as the value of V_{FB_bias} by trade off the gain and bandwidth.

4. Results and Discussion

The proposed ABB prototype was fabricated in 40 nm CMOS technology and tested by wafer probing. Figure 16a shows the chip microphotograph, and the measurement setup is shown in Figure 16b. The ABB system occupies an active area of only 0.045 mm², while the area of VGA is confined to just 0.027 mm².

The input and output of the chip are connected to the Keysight network analyzer (N5247B) through the differential probes, and the DC pad is connected to the PCB through wire bonding. The power supply voltage and bias voltage are provided through the DC power supply. All measurements results were performed at room temperature. The measured S11, S22, and S12 (under V_CTRL = 700 mV and –50 dBm input power) are shown in Figure 17. It can be seen that S11, S22, and S12 are all less than –10 dB in the range of 0–10 GHz. Therefore, the measured S21 can be used to indicate the gain of the VGA. The frequency response (S21) under different control voltages is also tested by Keysight network analyzer, as shown in Figure 18a (under –50 dBm input power). As the control voltage increases from 700 mV to 880 mV, the gain of the ABB system decreases. Figure 18b shows that the bandwidth of the ABB system increases from 4 GHz to 4.6 GHz as the control voltage increases, and its OOB rejection function provided by the filter is also verified as there is more than a 25 dB attenuation at twice the bandwidth frequency. The ABB system achieves a dB-linear gain variation range of 44 dB from 26 dB to –18 dB. Figure 18c,d summarizes the dB-linear gain range and dB-linear gain error at different frequencies. It can be seen that the ABB system has an excellent dB-linear characteristic within the dB-linear gain range of 44 dB (26 dB to –18 dB), and the dB-linear gain error is calculated to be less than ±0.5 dB.

With the provided power supply and bias voltage, the gain of the chip at 1 GHz under the input power of −50~0 dBm is scanned by the network analyzer with different control voltages to measure the IP1dB of the chip. Figure 19a displays the IP1dB results at 1 GHz of ABB system under different control voltages, ranging from –30 dBm to –5.7 dBm. In the high gain mode, the output swing exceeds the maximum allowable range, resulting in a limited IP1dB, and it can be seen that IP1dB increases as the gain decreases. However, when the input signal reaches a certain level, it becomes saturated before the output signal, resulting in the reduction of IP1dB [34]. Figure 19b presents the NF simulation results of the ABB system. It can be seen that the NF of ABB at 1 GHz is 16 dB at the highest gain, while the NF at the lowest gain is 52 dB.

Table 3. Comparison of proposed ABB with other ABBs.

	This Work	[13] 2014	[14] 2013	[15] 2012
Technology	40 nm	90 nm	65 nm	40 nm
dB-linear characteristic	Yes	No	No	No
LPF order	4th	6th	3th	5th
Gain range (dB)	–18~26	0.1~19.6	3~31	0~40
Bandwidth (GHz)	4	0.915	0.98	1
IP1dB (dBm)	–30~–5.7	N/A	–31~–4	N/A
Power (mW)	11.3	9.5	32	18
Area (mm2)	0.045	0.156	0.2	0.36

presents the comparison between this work and other ABB systems. It can be seen that, compared to other ABB systems, the proposed ABB system achieves a significant bandwidth improvement while maintaining low power consumption, thanks to the use of the active inductor technique. Additionally, the system achieves better dB-linear characteristics through the proposed self-compensated transistor technique and the error compensation method.

Table 4. Comparison of proposed VGA with other state-of-the-art VGAs.

	This Work	[9] 2018	[10] 2023	[22] 2021	[23] 2016	[27] 2019	[34] 2020
CMOS Technology	40 nm	65 nm	55 nm	40 nm	130 nm	55 nm	65 nm
Gain range (dB)	44 (–18~26)	40 (–18~22)	42.2 (–30~12.2)	51 (–34~17)	40 (–15~25)	45 (–31~14)	40 (–19~21)
dB-linear gain error (dB)	±0.5	±1	±0.79	±1	±1	±0.85	±1
Bandwidth (GHz)	4	7	0.14	7	5	0.74	4
IP1dB (dBm)	–30~–5.7	N/A	–15~0	N/A	N/A	N/A	–13~–8
Power (mW)	11.3 (8.3 *)	28	4.5	27	50	2.49	3.5
NF (dB)	16~52 **	N/A	21.3	30.5	N/A	30	17~47
Area (mm2)	0.045 (0.027 *)	0.045	0.026	0.038	0.4	0.033	0.012
FOM	1570.6	222	63.9	347.4	10	476.7	3808.3

* VGA only. ** Simulation results.

presents the comparison between this work and other state-of-the-art works. Based on [39], a modified Figure of Merit (FOM) is given by:

$$FOM={\displaystyle \frac{dB-linear Gain Range\left(dB\right)\times BW\left(GHz\right)}{Power\left(mW\right)\times Area\left(m{m}^2\right)\times Gain error\left(dB\right)}}$$

(23)

The VGAs in [10,27] offer a wide dB-linear gain range and a low dB-linear gain error but lack the bandwidth required for mmW communication applications. In contrast, the VGAs proposed in [9,22,23] provide sufficient bandwidth for mmW communication applications but rely on additional exponential generator circuits, increasing power consumption and circuit complexity. The proposed VGA achieves excellent wideband dB-linear characteristics without using additional exponential generator circuits because of the designed active inductor technique and self-compensating transistor technique, and its power consumption and area are well improved. Compared to the VGA in [34], the VGA proposed in this paper achieves a 10% improvement in dB-linear gain range and a 50% reduction in dB-linear gain error while maintaining the same bandwidth due to the proposed error compensation method. The proposed error compensation method effectively reduces the dB-linear gain error of the VGA, and can be utilized in a high-precision AGC loop to improve the accuracy of signal processing with high dynamic range. However, due to the triode mode operation of the differential pair transistors of the first-stage VGA instead of the saturation region, the linearity is largely affected, resulting in limitations for RF receivers in applications with high linearity requirements.

5. Conclusions

A compact wideband dB-linear multi-cascaded stage ABB circuit using several unique techniques for gain error correction, linearity, and stability enhancement is presented in this paper. The self-compensated transistor pair with an area-efficient active inductor is designed to realize the wideband dB-linear function in the first VGA unit, followed by second VGA unit which employs a proposed error compensation method for the dB-linear gain error correction enhancement. Moreover, an FSF structure is employed to enhance the linearity of the G_m-C LPF between the VGA and output buffer for testing purposes only, and the stability of the filter is secured by neutralization technique. The ABB prototype was fabricated in 40 nm low power (LP) CMOS technology and tested. The measurement results demonstrated that, thanks to the proposed compensation method, the ABB system achieves the state-of-the-art high precision dB-linear characteristics with a dB-linear gain error of less than 0.5 dB in the whole gain tuning range of 44 dB, and its bandwidth reaches 4 GHz with a compact size of 0.045 mm² and low power consumption under 1 V DC supply.