A Wide-Range Negative Output DC-DC Converter with Adaptive Drive Technique for Active-Matrix OLED Microdisplays

Abstract

This paper presents a DC-DC converter with wide-range negative output for active-matrix organic light-emitting diode (AMOLED). The generated negative voltage $V_{out}$ is connected to the negative terminal of the organic light-emitting diode (OLED), and the luminous brightness is adjusted by changing the value of $V_{out}$. The negative output voltage of the DC-DC converter is regulated by a Buck–Boost topology structure with a dual-loop control (DLC) system composed of a voltage loop and a current loop. The proposed compensatory peak-current-sensing technique (PCST) and switch MOSFETs adaptive drive technique (ADT) successfully support the implementation of the converter topology and enable the converter to work in continuous conduction mode (CCM). In addition, with the DLC system, the converter can guarantee a negative output voltage that enables both a fast transient response such as excellent load/line regulation, and a small output voltage ripple of the pulse width modulation (PWM) control. The proposed chip is implemented in a $0.18 \mathsf{\mu }\mathrm{m}$ CMOS process that operates at an operating frequency of $2 \mathrm{M}\mathrm{H}\mathrm{z}$ with a maximum efficiency of $85.82\mathrm{\%}$. The output voltage ripple is $1.5 \mathrm{m}\mathrm{V}$ at typical loading of $V_{out}=-4 \mathrm{V}$ and $I_{out}=100 \mathrm{m}\mathrm{A}$.

1. Introduction

In recent years, with the surge in user demand for interaction with information in the digital world and the rise of the metaverse concept, technologies such as virtual reality, augmented reality, and microdisplays have gained widespread attention across various industries worldwide. Among these, microdisplay technology plays a critically important role as the primary conduit bridging the virtual and real worlds in this field. Combining AMOLED display technology with microdisplay drive techniques can deliver superior performance in terms of high resolution, high contrast, low power consumption, and rapid response. This combination is especially well suited for integration into electronic devices such as head-mounted displays and smart glasses [1,2]. In general, driving AMOLED organic light-emitting diodes requires bipolar voltage rails. A fixed positive voltage supplies the current source for pixel color control, while a variable negative voltage is used to adjust display brightness [3]. To enhance the display quality and stability of AMOLED, a low-ripple, high-load capacity, and adjustable negative voltage DC-DC converter is of paramount importance.

This paper addresses the need for a high-resolution AMOLED microdisplay driver chip and presents a design for a fast-response, low-ripple DC-DC converter with an input voltage of $5 \mathrm{V}$ and an adjustable output voltage ranging from 0 to $-6 \mathrm{V}$. The converter can deliver a maximum output load current of $500 \mathrm{m}\mathrm{A}$. Traditional AMOLED drive circuits often employ a switched capacitor converter and charge pump to generate the required negative voltage. However, due to the substantial output ripple and limited load capacity, charge pumps typically can only drive loads of a few tens of milliamperes, which falls short of meeting the demands of this design for high output voltage and high load current [4]. In recent years, to further simplify the size of DC-DC converters used in microdisplay driver chips, many scholars have been researching single-inductor multiple-output (SIMO) converters. These converters utilize a single inductor to simultaneously generate the positive and negative voltages required for organic light-emitting diode transistors. However, this method has the problem of large output negative voltage ripple [5,6]. For this paper, the switched inductor converter, the Buck–Boost converter, is chosen to generate negative voltage, increasing the load capacity. To meet the requirement for fast response, this design employs a dual-loop control system involving voltage and current. It combines peak-current-sensing technology with PWM control mode [7]. By utilizing a higher operating frequency, meticulous loop compensation design, and slope compensation technique, it is possible to significantly reduce the output voltage ripple. Due to the relatively lower circuit conversion efficiency of the Buck–Boost topology compared to other configurations, this proposed converter chooses to incorporate synchronous rectification technology using NMOS as the switch to effectively enhance the efficiency of the converter. Furthermore, since the source terminal of the main switch and the drain terminal of the synchronous rectification switch in the Buck–Boost topology are constantly switching between positive and negative voltages, an effective design of the drive circuit can further optimize the output voltage ripple and enhance the efficiency of the converter.

2. Control System Design for the Proposed Buck–Boost Converter

2.1. Control System Composition

This paper introduces a design proposal for a DC-DC switch converter with both boost and buck capabilities, intended for application in an AMOLED driver chip. Using the Buck–Boost topology, the design can achieve either boosting or bucking of negative voltages, fulfilling the requirement of an adjustable output voltage range from 0 to $-6 \mathrm{V}$. PWM modulation is a method that utilizes a fixed clock frequency to achieve stable output voltage by altering the duty cycle of the gate signal of the switch transistor through feedback loops. This modulation technique is characterized by low noise, efficient performance under heavy loads, and operation in continuous conduction mode. The peak-current mode is a dual feedback loop control mode that samples both the inductor current and the output voltage. This approach significantly improves line regulation compared to the traditional single feedback loop control mode. Simultaneously, system stability is optimized, simplifying loop compensation [8]. The proposed converter employs a control method that combines peak-current mode and PWM modulation to achieve fundamental control of the loop. The internal control structure of the Buck–Boost converter is shown in Figure 1.

The black dashed line in Figure 1 represents the off-chip passive components, including the input voltage source $V_{IN}$, inductor $L$, output load resistance $R_O$, filter capacitor $C$, and its parasitic $\mathrm{E}\mathrm{S}\mathrm{R}$ resistance. The remaining modules, including the two NMOS main switch transistors $\mathrm{M}1$ and the synchronous rectification transistor $\mathrm{M}2$, are integrated on chip. The on-chip integrated modules mainly include the bandgap reference circuit [9], error amplifier, current-sensing circuit ($\mathrm{S}\mathrm{a}\mathrm{m}\mathrm{p}\mathrm{l}\mathrm{e}\_\mathrm{I}$), PWM comparator, oscillator (including slope compensation module), overcurrent protection circuit $\left(\mathrm{O}\mathrm{C}\mathrm{P}\right)$, dead-time control module, level shifter, logic module, and switch transistor adaptive drive module. To reduce power consumption and enhance circuit efficiency, this design employs two supply voltage sources: $1.8 \mathrm{V}$ and $5 \mathrm{V}$. In Figure 1, modules powered by a $1.8 \mathrm{V}$ power supply are all specially marked. Among them, $\mathrm{S}\mathrm{a}\mathrm{m}\mathrm{p}\mathrm{l}\mathrm{e}\_\mathrm{I}$ is supplied with a combination of $1.8 \mathrm{V}$ and $5 \mathrm{V}$ sources, while the remaining modules are powered by a $5 \mathrm{V}$ power supply.

2.2. Control System Operation Principle

During power-up and until $V_{out}$ reaches the targeted voltage when $\mathrm{V}\mathrm{F}\mathrm{B}$ is greater than $\mathrm{G}\mathrm{N}\mathrm{D}$, the $\mathrm{P}\mathrm{W}\mathrm{M}$ output remains low. In this state, the reversal of the switch transistor drive signals is controlled by the limiting signal $V_{limit}$ generated from $\mathrm{O}\mathrm{C}\mathrm{P}$. When the rising edge of $\mathrm{C}\mathrm{L}\mathrm{K}$ arrives, the drive signal causes $\mathrm{M}1$ to turn on and $\mathrm{M}2$ to turn off, leading to an increase in inductor current. Once the current reaches a certain value, $V_{limit}$ flips, causing the drive signal to invert. As a result, $\mathrm{M}1$ turns off and $\mathrm{M}2$ turns on, causing the inductor current to decrease and charge the output capacitor $C$. This process then repeats. Until $V_{out}$ reaches the targeted voltage, $V_{EA}$ decreases, and $V_{isense}$ increases during the conduction of $\mathrm{M}1$. When $V_{EA}=V_{isense}$, the $\mathrm{P}\mathrm{W}\mathrm{M}$ output is a logic high signal that turns off $\mathrm{M}1$ and turns on $\mathrm{M}2$. When the rising edge of $\mathrm{C}\mathrm{L}\mathrm{K}$ arrives again, the drive signal inverts and the system enters a dual-loop control mode for both current and voltage. This cycle repeats with each clock period, maintaining the output voltage $V_{out}$ to be relatively stable.

In general, the voltage control loop where $\mathrm{V}\mathrm{F}\mathrm{B}$ is situated can quickly respond to transient loading current. If the system experiences a transient change in input voltage, in the case of traditional single voltage loop control mode, the switch transistor drive signal needs to wait until the input change is reflected in the output and then adjusted through the voltage loop. This leads to a slow response rate and significant output voltage overshoot [10]. The peak-current mode control employed in the proposed converter utilizes the $\mathrm{S}\mathrm{a}\mathrm{m}\mathrm{p}\mathrm{l}\mathrm{e}\_\mathrm{I}$ module to directly capture signals of input voltage transient changes. Through the current loop, rapid adjustment of the drive signal is achieved, resulting in a fast response and minimal output voltage overshoot. Therefore, the peak-current mode control offers more stable output voltage and superior immunity to input source disturbances compared to the traditional signal voltage loop control mode.

3. Stability Analysis and Circuit Implementation

3.1. Loop Stability Analysis

For a power conversion chip, the output voltage must remain stable when faced with fluctuations in the input voltage or other external factors. Hence, to ensure system stability, this paper undertakes small-signal modeling of the Buck–Boost system using the peak-current mode control [11,12], as depicted in Figure 2. It proceeds to derive the system’s transfer function and compensation calculations.

In the diagram, $G_{ig}\left(s\right)=i_L\left(s\right)/V_g\left(s\right)$, $G_{id}\left(s\right)=i_L\left(s\right)/d\left(s\right)$, $G_{vg}\left(s\right)=V_O\left(s\right)/V_g\left(s\right)$, $G_{vd}\left(s\right)=V_O\left(s\right)/d\left(s\right)$ represent the power stage switch model for the voltage–current dual-loop control mode. In the control stage, $G_{fb}=R_2/\left(R_1+R_2\right)$ represents the resistor feedback network; $G_C$ represents the error amplifier and RC compensation network; the voltage-to-current model can be represented as $1/R_i$. $F_m$ represents the conversion network from $i_C$ to the duty cycle control signal $\mathrm{D}$, which is related to slope compensation and the slope of inductor current variation. The function of $F_m$ is given by

$$F_m=\frac{∆d}{{∆i}_c\left(t\right)}=\frac{1}{\left(S_e+S_n\right)·T_s}$$

(1)

where $S_e$, $S_n$ and $T_s$, respectively, represent slope compensation rate, inductor current decay rate, and operating period. $S_n$ represents the decrease in current per unit time during the discharge of the inductor ${∆i}_n$; $S_e$ represents the slope compensation current per unit time ${∆i}_n$. To avoid sub-harmonic oscillations when the duty cycle control signal $\mathrm{D}$ exceeds 50%, setting $S_e>0.5·S_n$ ensures system stability. $H_e$ represents the sample-and-hold effect model for peak-current-sensing technology. The function of $H_e$ is given by

$$He\left(s\right)=\frac{\widehat{d\left(s\right)}}{\widehat{i_L\left(s\right)}}·\frac{1}{Fm}=\frac{s·T_s}{e^{s·T_s}-1}=1-\frac{s}{Q_z·{\omega }_n}+{\left(\frac{s}{{\omega }_n}\right)}^2$$

(2)

where ${\omega }_n=1/\left(2·T_s\right),Q_z=-2/\pi$. $k_f$ represent the influence of input voltage variation $∆V_g$ on the signal $\mathrm{D}$. $k_r$ represents the influence of output load transients on $\mathrm{D}$. The functions of $k_f$ and $k_r$ are given by

$$k_f=-\frac{D·\left(1-D/2\right)·T_s·R_i}{L}$$

(3)

$$k_r=\frac{{\left(1-D\right)}^2·T_s·R_i}{2L}$$

(4)

Based on the above equations, the overall transfer function of the system is given by

$$F_{loop}\left(s\right)=\frac{V_{out}\left(s\right)}{i_c\left(s\right)}·\frac{G_{fb}·G_C}{R_i}=G_{ic}\left(s\right)·\frac{G_{fb}·G_C}{R_i}$$

(5)

The function of the current loop is given by

$$i_L\left(s\right)=\left[i_c\left(s\right)+k_r·V_{out}\left(s\right)\right]·\frac{F_m·G_{id}}{H_e·F_m·G_{id}+1}$$

(6)

The function of the voltage loop is given by

$$\begin{array}{cc}{V}_{out}\left(s\right)& =\left[i_c\left(s\right)+k_r·V_{out}\left(s\right)-H_e·i_L\left(s\right)\right]·F_m·G_{vd}\\ & =\left[i_c\left(s\right)+k_r·V_{out}\left(s\right)\right]·\frac{F_m·G_{vd}}{H_e·F_m·G_{vd}+1}\hfill \end{array}$$

(7)

From (6) to (7), the transfer function of $G_{ic}\left(s\right)$ is given by

$$G_{ic}\left(s\right)=\frac{V_{out}\left(s\right)}{i_c\left(s\right)}=\frac{G_{ic0}}{\left(1+s/{\omega }_p\right)}·\frac{\left(1-s/{\omega }_z\right)}{\left(1+s/\left(Q_p·{\omega }_n\right)+{\left(s/{\omega }_n\right)}^2\right)}$$

(8)

where $Q_p=1/\left[\pi ·\left(m_c·D^{\prime }-0.5\right)\right],m_c=S_e/S_n+1,{\omega }_n=\mathsf{\pi }/{\mathrm{T}}_{\mathrm{s}}$. The transfer function without the loop compensation of $G_C$ is given by

$${\mathrm{F}}_{loop0}\left(s\right)=\frac{1}{R_i}·\frac{R_2}{R_1+R_2}·\frac{G_{ic0}}{\left(1+s/{\omega }_p\right)}·\frac{\left(1-s/{\omega }_z\right)}{\left(1+s/\left(Q_p·{\omega }_n\right)+{\left(s/{\omega }_n\right)}^2\right)}$$

(9)

This transfer function only has one low-frequency left-half-plane pole ${\omega }_p$, which significantly affects the loop stability. The system exhibits sufficient phase margin, enabling the use of a Proportional–Integral (PI) controller structure for the $G_C$. This compensates for the loop’s low-frequency gain and $\mathrm{G}\mathrm{B}\mathrm{W}$. The transfer function of the PI controller is given by

$$G_C=G_{c0}·\frac{\left(1+{\omega }_{z1}/s\right)}{\left(1+s/{\omega }_{p1}\right)}$$

(10)

where ${\omega }_{z1}$ is employed to provide low-frequency gain, while ${\omega }_{p1}$ serves to mitigate noise. The fundamental structure of the PI controller is illustrated in Figure 3.

3.2. Implementation of Voltage Control Loop

The voltage control loop is mainly composed of a bandgap reference circuit, feedback resistors, an error amplifier, and a PI compensation circuit. To simplify the content of this paper, this section focuses primarily on the basic construction of the error amplifier.

The role of the error amplifier in the control loop is to amplify the small error between the amplified output voltage feedback $\mathrm{V}\mathrm{F}\mathrm{B}$ and the reference voltage. The amplified error signal is then fed into the positive terminal of the PWM comparator to adjust the pulse width of the switch signal, thereby achieving output stability. As the core of the voltage feedback loop, the error amplifier is required to have a sufficiently large gain and slew rate to enhance output voltage accuracy and response speed. Simultaneously, higher gain–bandwidth product $\mathrm{G}\mathrm{B}\mathrm{W}$ and output slew rate are required to enhance transient response speed and optimize the converter load adjustment rate. Therefore, the folded cascode amplifier employed in this design effectively meets these requirements.

The schematic diagram of the folded cascode amplifier design is illustrated in Figure 4. Components ${\mathrm{M}}_{\mathrm{P}1}$, ${\mathrm{M}}_{\mathrm{P}2}$, ${\mathrm{M}}_{\mathrm{N}1},$ and ${\mathrm{M}}_{\mathrm{N}2}$ constitute the folded cascode structure, and the use of PMOS as the input pair effectively reduces flicker noise. ${\mathrm{M}}_{\mathrm{N}3}$, ${\mathrm{M}}_{\mathrm{N}4}$, and ${\mathrm{M}}_{\mathrm{P}3}~{\mathrm{M}}_{\mathrm{P}7}$ constitute the biased current source, wherein ${\mathrm{M}}_{\mathrm{P}4}~{\mathrm{M}}_{\mathrm{P}7}$ adopt a low-voltage cascode current mirror structure to further enhance the output swing of the error amplifier. ${\mathrm{M}}_{\mathrm{N}5}~{\mathrm{M}}_{\mathrm{N}13}$ and ${\mathrm{M}}_{\mathrm{P}8}~{\mathrm{M}}_{\mathrm{P}17}$ constitute the bias circuit. To achieve higher DC gain, error amplifiers generally adopt a two-stage amplification structure. However, this structure not only increases additional power consumption but also introduces complex phase margin compensation issues, significantly impacting the overall stability and loop bandwidth of the system. The folded cascode amplifier designed in this paper is a single-stage amplifier. Combined with the $\mathrm{P}\mathrm{I}$ controller, it provides a low-frequency gain of $71 \mathrm{d}\mathrm{B}$, meeting the requirement for high gain while avoiding the issues associated with a two-stage structure.

3.3. Implementation of Current Control Loop

In the peak-current mode control, sub-harmonic oscillations [13] occur when the duty cycle of the switch transistor drive signal exceeds $50\mathrm{\%}$. To mitigate such oscillations, the implementation of the current control loop requires not only the sampling of inductor current but also a specific slope compensation applied to the sampled current. Traditional current sensing techniques involve placing a series sampling resistor at the power stage to obtain inductor current information based on the voltage drop across the resistor [14]. Due to the high current at the power stage, this method consumes significant power on the sampling resistor, significantly reducing the efficiency of the converter. Another current sensing technique involves utilizing the current information obtained from the conduction resistance of the main switch transistor $\mathrm{M}1$ and the voltage drop across its terminals. However, the conduction resistance is subject to significant variations due to factors such as temperature, impacting the accuracy of the sampling circuit. The proposed high-precision peak-current-sensing technique (PCST) in this paper introduces a sampling transistor, proportional to the main switching transistor, to sample information during the rising phase of the inductor current. This sampling method not only significantly reduces power consumption compared to traditional sampling techniques but also cancels the impact of Process, Voltage, and Temperature (PVT) variations on sampling accuracy. Additionally, the integrated $\mathrm{O}\mathrm{C}\mathrm{P}$ circuit within the PCST prevents chip damage due to excessive surge currents and assists in the proper startup of the system.

The proposed PCST circuit is depicted in Figure 5, encompassing a fundamental sensing circuit comprised of a current amplifier, a current limiting protection circuit, and a slope compensation voltage-to-current circuit. The primary switch employed in this design is LDNMOS [15]. To achieve better matching, the PCST circuit employs a transistor $\mathrm{M}0$ of the same type as $\mathrm{M}1$ as the sampling transistor. The source and gate terminals of $\mathrm{M}0$ are connected in parallel with $\mathrm{M}1$. When the gate signal is high, the sampling current during the rising phase of the inductor current is obtained. The sampling current then passes through the resistor $R_0$. The relationship between the sampling current $I_{R_0}$ and the inductor current $I_L$ is given by

$$I_{R_0}=I_{M0}=\frac{{\left(W/L\right)}_{M0}}{{\left(W/L\right)}_{M1}}·I_{M1}=\frac{{\left(W/L\right)}_{M0}}{{\left(W/L\right)}_{M1}}·I_L$$

(11)

It is important to note that, in this subsection, $W$ and $L$ represent the channel width and length of the transistors, respectively.

Continuing to utilize the current amplifier, $I_{R0}$ is further scaled down by a factor of $R_1/R_0=10/1$. ${\mathrm{M}}_{\mathrm{N}1}$ and ${\mathrm{M}}_{\mathrm{N}2}$ provide a constant bias current for the current amplifier, while ${\mathrm{M}}_{\mathrm{P}1}$ and ${\mathrm{M}}_{\mathrm{P}2}$ are current mirrors operating in the saturation region. Due to the equal current $I_b$ flowing through ${\mathrm{M}}_{\mathrm{P}1}$ and ${\mathrm{M}}_{\mathrm{P}2}$, and their gate voltages $V_g$ being equal, the source voltages of ${\mathrm{M}}_{\mathrm{P}1}$ and ${\mathrm{M}}_{\mathrm{P}2}$ and $V_A$ and $V_B$, are also equal. $R_1=R_2$. When current flows through $R_0$, the voltage across its terminals becomes unequal. The current $I_{R1}$ flowing through $R_1$ is the sum of the currents flowing through ${\mathrm{M}}_{\mathrm{P}1}$ and ${\mathrm{M}}_{\mathrm{P}3}$. Through simple calculations, the function of the sampled current after secondary scaling is given by

$$I_{sense}{=I}_{M_{P3}}=I_{R1}-I_b=\left(V_{IN}-V_X\right)/R_1=\frac{R_0}{R_1}·I_{R0}=\frac{R_0}{R_1}·\frac{{\left(W/L\right)}_{M0}}{{\left(W/L\right)}_{M1}}·I_L$$

(12)

From Formula (12), we can understand that $I_{sense}$ is proportional to the ratio of resistors $R_0$ and $R_1$ ($R_2$). We choose resistors $R_0$, $R_1$, and $R_2$ of the same type, avoiding the influence of different temperature coefficients on the scaling ratio of the sampling current. This further enhances the sampling accuracy.

The current mirrors ${\mathrm{M}}_{\mathrm{N}3},{\mathrm{M}}_{\mathrm{N}4}$, and ${\mathrm{M}}_{\mathrm{P}4}~{\mathrm{M}}_{\mathrm{P}9}$ replicate $I_{sense}$, each flowing through $R_3$ and $R_4$. By converting $I_{sense}$ into a voltage signal $V_{pro}$, the integration of the $\mathrm{O}\mathrm{C}\mathrm{P}$ function is achieved using a comparator. When $I_{sense}$ reaches the current limit value, the signal $V_{limit}$ from the output of the comparator takes precedence as a higher priority logic signal, controlling $\mathrm{M}1$ to turn off. This action stops the further rise of the inductor current. The error amplifier $\mathrm{E}\mathrm{A}$, along with ${\mathrm{M}}_{\mathrm{N}5}$ and $R_5$, accomplishes the conversion of the slope compensation voltage $V_{slope}$ to the slope compensation current $I_{slope}$. The current mirrors ${\mathrm{M}}_{\mathrm{P}10}$ and ${\mathrm{M}}_{11}$ superpose $I_{slope}$ and $I_{sense}$, resulting in the peak current sampling voltage $V_{isense}$. The circuit generating $V_{slope}$ will be elaborated in detail in Section 3.4.

3.4. Clock Oscillator and Slope Compensation Circuit

Based on the analysis in the preceding sections, an oscillator is required to generate clock pulse signals, providing the system with a constant operating frequency. Additionally, it is essential to generate a sawtooth wave slope compensation signal with specific slopes for superimposing on the current sampling signal. A higher operating frequency and an appropriate slope compensation signal can significantly reduce the magnitude of output voltage ripple [16]. To effectively reduce output voltage ripple, the proposed converter’s chosen operating frequency is 2 MHz. However, further increasing the clock frequency may result in excessive switch power loss in the converter, leading to a decrease in efficiency. The preset slope compensation slope $S_e$ is set to be equal to the maximum inductor current decay rate $S_n$. The implementation circuit for the sawtooth wave oscillator is depicted in Figure 6.

$V_{ref}$ serves as the input bandgap reference signal, $\mathrm{C}\mathrm{L}\mathrm{K}$ is the output clock signal, and $V_{slope}$ represents the output slope compensation voltage. In Figure 6a, $\mathrm{E}\mathrm{A}$, transistor ${\mathrm{M}}_{\mathrm{N}1}$, and $R_1$ constitute a negative feedback system yielding the current source $I_{SS}=V_{ref}/R_1$. $I_{SS}$ provides charging current to the capacitor $C_1$ through the current mirrors ${\mathrm{M}}_{\mathrm{P}1}~{\mathrm{M}}_{\mathrm{P}3}$. The currents flowing through $R_2$ and $R_3$ generate threshold voltages $V_H$ and $V_L$. Figure 6b depicts the charge–discharge control circuit, primarily comprising two comparators and an SR flip-flop constructed using two NAND gates. Assuming the initial value of $V_{ramp}$ is 0, the output $V_{O1}$ of comparator $\mathrm{C}\mathrm{o}\mathrm{m}\mathrm{p}1$ is high, the output $V_{O2}$ of comparator $\mathrm{C}\mathrm{o}\mathrm{m}\mathrm{p}2$ is low, and the $\mathrm{C}\mathrm{L}\mathrm{K}$ output is at a low level. With ${\mathrm{M}}_{\mathrm{N}2}$ turned off, the capacitor $C_1$ begins to charge. Continuing this cycle, the oscillator produces a short pulse clock signal, $\mathrm{C}\mathrm{L}\mathrm{K}$. Through a simple derivation, the function of frequency expression for the clock signal is given by

$$f\approx \frac{I_{M_{P2}}}{C_1·\left(V_H-V_L\right)}$$

(13)

In the left-side circuit of Figure 6a, ${\mathrm{M}}_{\mathrm{P}4}$, ${\mathrm{M}}_{\mathrm{N}3}$, $C_2$ and the inverter constitute the slope compensation signal generation circuit, with the input terminal $V_{in\_s}$ connected to the gate drive signal of the main switch transistor $\mathrm{M}1$. When $\mathrm{M}1$ is turned on, $V_{in\_s}$ is at a high level, causing ${\mathrm{M}}_{\mathrm{N}3}$ to turn off and capacitor $C_2$ to charge, leading to the rise of $V_{slope}$. When $\mathrm{M}1$ is turned off, $V_{in\_s}$ is at a low level, causing ${\mathrm{M}}_{\mathrm{N}3}$ to turn on, and $V_{slope}$ outputs as 0. This cycle repeats in this manner every period. The proposed slope compensation generation circuit can obtain a sawtooth wave signal of $V_{slope}$, possessing the same rise time as the inductor current. Furthermore, by adjusting the values of $C_2$ and the current of ${\mathrm{M}}_{\mathrm{P}4}$, the slope compensation slope of $S_e$ can be controlled to match $S_n$. The function of $S_e$ is given by

$$S_e=\frac{I_{M_{P4}}}{C_2}=\left|\frac{V_{out}}{L}\right|=S_n$$

(14)

3.5. Implementation of PWM Comparator

In the preceding Section 3.2 and Section 3.3, we obtained the output voltage $V_{EA}$ of the voltage control loop and the sampled voltage $V_{isense}$ of the current control loop. By utilizing the $\mathrm{P}\mathrm{W}\mathrm{M}$ comparator to compare these two signals, it generates the pulse signals for controlling the main switching transistor $\mathrm{M}1$ and the synchronous rectification transistor $\mathrm{M}2$. Comparators exhibit an unavoidable time delay between input excitation and corresponding output, known as the propagation delay. The voltage gain $A_V$ influences the small-signal dynamic characteristics of the comparator, determining the minimum input differential voltage required for the comparator to toggle between high and low levels, i.e., the accuracy of the comparator. The magnitude of the propagation delay affects the accuracy of the output voltage and the size of the output voltage ripple. Therefore, the precise design of the $\mathrm{P}\mathrm{W}\mathrm{M}$ comparator is crucial. The $\mathrm{P}\mathrm{W}\mathrm{M}$ comparator designed in this paper is illustrated in Figure 7.

In order to enhance the voltage gain, the comparator adopts a three-stage amplification structure with an output stage cascade. ${\mathrm{M}}_{\mathrm{P}1}~{\mathrm{M}}_{\mathrm{P}6}$ and $R_1~R_4$ form the first and second-stage differential amplifiers. To broaden the lower limit range of the input common-mode level, resistors are used as loads, where $R_1=R_2=R_3=R_4$. ${\mathrm{M}}_{\mathrm{P}7}~{\mathrm{M}}_{\mathrm{P}9}$, ${\mathrm{M}}_{11}$, and ${\mathrm{M}}_{\mathrm{N}2}$ constitute the third-stage current mirror load differential amplifier, which aims to achieve the conversion from differential output to single-ended output. ${\mathrm{M}}_{\mathrm{P}10}$ and ${\mathrm{M}}_{\mathrm{N}3}$ form the high-swing output stage. The expression for voltage gain is

$$A_V=g_{m\_P2}·g_{m_{P5}}·R_1·g_{m_{P8}}·\left(r_{O_{N3}}\left|\right|r_{O_{P10}}\right)$$

(15)

The proposed $\mathrm{P}\mathrm{W}\mathrm{M}$ comparator exhibits a low-frequency gain of $147 \mathrm{d}\mathrm{B}$, with a DC voltage gain as high as $123 \mathrm{d}\mathrm{B}$ at a switching frequency of $2 \mathrm{M}\mathrm{H}\mathrm{z}$. The gain–bandwidth product is $19.5 \mathrm{M}\mathrm{H}\mathrm{z}$, meeting the design requirements.

3.6. Implementation of the Drive Circuit

The Buck–Boost converter operates with $V_{IN}$ = 5 V, $V_{out}$ that can go as low as $-6 \mathrm{V}$, and a voltage range of $-6 \mathrm{V}$ to $5 \mathrm{V}$ for the SW node. The maximum source-drain voltage across the main switch transistor $\mathrm{M}1$ and synchronous rectification switch $\mathrm{M}2$ is $11 \mathrm{V}$. When $\mathrm{M}1$ is turned on, the source terminal of the SW node approaches $V_{IN}$, necessitating an increase in the gate voltage $\mathrm{H}\mathrm{V}\_\mathrm{N}$ to ${\mathrm{V}}_{\mathrm{I}\mathrm{N}}+5 \mathrm{V}$. When $\mathrm{M}1$ is turned off, SW approaches $V_{out}$, requiring $\mathrm{H}\mathrm{V}\_\mathrm{N}$ to be pulled down to $V_{SW}$. When $\mathrm{M}2$ is turned on, as the source terminal is continuously connected to $V_{out}$, the gate voltage $\mathrm{L}\mathrm{V}\_\mathrm{N}$ needs to be raised to $V_{out}+5 \mathrm{V}$. When $\mathrm{M}2$ is turned off, $\mathrm{L}\mathrm{V}\_\mathrm{N}$ needs to be pulled down to $V_{out}$.

To meet the level shift requirements, the proposed power-stage switch adaptive drive technique (ADT) scheme has been depicted in Figure 8. The duty cycle signal output from the logic circuit is processed by the dead-time control circuit, resulting in the generation of the duty cycle signals $\mathrm{d}\mathrm{r}\mathrm{v}\_\mathrm{H}$ and $\mathrm{d}\mathrm{r}\mathrm{v}\_\mathrm{L}$ for $\mathrm{M}1$ and $\mathrm{M}2$, respectively. These signals are then fed into the bootstrap circuit and clamped with the level-down circuit. After passing through the high-power buffer, $\mathrm{H}\mathrm{V}\_\mathrm{N}$ and $\mathrm{L}\mathrm{V}\_\mathrm{N}$ are realized to drive $\mathrm{M}1$ and $\mathrm{M}2$.

3.6.1. Dead-Time Control Circuit

Traditional DC-DC converters utilize off-chip MOSFET and diodes as the main switch $\mathrm{M}1$ and synchronous rectification switch $\mathrm{M}2$, respectively. While this approach is straightforward, the efficiency of the converter is compromised due to the significant IR drop across the diode during conduction. The proposed converter employs synchronous rectification technology, utilizing NMOS transistors as both $\mathrm{M}1$ and $\mathrm{M}2$, which are integrated into the chip. This technology not only effectively reduces conduction losses to improve converter efficiency but also significantly reduces the need for off-chip components, leading to a higher degree of integration in the converter. It is essential to note that during the alternating switching of $\mathrm{M}1$ and $\mathrm{M}2$, due to differences in switching speed and gate drive signal propagation delay, there might be a brief period where both transistors are conducting simultaneously. During this time, a substantial current may flow between $V_{IN}$ and $V_{out}$. This can not only increase power consumption and impair chip operation but also potentially lead to chip damage [17]. To mitigate this issue, a dead-time control circuit is added, introducing a period of simultaneous low signals at the gate drive of $\mathrm{M}1$ and $\mathrm{M}2$. This circuit ensures that one switch is completely turned off before the other turns on. This period, known as the dead time, is denoted as $t_d$.

Figure 9 illustrates the schematic of the dead-time control circuit. The input signal $\mathrm{d}\mathrm{r}\mathrm{v}\_\mathrm{i}\mathrm{n}$ is the duty cycle signal obtained from the logic circuit module. This signal is split into two paths after being inverted by ${\mathrm{I}\mathrm{N}\mathrm{V}}_1$: The upper path signal, after being processed by ${\mathrm{I}\mathrm{N}\mathrm{V}}_2$ and passed through an RC delay network formed by $R_1$ and $C_1$, is sent into a logic circuit composed of ${\mathrm{M}}_{\mathrm{P}1}$, ${\mathrm{M}}_{\mathrm{P}3}$, ${\mathrm{M}}_{\mathrm{N}2}$, ${\mathrm{M}}_{\mathrm{N}3}$, ${\mathrm{I}\mathrm{N}\mathrm{V}}_3$, and ${\mathrm{I}\mathrm{N}\mathrm{V}}_4$. This logic circuit generates the duty cycle signal $\mathrm{d}\mathrm{r}\mathrm{v}\_\mathrm{L}$ for $\mathrm{M}2$. The lower path signal is sent into a logic circuit composed of ${\mathrm{M}}_{\mathrm{P}2}$, ${\mathrm{M}}_{\mathrm{P}4}$, ${\mathrm{M}}_{\mathrm{N}1}$, ${\mathrm{M}}_{\mathrm{N}4}$, ${\mathrm{I}\mathrm{N}\mathrm{V}}_5$, and ${\mathrm{I}\mathrm{N}\mathrm{V}}_6$. The output signal from this logic circuit is passed through an RC delay network formed by $R_2$ and $C_2$ and further processed by dual ${\mathrm{I}\mathrm{N}\mathrm{V}}_7$ and ${\mathrm{I}\mathrm{N}\mathrm{V}}_8$, yielding the duty cycle signal $\mathrm{d}\mathrm{r}\mathrm{v}\_\mathrm{H}$ for $\mathrm{M}1$. Figure 10 shows the waveform diagrams of input and output signals. The function of dead-time $t_d$ is given by

$$t_d\approx R_1·C_1-R_2·C_2$$

(16)

3.6.2. Bootstrap Circuit

Due to ${\mathrm{M}}_1$ is an NMOS transistor, which compared to a PMOS transistor of the same size, exhibits smaller on-resistance and chip area. The drain voltage of ${\mathrm{M}}_1$ is $V_{IN}$. When ${\mathrm{M}}_1$ is turned on, the source voltage is $V_{IN}-V_{ds\_M_1}$, where the small on-resistance drop $V_{ds\_M_1}$ effectively reduces power consumption. To enhance the drive capability of the gate voltage and reduce on-resistance losses, this paper presents a level-shifting bootstrap circuit [18] that raises the gate drive signal from $5 \mathrm{V}$ to $10 \mathrm{V}$ when ${\mathrm{M}}_1$ turns on and lowers it from $0 \mathrm{V}$ to the same potential as the source voltage $\mathrm{S}\mathrm{W}$ when ${\mathrm{M}}_1$ is turned off. The circuit schematic is illustrated in Figure 11.

In the circuit, the input signal $\mathrm{d}\mathrm{r}\mathrm{v}\_\mathrm{H}$ has a high voltage of $5\mathrm{V}$ and a low voltage of $0 \mathrm{V}$. The positive terminal of capacitor $C$ is connected to the $5 \mathrm{V}$ power supply voltage through the diode ${\mathrm{D}}_1$, while the negative terminal is connected to $\mathrm{d}\mathrm{r}\mathrm{v}\_\mathrm{H}$ through a buffer. When the output of $\mathrm{d}\mathrm{r}\mathrm{v}\_\mathrm{H}$ is $0 \mathrm{V}$, the voltage of $\mathrm{B}\mathrm{O}\mathrm{O}\mathrm{S}\mathrm{T}$ is $5 \mathrm{V}$. Using the principle that the voltage difference across a capacitor cannot change abruptly when $\mathrm{d}\mathrm{r}\mathrm{v}\_\mathrm{H}$ flips to $5 \mathrm{V}$, the voltage at the voltage of $\mathrm{B}\mathrm{O}\mathrm{O}\mathrm{S}\mathrm{T}$ is raised close to $10 \mathrm{V}$.

The positive feedback latch structure formed by ${\mathrm{M}}_{\mathrm{P}1}~{\mathrm{M}}_{\mathrm{P}4}$, ${\mathrm{M}}_{\mathrm{N}1},$ and ${\mathrm{M}}_{\mathrm{N}2}$ accelerates the speed of the output voltage transition. Assuming that $\mathrm{d}\mathrm{r}\mathrm{v}\_\mathrm{H}$ starts at $0 \mathrm{V}$, ${\mathrm{M}}_{\mathrm{N}2}$ and ${\mathrm{M}}_{\mathrm{N}4}$ are turned on, causing the $\mathrm{H}\mathrm{V}\_\mathrm{N}$ to be pulled down to $\mathrm{S}\mathrm{W}$. ${\mathrm{M}}_1$ is turned off, and during this time, capacitor $C$ charges. When $\mathrm{d}\mathrm{r}\mathrm{v}\_\mathrm{H}$ transitions to $5 \mathrm{V}$, ${\mathrm{M}}_{\mathrm{N}1}$ and ${\mathrm{M}}_{\mathrm{P}6}$ are turned on, resulting in the raising of $\mathrm{H}\mathrm{V}\_\mathrm{N}$ to $\mathrm{B}\mathrm{O}\mathrm{O}\mathrm{S}\mathrm{T}$. This achieves the flip of the main switch transistor drive voltage from $\mathrm{S}\mathrm{W}$ to $10 \mathrm{V}$. The input and output signal waveforms are shown in Figure 12.

3.6.3. Clamp and Level-Down Circuit

The source terminal of the synchronous rectification transistor ${\mathrm{M}}_2$ is connected to the converter output $V_{out}$, with a minimum of $-6 \mathrm{V}$. The duty cycle signal $\mathrm{d}\mathrm{r}\mathrm{v}\_\mathrm{L}$ from the dead-time control circuit transitions between $0 \mathrm{V}$ and $5 \mathrm{V}$. Due to the use of LDNMOS transistors with a gate-source withstand voltage of $5 \mathrm{V}$ as ${\mathrm{M}}_2$, if the $\mathrm{d}\mathrm{r}\mathrm{v}\_\mathrm{L}$ signal is directly connected to the gate terminal of ${\mathrm{M}}_2$ without adjustment, it may lead to the inability of the device to turn off properly [19]. Thus, we need to clamp the gate terminal signal of ${\mathrm{M}}_2$. After clamping, the gate-source voltage is set to $V_{gs\_M_2}=4V_{gs\_NMOS}$.

The schematic diagram of the clamp and level-down circuit for the synchronous rectification transistor is shown in Figure 13. This circuit is divided into two parts: the clamp voltage generation circuit and the level-down circuit. The input terminal $\mathrm{V}\mathrm{N}\mathrm{E}\mathrm{G}$ is the output of the converter and, together with ${\mathrm{M}}_{\mathrm{P}1}~{\mathrm{M}}_{\mathrm{P}3}$, ${\mathrm{M}}_{\mathrm{N}1}~{\mathrm{M}}_{\mathrm{N}6}$, $R_0$, $R_1$, and capacitor $C$, forms the clamp voltage generation circuit. The current source $i_b$ provides bias current for the clamp transistors ${\mathrm{M}}_{\mathrm{N}3}~{\mathrm{M}}_{\mathrm{N}6}$, ensuring that the clamp voltage always satisfies $VNEGP5=VNEG+4V_{gs\_NMOS}$. This ensures that when ${\mathrm{M}}_2$ is turned on, the gate-source voltage does not vary with changes in $V_{out}$. The level-down circuit on the right of Figure 13 is controlled by the pulse signals $V_{pulse1}$ and $V_{pulse2}$ and the level signals $V_{in1}$ and $V_{in2}$. $\mathrm{V}\mathrm{N}\mathrm{E}\mathrm{G}\mathrm{P}5$ serves as the high-voltage output signal for the level-down circuit, and $\mathrm{V}\mathrm{N}\mathrm{E}\mathrm{G}$ acts as the low-voltage output signal. $V_{in1}$ is the duty cycle signal of ${\mathrm{M}}_2$. After passing through the pulse generation circuit shown in Figure 14, $V_{pulse1}$ and $V_{pulse2}$ are obtained. The pulse width can be adjusted by changing the capacitance value, as shown in Figure 15 for the specific waveform.

The proposed level-down circuit uses a two-stage positive feedback latch structure to accelerate the inversion speed of the output voltage. ${\mathrm{M}}_{\mathrm{P}10}$, ${\mathrm{M}}_{\mathrm{P}11}$, ${\mathrm{M}}_{\mathrm{N}13}$, and ${\mathrm{M}}_{\mathrm{N}14}$ constitute the first-stage positive feedback structure, while ${\mathrm{M}}_{\mathrm{P}8}$, ${\mathrm{M}}_{\mathrm{P}9}$, ${\mathrm{M}}_{\mathrm{N}11}$, and ${\mathrm{M}}_{\mathrm{N}12}$ constitute the second-stage positive feedback structure. When the falling edge of $V_{in1}$ arrives, $V_{pulse1}$ generates a low pulse signal, causing ${\mathrm{M}}_{\mathrm{P}4}$ to turn on and allow a large current to flow through the current mirror ${\mathrm{M}}_{\mathrm{N}9}$ and ${\mathrm{M}}_{\mathrm{N}10}$, pulling node ${\mathrm{X}}_1$ down to $\mathrm{V}\mathrm{N}\mathrm{E}\mathrm{G}$. The signal $V_{in1}$ causes ${\mathrm{M}}_{\mathrm{P}6}$ to turn on, raising the node ${\mathrm{X}}_2$ to a level near $\mathrm{V}\mathrm{N}\mathrm{E}\mathrm{G}\mathrm{P}5$. The first-stage positive feedback latch structure accelerates the pull-down and pull-up speed of the nodes ${\mathrm{X}}_1$ and ${\mathrm{X}}_2$. At this point, ${\mathrm{M}}_{\mathrm{N}11}$ starts to turn off and ${\mathrm{M}}_{\mathrm{N}12}$ starts to turn on, leading to an $LV\_N=VNEG$. When nodes ${\mathrm{X}}_1$ and ${\mathrm{X}}_2$ are not fully latched yet, the second-stage positive feedback structure concurrently prompts ${\mathrm{M}}_{\mathrm{P}9}$ to turn off and ${\mathrm{M}}_{\mathrm{P}8}$ to turn on, accelerating the speed at which $\mathrm{L}\mathrm{V}\_\mathrm{N}$ is pulled down to output $\mathrm{V}\mathrm{N}\mathrm{E}\mathrm{G}$. Similarly, it can be deduced that when the falling edge signal of $V_{in2}$ and $V_{pulse2}$ arrives, $\mathrm{L}\mathrm{V}\_\mathrm{N}$ outputs $\mathrm{V}\mathrm{N}\mathrm{E}\mathrm{G}\mathrm{P}5$. Due to space constraints, the detailed process is not further elaborated in this paper.

4. Post-Layout Simulation Results

Based on the $0.18 \mathsf{\mu }\mathrm{m}$ CMOS process, circuit and layout design for a Buck–Boost power management chip were conducted at $1.8 \mathrm{V}$ and $5\mathrm{V}$ power supplies, as illustrated in Figure 16. The overall layout area is $1125 \mathsf{\mu }\mathrm{m}\times 560 \mathsf{\mu }\mathrm{m}$, with the control and driver circuit layout area, excluding the power switch transistor, being approximately $670 \mathsf{\mu }\mathrm{m}\times 200 \mathsf{\mu }\mathrm{m}$. Due to the stringent matching requirements for circuit devices in this design, the co-centric matching design was applied to core circuit modules, including the bandgap reference, error amplifier, PWM comparator, current sampling ($\mathrm{S}\mathrm{a}\mathrm{m}\mathrm{p}\mathrm{l}\mathrm{e}\_\mathrm{I}$), and other modules. This ensures a consistent handling of parasitic effects introduced by the layout, thereby maintaining uniformity in the performance of the circuit.

After extracting parasitic parameters from the layout, an overall post-simulation of the circuit is conducted. A typical operating scenario for this Buck–Boost power management chip is defined as follows: $V_{IN}=5 \mathrm{V},V_{out}=-4 \mathrm{V},I_{out}=100 \mathrm{m}\mathrm{A}$. Figure 17a,b depict the simulation results for the chip’s operation under these conditions, illustrating the start-up results and the output voltage ripple results, respectively. Upon powering up $V_{IN}$, the time taken for the output to stabilize is approximately $1.5 \mathrm{m}\mathrm{s}$. The average output voltage of the switching power supply is around $-4.009 \mathrm{V}$, with an output voltage ripple measuring $1.5 \mathrm{m}\mathrm{V}$ and a ripple rate of $0.0375\mathrm{\%}$.

Table 1. Output voltage ripple (mV).

${\mathit{V}}_{\mathit{o}\mathit{u}\mathit{t}}$	100 mA	200 mA	300 mA	400 mA	500 mA
−1 V	0.90	1.45	2.34	3.23	4.05
−2 V	1.07	1.99	3.23	4.37	5.66
−3 V	1.38	2.75	4.37	5.89	7.30
−4 V	1.50	3.05	4.75	6.80	8.27
−5 V	3.43	6.09	9.49	12.86	15.98
−6 V	3.43	6.49	10.09	13.92	17.09

presents the output voltage ripple conditions within the range of output voltage from $-1 \mathrm{V}$ to $-6 \mathrm{V}$ and output current from $100 \mathrm{m}\mathrm{A}$ to $500 \mathrm{m}\mathrm{A}$. It can be observed that the output voltage ripple remains below $20 \mathrm{m}\mathrm{V}$ across the entire range, with a maximum value of $17.09 \mathrm{m}\mathrm{V}$ and a minimum value of $0.9 \mathrm{m}\mathrm{V}$.

Linear regulation (LNR) is a crucial metric for assessing the capability of the output voltage to resist interference from input signals. A smaller overshoot voltage reflected at the output when the input voltage changes indicates a lower load regulation rate, demonstrating stronger immunity to interference for the switching power supply. When the output voltage is $-6 \mathrm{V}$, set the initial value of the input voltage to $5 \mathrm{V}$, make it jump to $4 \mathrm{V}$, and then, once the output voltage stabilizes, jump back to $5 \mathrm{V}$. The simulation results for the linear regulation are shown in Figure 18.

In Figure 18, with a $1 \mathrm{V}$ step change in the input voltage and constant output linear current, the overshoot voltage and undershoot voltage of $V_{out}$ are $10.29 \mathrm{m}\mathrm{V}$ and $10.57 \mathrm{m}\mathrm{V}$, respectively. The linear regulation is

$$LNR=\frac{∆V_{out}}{∆V_{IN}·V_{out}}=0.167\%$$

(17)

Load regulation (LDR) refers to the system’s ability to maintain a stable output voltage when the load changes.

Table 2. Overshoot voltages caused by load changes (mV).

${\mathit{V}}_{\mathit{o}\mathit{u}\mathit{t}}$	100 mA → 200 mA	200 mA → 300 mA	300 mA → 400 mA	400 mA → 500 mA
−1 V	8.21	10.56	12.89	11.76
−2 V	8.01	8.85	11.19	13.90
−3 V	8.99	11.21	14.27	13.74
−4 V	11.66	13.67	15.49	17.16
−5 V	17.21	22.49	21.73	24.58
−6 V	23.63	23.02	26.52	29.17

presents the overshoot conditions of $V_{out}$ when there is a step change in the output load current from $100 \mathrm{m}\mathrm{A}$ to $500 \mathrm{m}\mathrm{A}$, with the output voltage ranging from $-1 \mathrm{V}$ to $-6 \mathrm{V}$. It can be observed that the output overshoot does not exceed $30 \mathrm{m}\mathrm{V}$ across the entire range, and the overshoot voltage tends to be smaller as the output voltage decreases.

For a DC-DC converter, conversion efficiency is one of the most crucial design metrics. The formula for conversion efficiency is

$$\eta =\frac{V_{out}\times I_{out}}{V_{IN}\times I_{IN}}$$

(18)

After calculation, the conversion efficiency of the DC-DC converter designed in this paper, within the range of output voltage from $-1 \mathrm{V}$ to $-6 \mathrm{V}$ and output load current from $100 \mathrm{m}\mathrm{A}$ to $500 \mathrm{m}\mathrm{A}$, is plotted as a line chart in Figure 19 using Origin.

To validate the performance and robustness of the proposed design, Monte Carlo simulations and PVT simulations were conducted. Under the maximum output loading condition, that is, with an output voltage of $-6 \mathrm{V}$ and an output current of $500 \mathrm{m}\mathrm{A}$, the Monte Carlo pre-layout simulation results are illustrated in Figure 20 and Figure 21. The PVT post-layout simulation results under typical operating conditions are shown in Figure 22.

Finally,

Table 3. Performance summary and comparison.

	[20]	[21]	[22]	[23]	This Work
Process	$0.35 \mathsf{\mu }\mathrm{m}$ BCD	—	$0.18 \mathsf{\mu }\mathrm{m}$ BCD	—	$0.18 \mathsf{\mu }\mathrm{m}$ CMOS
Scheme	MPLT	Constant off-time	PWM + Voltage Mode	PFM + Peak-Current Mode	PWM + Peak-Current Mode
Input Voltage (V)	3.7	3	4	3.3	5
Inductor $\left(\mathsf{\mu }\mathrm{H}\right)$	10	4.7	1	6.8	4.7
$\mathrm{Output} \mathrm{Capacitor} (\mathsf{\mu }\mathrm{H}$)	4.7	20	10	44	20
Switching Frequency (MHz)	1	1.7	1	>0.5	2
Maximum Efficiency (%)	90.5	>90	87.5	75	85.82
Typical Output Voltage (V)	−4.9	−4	−7.5	−5	−4
Output Ripple (mV)	25@140 mA	12@100 mA	44@250 mA	11@70 mA	1.5@100 mA
Load Regulation (mV/mA)	0.74	1.6	0.5	0.58	0.08

provides a comparison of key reference metrics between this design and the other relevant literature. It is evident that the negative voltage DC-DC converter designed in this paper for AMOLED microdisplay driver circuits exhibits lower output voltage ripple and maintains stable output capability and good conversion efficiency across the entire operating range when compare to the other literature references.

5. Conclusions

• This paper addresses the design of a Buck–Boost converter for high-resolution microdisplay driver circuits, featuring a wide output voltage range, low output voltage ripple, and robust load-bearing capacity. Employing a dual-loop control mode for voltage and current, the converter combines peak current sampling control technology with pulse width modulation control mode. The proposed peak current sampling circuit, which integrates overcurrent protection functionality, achieves high-precision sampling of the power switch transistor, effectively reducing output voltage ripple and improving line regulation.
• The adaptive driving scheme proposed based on the $0.18 \mathsf{\mu }\mathrm{m}$ CMOS process effectively addresses the issue of driving power switches in a synchronous rectification Buck–Boost structure, particularly within a wide output voltage range. The proposed level-down circuit utilizes a two-stage positive feedback latch structure to efficiently accelerate the flipping speed of the output level, enhancing the driving capability.
• Post-layout simulation results indicate that the proposed Buck–Boost converter in this paper can deliver stable and low-ripple output voltage across the entire operating range. It demonstrates adaptability to various scenarios, making it versatile and providing a new solution for the power management aspect of AMOLED microdisplay driver systems.
• For convenience in understanding this paper, Abbreviations summarizes the abbreviations and other symbols mentioned, along with their corresponding explanations.