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Peer-Review Record

Approaches to Extend FPGA Reverse-Engineering Technology from ISE to Vivado

Electronics 2024, 13(6), 1100; https://doi.org/10.3390/electronics13061100
by Soyeon Choi and Hoyoung Yoo *
Reviewer 1:
Reviewer 2: Anonymous
Reviewer 3: Anonymous
Electronics 2024, 13(6), 1100; https://doi.org/10.3390/electronics13061100
Submission received: 6 February 2024 / Revised: 4 March 2024 / Accepted: 14 March 2024 / Published: 16 March 2024
(This article belongs to the Section Semiconductor Devices)

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

This paper proposes a method to generate XDLRC and XDL files in Vivado, similar to those in ISE, allowing for the extension of reverse engineering technology to cover the latest FPGAs supported by Vivado. The experimental results show that the XDLRC and XDL generated in Vivado respectively match 99% and 75% with those generated in ISE for Artix-7 100T. The method for generating textual netlists in both ISE and Vivado ensures that the programmable point information is the same in both tools, enabling the application of existing reverse engineering tools to devices supported by Vivado. The paper emphasizes the importance of security measures and highlights the risk associated with malicious attacks, rather than encouraging bitstream attacks through reverse engineering. However, the following points need to be addressed:

1. What is the significance of XDLRC and XDL files in reverse engineering?

2. What are the differences in XDLRC and XDL generated in ISE and Vivado?

3. How can existing reverse engineering tools be applied to devices supported by Vivado?

4. If possible, in the introduction section, the authors could have been clearer about the importance of SRAM-based FPGAs and the safety hazards that exist in order to better draw out the motivation and objectives of the research.

5. The scope of the literature review could have been a bit broader to include more research results on FPGA reverse engineering and security.

6. If possible, the description of the methodology could be more detailed, including specific steps and algorithms.

7. If possible, the authors should provide a more in-depth analysis and explanation of the results, including an exploration of the reasons for the low level of matching, and suggest possibilities for improvement.

8. If possible, the authors should suggest more specific and feasible research directions in the outlook section, such as further improving the methodology, expanding the experimental scope, or exploring other reverse engineering techniques.

Therefore, by considering the previous notes, in the opinion of the reviewer, this paper can be accepted for publication after further revision.

Author Response

Please see the attachment

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The topic of the present paper is interesting. However, there is an ethical  concern on the approach. The topic of the paper is essentially a reverse engineering of commercial FPGA design tools. I think the authors should present the evidence that this approach is not against the license terms of the tools.

Author Response

Please see the attachment

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

Dear authors,

Thank you for this interesting paper. I have some questions and some comments.

-My understanding from the references is that the XDLRC and XDL files are used to understand how the bitstream is generated and then be able to do reverse engineering from a new bitstream? Is that correct? I don't think this is clear in section 3.

Comments:

- Revise lines 18-19, it is hard to understand

- Revise all the acronyms. E.g. it should be FPGA  (Field Programmable Gate Array).

- Table 1 is not relevant for this study. I would remove it.

- Review the text, in L85 conn should be in italic, L101 ";map'" should be map in italic, etc

- Section 3.2 and 3.4: the title is not accurate since it is understood that Vivado can generate XDL and XDLRC files. Maybe it is better "through Vivado TCL commands"

-L196. bel -> BEL

- Captions of Figure 12 and 14: Please add here the color code too.

- Remove lines 337-339

Comments on the Quality of English Language

It is a bit difficult to follow some parts of the text. I would recommend to revise deeply the Quality of English.

Author Response

Please see the attachment

Author Response File: Author Response.pdf

Round 2

Reviewer 3 Report

Comments and Suggestions for Authors

I am satisfied with the new version. Thanks.

Comments on the Quality of English Language

No additional comments about the English. Thanks.

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