Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

Abstract

In this paper, a new negative lossless grounded capacitance multiplier (GCM) circuit based on a Current Feedback Operational Amplifier (CFOA) is presented. The proposed circuit includes a single CFOA, four resistors, and a grounded capacitor. In order to reduce the power consumption, the internal structure of the CFOA is realized with dynamic threshold-voltage MOSFET (DTMOS) transistors. The effects of parasitic components on the operating frequency range of the proposed circuit are investigated. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The functionality of the circuit is provided by the capacitance cancellation circuit. PVT (Process, Voltage, Temperature) analyses were performed to verify the robustness of the proposed circuit. An experimental study is provided to verify the operability of the proposed negative lossless GCM using commercially available integrated circuits (ICs).

1. Introduction

High-value capacitors in IC technology require a large silicon area. To address this issue, capacitance multiplier (CM) circuits capable of multiplying capacitance have been proposed to obtain large capacitance from small capacitance values. Therefore, CM circuits play an essential role in obtaining high-value capacitances.

CM circuits can be classified as grounded [1,2,3,4,5,6,7,8] and floating [9,10,11,12,13,14,15,16,17,18] according to the type of the simulated capacitance, and positive [1,2,3,4,5,6,7] and negative [19,20,21,22,23,24,25,26,27,28] according to the value of the simulated capacitance.

A literature survey reveals that there are various CM circuits are reported using numerous versatile active building blocks (ABBs). However, upon careful examination of the circuit configurations published in the literature, they are considered to suffer from some of the limitations given below.

• The circuits implemented with two or more active and passive elements have higher power consumption and a larger area on the chip.
• They are practically not applicable with commercially available ICs.
• The multiplication factor is not electronically adjustable.

Four negative CFOA-based CM circuit topologies have been proposed by Lahiri and Gupta [19]. While the first two proposed circuits contain two CFOAs, the other circuits consist of a single CFOA. All circuits are designed using two resistors and a single capacitor. Additionally, the circuits do not require any critical component matching conditions. All of the circuits in SPICE have been tested using the AD844 macro model. A capacitance cancellation circuit and a quadratic oscillator circuit are given as application examples. The resistance-controlled negative capacitance multiplier circuit presented by Abuelma’atti and Dhar consists of two CFOAs, two floating resistors, and a floating capacitor [20]. The negative CM circuit proposed by Dogan and Yuce includes a single CFOA, three resistors, and a capacitor [21]. The circuit proposed by Al-Absi and Abuelma’atti includes one CFOA and two OTAs. It is configured as an OTA-negative resistor to achieve an adjustable negative impedance multiplier [22]. The resistor-free circuit presented by Stornelli et al. consists of an E-VCII- and a capacitor [23].

Many of the negative CMs available in the literature contain two or more ABBs [19,20,22,24,25,27,28]. There are also circuits that contain only one active device [19,21,23,26,29,30,31]. When designing negative CMs, excessive use of active and passive elements should be avoided as this will increase power consumption. Negative CMs presented by researchers have generally been realized through the use of three or more passive elements [19,20,21,24,25,28,30,31]. Negative CMs containing a single capacitor have also been proposed, but each of these circuits operates with two or more active components [22,27].

The aim of this work was to design a negative lossless GCM circuit using currently commercially available ICs, namely the AD844 [32]. The proposed circuit is designed with a single CFOA, four resistors and a grounded capacitor. The internal structure of the CFOA is built with DTMOS transistors to reduce power consumption. The total power consumption of the circuit is 1.6 mW. The non-ideal analysis for the proposed circuit has been investigated in detail. A capacitance cancellation circuit is presented as an application example. To verify the operability of the proposed circuit, it has been experimentally tested using commercially available ICs, namely AD844s.

The paper is structured as follows: Section 2 introduces the proposed circuit utilizing a CFOA. The non-ideal analysis is given in Section 3. SPICE simulation results and discussions are given in Section 4. An application example is presented in Section 5. Finally, Section 6 concludes the paper.

2. The Proposed Circuit

The terminal relations of CFOAs, whose circuit symbol and equivalent circuit are given in Figure 1 and Figure 2, respectively, can be represented in the following matrix equation:

$$\left[\begin{array}{c}{I}_Y\\ \begin{array}{c}{I}_Z\\ V_X\\ V_W\end{array}\end{array}\right]=\left[\begin{array}{cccc}0& 0& 0& 0\\ \alpha \left(s\right)& 0& 0& 0\\ 0& \beta \left(s\right)& 0& 0\\ 0& 0& \eta \left(s\right)& 0\end{array}\right]\left[\begin{array}{c}{I}_X\\ V_Y\\ \begin{array}{c}{V}_Z\\ I_W\end{array}\end{array}\right]$$

(1)

where α(s) represents the current gain which is ideally equal to unity. Also, the β(s) and η(s) correspond to voltage gains and ideally both of them are equal to unity. Furthermore, α(s), β(s), and η(s) can be given by

$$\alpha \left(s\right)=\frac{{\omega }_{\alpha }\left(1-{\epsilon }_{\alpha }\right)}{s+{\omega }_{\alpha }}$$

(2)

$$\beta \left(s\right)=\frac{{\omega }_{\beta }\left(1-{\epsilon }_{\beta }\right)}{s+{\omega }_{\beta }}$$

(3)

$$\eta \left(s\right)=\frac{{\omega }_{\eta }\left(1-{\epsilon }_{\eta }\right)}{s+{\omega }_{\eta }}$$

(4)

Herein, ${\epsilon }_{\alpha }$ represents the current-tracking error, ideally equal to zero, while ${\epsilon }_{\beta }$ and ${\epsilon }_{\eta }$ denote the voltage tracking errors, also ideally equal to zero. It is assumed that $\left|{\epsilon }_{\alpha }\right|$, $\left|{\epsilon }_{\beta }\right|$, and $\left|{\epsilon }_{\eta }\right|$ are significantly smaller than one.

In addition, ${\omega }_{\alpha }$, ${\omega }_{\beta }$, and ${\omega }_{\eta }$ denote corner frequencies of the relevant parameter. Furthermore, in an ideal case, R_in is infinity and the port relationships of the CFOA are expressed by the following equations: V_X = V_Y, I_Y = 0, I_Z = I_X, and V_W = V_Z.

The proposed negative lossless GCM is depicted in Figure 3. Without passive element matching conditions, the input admittance (Y_in) of the circuit is obtained as follows:

$$Y_{in}\left(s\right)=\frac{I_{in}}{V_{in}}=-\frac{\left(R_3+R_4\right)\left(R_2-R_1+sC{R}_1{R}_2\right)}{R_1{R}_3\left(R_2+R_4\right)}$$

(5)

If R₂ = R₁ is selected for the circuit in Figure 3, the input admittance is simplified as follows. When this condition is met, the circuit can simulate negative lossless GCM. The equivalent capacitance (C_eq) and the multiplication factor (K) are given by

$$Y_{in}\left(s\right)=\frac{I_{in}}{V_{in}}=s{C}_{eq}=sCK=sC\left[-\frac{R_1\left(R_3+R_4\right)}{R_3\left(R_1+R_4\right)}\right]$$

(6)

$$C_{eq}=CK=C\left[-\frac{R_1\left(R_3+R_4\right)}{R_3\left(R_1+R_4\right)}\right]$$

(7)

$$K=-\frac{R_1\left(R_3+R_4\right)}{R_3\left(R_1+R_4\right)}$$

(8)

As can be seen from Equation (8), if one of the resistors R₃ or R₄ is replaced with an MOS-based voltage-controlled resistor, the multiplication factor becomes electronically controllable.

The sensitivity of the K with respect to the tuning resistors is given below.

$$S_{R_1}^K=\frac{R_4}{R_1+R_4}$$

(9)

$$S_{R_3}^K=-\frac{R_4}{R_3+R_4}$$

(10)

$$S_{R_4}^K=\frac{R_4\left(R_1-R_3\right)}{\left(R_1+R_4\right)\left(R_3+R_4\right)}$$

(11)

3. Non-Ideal Analysis

The non-ideal equivalent circuit of a CFOA is shown in Figure 4. Here, R_X, R_Z, and R_W indicate parasitic resistors. Also, C_Y and C_Z demonstrate the parasitic capacitors. Ideally, these parasitic elements are R_X = R_W = C_Z = C_Y = 0 and R_Z = ꝏ. The terminal relations of the CFOA in non-ideal conditions are given in Equation (12).

$$\left[\begin{array}{c}{I}_Y\\ \begin{array}{c}{I}_Z\\ V_X\\ V_W\end{array}\end{array}\right]=\left[\begin{array}{cccc}0& s{C}_Y& 0& 0\\ \alpha \left(s\right)& 0& s{C}_Z+{1/R}_Z& 0\\ R_X& \beta \left(s\right)& 0& 0\\ 0& 0& \eta \left(s\right)& R_W\end{array}\right]\left[\begin{array}{c}{I}_X\\ V_Y\\ \begin{array}{c}{V}_Z\\ I_W\end{array}\end{array}\right]$$

(12)

Taking into account the effects of the non-ideal gains of the CFOA, the input admittance of the circuit is obtained as follows.

$$Y_{in}\left(s\right)=\frac{R_3\left(1-\alpha \beta \right)+R_4\left(1-\alpha \beta \eta \right)+R_1\left(1-\eta \right)-\alpha \beta R_1\left(R_3+\eta R_4\right)sC}{R_3\left(R_1+R_4\right)}$$

(13)

Considering the non-ideal gains of the CFOA, the equivalent circuit of the proposed circuit is given in Figure 5; the values of the equivalent components are given in Equations (14)–(16).

$$R_{eq}=\frac{R_3\left(R_1+R_4\right)}{R_3\left(1-\alpha \beta \right)+R_4\left(1-\alpha \beta \eta \right)+R_1\left(1-\eta \right)}$$

(14)

$$C_{eq}=CK=-\frac{\alpha \beta R_1\left(R_3+\eta R_4\right)}{R_3\left(R_1+R_4\right)}C$$

(15)

$$K=-\frac{\alpha \beta R_1\left(R_3+\eta R_4\right)}{R_3\left(R_1+R_4\right)}$$

(16)

The sensitivity analysis is given below.

$$S_{\alpha }^K=S_{\beta }^K=1$$

(17)

$$S_{\eta }^K=\frac{\eta R_4}{\left(R_3+{\eta R}_4\right)}$$

(18)

$$S_{R_1}^K=\frac{R_4}{R_1+R_4}$$

(19)

$$S_{R_3}^K=-\frac{\eta R_4}{\left(R_3+{\eta R}_4\right)}$$

(20)

$$S_{R_4}^K=-\frac{R_4\left(R_3-\eta R_1\right)}{\left(R_1+R_4\right)\left(R_3+\eta R_4\right)}$$

(21)

Under the specified condition where only the parasitic impedances of the X, Y, Z, and W terminals are considered, the input admittance is derived in the form presented in Equation (22).

$$Y_{in}\left(s\right)=\frac{a_0+a_{1}s+a_2{s}^2}{b_0+b_{1}s+b_2{s}^2}$$

(22)

In this context, a_i and b_i represent the real coefficients of the driving point admittance Y_in(s).

$$a_0=\left(\left(R_3+R_W\right)+R_4\right)\left[R_1+R_X-\left(R_1\parallel R_Z\right)\right]$$

(23)

$$a_1=R_4\left(R_3+R_W\right)\left[C{R}_1\left(R_X-\left(R_1\parallel R_Z\right)\right)+C_Z\left(R_1+R_X\right)\right]$$

(24)

$$a_2=C{C}_Z{R}_1{R}_X\left(R_1\parallel R_Z\right)\left(\left(R_3+R_W\right)+R_4\right)$$

(25)

$$b_0=\left(R_1+R_X\right)\left(R_3+R_W\right)\left(R_4+\left(R_1\parallel R_Z\right)\right)$$

(26)

$$b_1=\left[C{R}_1{R}_X\left(R_3+R_W\right)\left(R_4+\left(R_1\parallel R_Z\right)\right)+C_Z{R}_4\left(R_3+R_W\right)\left(R_1\parallel R_Z\right)\left(R_1+R_X\right)\right]$$

(27)

$$b_2=C{C}_Z{R}_1{R}_4{R}_X\left(R_3+R_W\right)\left(R_1\parallel R_Z\right)$$

(28)

In the ideal case, the input admittance of the capacitor is of the form Y_in(s) = a₁s/b₀. To obtain a lossless capacitor, the terms other than a₁s and b₀ need to be small enough. In other terms, when s is substituted with jω, the following inequalities must be concurrently fulfilled to approximate the ideal capacitor admittance:

$$\left|a_0\right|\ll \left|a_1\times \left(j\omega \right)\right|\Rightarrow f\gg f_L=\frac{1}{2\pi }\left(\frac{a_0}{a_1}\right)$$

(29)

$$\left|a_2\times {\left(j\omega \right)}^2\right|\ll \left|a_1\times \left(j\omega \right)\right|\Rightarrow f\ll f_{H1}=\frac{1}{2\pi }\left(\frac{a_1}{a_2}\right)$$

(30)

$$\left|b_1\times \left(j\omega \right)\right|\ll \left|b_0\right|\Rightarrow f\ll f_{H2}=\frac{1}{2\pi }\left(\frac{b_0}{b_1}\right)$$

(31)

$$\left|b_2\times {\left(j\omega \right)}^2\right|\ll \left|b_0\right|\Rightarrow f\ll f_{H3}=\frac{1}{2\pi }\sqrt{\frac{b_0}{b_2}}$$

(32)

According to the inequalities given above, the operating frequency range of the proposed circuit is calculated approximately as follows.

$$f\gg f_L=\frac{1}{2\pi }\left(\frac{a_0}{a_1}\right)$$

(33)

$$f\ll f_H=\frac{1}{2\pi }min\left\{\frac{a_1}{a_2},\frac{b_0}{b_1},\sqrt{\frac{b_0}{b_2}} \right\}$$

(34)

4. Simulation Results

In order to reduce the power consumption of analog integrated circuits, operations with lower supply voltages can be provided by DTMOS technology [33,34,35,36,37]. To obtain a DTMOS transistor, the body and gate terminals of the MOSFET are short-circuited as shown in Figure 6. The DTMOS-based implementation of the CFOA, derived from the CCII+ presented in reference [38], is depicted in Figure 7.

The simulation results have been obtained utilizing the SPICE program, employing 0.13 µm IBM CMOS technology parameters. The power supply and bias voltage were chosen as V_DD = −V_SS = 0.6 V and V_B = −0.2 V, respectively. The transistor dimensions are detailed in

Table 1. The transistor dimensions.

Transistors	W (μm)/L (μm)
M1–M13	130/0.65
M14, M15, M20–M23, M25, M26, M28	13/0.65
M24, M27	26/0.65
M16–M19	15.6/0.26

. The parasitic impedances and non-ideal gains of the CFOA are delineated in

Table 2. Parasitic impedances and non-ideal gains of the CFOA.

Parasitic Impedances	Values
RX	0.637 Ω
RW	0.637 Ω
RZ	20.04 kΩ
CZ	66 fF
CY	8.23 fF
α	0.999972
β	1.000009
η	1.000009

.

The functionality of the proposed negative GCM was examined under the following simulation conditions. Detailed simulation settings are included in Table 3.

(i)

Multiplication factor (K) is constant while C is variable;

(ii)

C is constant while K is variable.

Table 3. Detailed simulation results and passive component settings.

Case	Passive Components					K	Ceq (nF)	Frequency Response
	C (nF)	R1 (kΩ)	R2 (kΩ)	R3 (Ω)	R4 (kΩ)			Magnitude within 10% Error	Phase within 10° Error
1	0.1	10	10	100	1	−10	−1	4 Hz to 80 MHz	14 Hz to 53 MHz
		10	10	100	10	−50.5	−5.05	9 Hz to 35 MHz	52 Hz to 47 MHz
		10	10	10	10	−500.5	50.05	9 Hz to 32 MHz	53 Hz to 11 MHz
2	0.5	10	10	100	1	−10	−5	1 Hz to 52 MHz	3 Hz to 30 MHz
	5						−50	1 Hz to 20 MHz	1 Hz to 15 MHz
	50						−500	1 Hz to 4.5 MHz	1 Hz to 4.5 MHz

Table 3. Detailed simulation results and passive component settings.

Case	Passive Components					K	Ceq (nF)	Frequency Response
	C (nF)	R1 (kΩ)	R2 (kΩ)	R3 (Ω)	R4 (kΩ)			Magnitude within 10% Error	Phase within 10° Error
1	0.1	10	10	100	1	−10	−1	4 Hz to 80 MHz	14 Hz to 53 MHz
		10	10	100	10	−50.5	−5.05	9 Hz to 35 MHz	52 Hz to 47 MHz
		10	10	10	10	−500.5	50.05	9 Hz to 32 MHz	53 Hz to 11 MHz
2	0.5	10	10	100	1	−10	−5	1 Hz to 52 MHz	3 Hz to 30 MHz
	5						−50	1 Hz to 20 MHz	1 Hz to 15 MHz
	50						−500	1 Hz to 4.5 MHz	1 Hz to 4.5 MHz

The frequency response of the input impedance of the proposed negative lossless GCM is given in Figure 8 for various multiplication factors (K). By selecting the passive elements as $C=100 \mathrm{pF}$, $R_1=R_2=10 \mathrm{k}\mathsf{\Omega }$, $R_3^1=R_3^2=100 \mathsf{\Omega }$, $R_3^3=10 \mathsf{\Omega }$, $R_4^1=1 \mathrm{k}\mathsf{\Omega }$, and $R_4^2=R_4^3=10 \mathrm{k}\mathsf{\Omega }$, the multiplication factors are set to $K_1=-10$, $K_2=-50.5$, and $K_3=-500.5$, resulting in C_eq = −1 nF, −5.05 nF, and −50.05 nF, respectively. In Figure 9, a comparison of the proposed negative GCM with the ideal capacitor for C_eq = 5, 50, and 500 nF is given by selecting K = 10, C = 0.5, 5, and 50 nF, respectively. The frequency responses of the proposed circuit to various supply voltages are shown in Figure 10. Monte Carlo (MC) simulations were conducted for 100 runs. The simulation results for a 10% change in the threshold voltages and gate oxide thicknesses of all MOS transistors and a 5% change in the width of all MOS transistors are shown in Figure 11 and Figure 12, respectively. A temperature analysis of the circuit is also depicted in Figure 13.

A table of comparisons of previously reported negative CM circuits using various ABBs can be seen in

Table 4. Comparison of negative CM circuit.

References	# and Type of ABB	# of Resistors		# of Capacitors		Electronic Tuning	Multiplication n Factor	Matching Condition	Technology	Operation Frequency	Power Dissipation
		F	G	F	G
[19] in Figure 2	2 CFOA	0	2	0	1	No	0.5	No	0.35 µm	NA	NA
[19] in Figure 3	2 CFOA	0	2	0	1	No	0.5	No	0.35 µm	NA	NA
[19] in Figure 4	1 CFOA	1	1	1	0	No	0.5	No	0.35 µm	1 kHz to 5 MHz	NA
[19] in Figure 5	1 CFOA	2	0	0	1	No	0.5	No	0.35 µm	NA	NA
[20] in Figure 1d	2 CFOA	2	0	1	0	No	NA	No	AD844	NA	NA
[21] in Figure 8	1 CFOA	1	2	0	1	No	NA	Yes	0.13 µm	NA	NA
[22] in Figure 11	1 CFOA, 2 OTA	0	0	0	1	Yes	NA	No	AD844, LM13700N	2 Hz to 7 MHz	NA
[23] in Figure 1b	1 EVCII−	0	0	1	0	Yes	100	No	0.18 µm	80 Hz to 40 kHz	67 nW
[24] in Figure 4	2 VCII+	1	1	1	0	No	50	No	0.35 µm	10 MHz	1.5 mW
[25] in Figure 6	2 CFTA	0	2	1	0	Yes	20.3	No	0.13 µm	10 kHz to 100 MHz	NA
[25] in Figure 7	2 CFTA	0	2	1	0	Yes	20.3	No	0.13 µm	10 kHz to 100 MHz	NA
[26] in Figure 7	1 CFTA	0	1	1	0	Yes	10	No	0.18 µm	280 Hz to 4.15 MHz	NA
[27] in Figure 2	1 VCII ±, 1 E-DVCC	0	0	0	1	Yes	25.4	No	0.18 µm	10 kHz to 1 MHz	3.184 mW
[28] in Figure 2	1 OTRA, 1 VF	3	0	1	0	Yes	99	Yes	0.18 µm	100 Hz to 1 MHz	NA
[29] in Figure 1	1 VDTA	0	1	1	0	Yes	20	No	0.18 μm	100 Hz to 100 MHz	0.89 mW
[30] in Figure 1	1 CFOA	3	0	1	0	No	26	No	AD844	1 kHz to 100 kHz	NA
[31] in Figure 2a	1 CFOA	2	0	0	1	No	2001	No	AD844	4 kHz to 1 MHz	NA
[31] in Figure 2b	1 CFOA	2	0	0	1	Yes	201	No	AD844	4 kHz to 1 MHz	NA
[31] in Figure 2c	1 CFOA	2	0	0	1	No	400	No	AD844	4 kHz to 1 MHz	NA
Proposed	1 CFOA	2	2	0	1	Yes	500.5	Yes	0.13 µm	8 Hz to 80 MHz	1.6 mW

Abbreviations: ABB: active building block; CFOA: current feedback operational amplifier; CFTA: current follower transconductance amplifier; E-DVCC: electronically tunable differential voltage current conveyor; F: floating; G: grounded; NA: not available; OTA: operational transconductance amplifier; VCII: second generation voltage conveyor; VF: voltage follower.

. The proposed circuit contains a single CFOA. Compared to other circuits implemented with a single active component, the number of passive elements is relatively high. However, to reduce power consumption, the internal structure of the CFOA is designed using the DTMOS technique. Power consumption can be reduced by using MOS-based resistors. The multiplication factor of the circuit can be adjusted up to 500. In addition, according to Figure 8, the operating frequency reaches 80 MHz. Considering its simplicity, operating frequency, and multiplication factor, it is clear that the proposed circuit is superior to the circuits in the literature.

5. Application Example

This section presents an application example to demonstrate the robustness and workability of the proposed GCM. The application example shown in Figure 14 is the capacitive cancellation circuit in which the parasitic capacitors in the output circuits are eliminated. Here, the negative capacitor (C_eq) is obtained with the proposed negative lossless GCM. The resistance currents $I_{R_a}$ and $I_{R_b}$ in the circuit are given below. If the condition $C_{eq}=-C_c$ is satisfied, $I_{R_a}$ and $I_{R_b}$ will be equal.

$$I_{R_a}=\frac{1+s\left(C_c+C_{eq}\right)R_b}{R_a+R_b+s\left(C_c+C_{eq}\right){R_{a}R}_b}{V}_s$$

(35)

$$I_{R_b}=\frac{1}{R_a+R_b+s\left(C_c+C_{eq}\right){R_{a}R}_b}{V}_s$$

(36)

The simulation result was obtained by choosing $R_a=R_b=1 \mathrm{k}\mathsf{\Omega }$ and $C_c=0.5 \mathrm{nF}$. The proposed negative GCM is designed to have $C_{eq}=-0.5 \mathrm{nF}$ in the circuit by choosing $K=10$ and $C=50 \mathrm{pF}$. The frequency performance of the capacitance cancellation circuit, for the output current $I_{R_b}$, is given in Figure 15. According to the results, the circuit is compatible with ideal results up to 10 MHz.

A sinusoidal waveform of 300 mV amplitude and 100 kHz frequency was applied to the input of the circuit. Waveforms of $I_{R_a}$ and $I_{R_b}$ currents are given in Figure 16. The current waveforms have the same amplitude and phase, indicating that the parasitic capacitance is eliminated in the proposed circuit.

6. Experimental Study

An experimental setup has been designed with the commercially available AD844 ICs to verify the operation of the proposed negative lossless GCM. The capacitance cancellation circuit is shown in Figure 17. Supply voltages of ±15 V were selected. The experimental results have been obtained out by selecting R_a = R_b = 1 kΩ and C_c = 1 nF. By choosing the passive components of the proposed GCM to eliminate the parasitic capacitor, C_c = 1 nF, R₁ = 10 kΩ, R₂ = 10 kΩ, R₃ = 100 Ω, R₄ = 1 kΩ and C = 100 pF, K = −10 and C_eq = −1 nF were obtained. A sinusoidal input voltage (V_x) with an amplitude of 2 V at frequencies of 1 kHz, 10 kHz and 100 kHz was applied to the input of the circuit. The input voltage (V_x) and the voltage waveforms of the compensated capacitor (V_y) are shown in Figure 18, Figure 19 and Figure 20. According to the test results, it can be seen that the voltages V_x and V_y are approximately in the same phase. The phase difference between the voltages was measured as 2.2° at most. As a result, the effect of the parasitic capacitor C_c is compensated for by the proposed GCM. Since the resistances R_a and R_b are chosen to be equal, the circuit works as a voltage divider and the voltage V_y is approximately half of the voltage V_x.

7. Conclusions

In this study, a new circuit configuration was introduced to realize the negative lossless GCM. The proposed circuit contains a single CFOA, four resistors, and a grounded capacitor. A detailed analysis of the circuit has been carried out. The factors affecting the frequency range have been investigated through mathematical analyses. In order to reduce the power consumption of the circuit, a CFOA was obtained by using DTMOS transistors. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The workability of the circuit has been shown by providing a capacitive cancellation circuit application and an experimental study.