A 0.4 V CMOS Current-Controlled Tunable Ring Oscillator for Low-Power IoT and Biomedical Applications

Abstract

This work presents a current-controlled CMOS ring oscillator (CCRO) optimized for ultra-low-voltage applications in next-generation energy-constrained systems. Leveraging bulk voltage tuning in 22 nm FDSOI differential inverter stages, the topology enables frequency adjustment while operating MOSFETs in the subthreshold region—critical for minimizing power in sub-1 V environments. Simulations at 0.4 V supply demonstrate robust performance: a three-stage oscillator achieves a 537–800 MHz tuning range with bias current (I_BIAS) modulation from 30–130 nA, while a four-stage configuration spans 388–587 MHz. At 70 nA I_BIAS, the three-stage design delivers a nominal frequency of 666.8 MHz with just 10.23 µW power dissipation, underscoring its suitability for ultra-low-power IoT and biomedical applications. The oscillator’s linear frequency sensitivity (2.63 MHz/nA) allows precise, dynamic control over performance–power tradeoffs. To address diverse application needs, the design integrates three tunability mechanisms: programmable capacitor arrays for coarse frequency adjustments, configurable stage counts (three- or four-stage topologies), and supply voltage scaling. This multi-modal approach extends the operational range to 1 MHz–1 GHz, ensuring compatibility with low-speed sensor interfaces and high-speed edge-computing tasks. The CCRO’s subthreshold operation at 0.4 V—coupled with nanoampere-level current consumption—makes it uniquely suited for battery-less systems, wearable health monitors, and implantable medical devices where energy efficiency and adaptive clocking are paramount. By eliminating traditional voltage-controlled oscillators’ complexity, this topology offers a compact, scalable solution for emerging ultra-low-power technologies.

1. Introduction

The rapid growth of the Internet of Things (IoT), wireless sensor networks, and energy-harvested microsystems continues to present significant challenges while driving demand for power-efficient analog and mixed-signal integrated circuit (IC) solutions using CMOS technology [1,2,3,4,5,6,7]. In such applications like implantable and wearable biomedical devices, body sensor networks, and other compact systems, controlled oscillators (COs) are essential due to their need for extremely low power consumption, low phase noise, minimal layout area, and wide frequency-tuning capability to accommodate process and temperature variations [7,8,9,10,11]. COs also play a vital role in analog-to-digital converters [12,13,14], time-to-digital converters [15,16,17], and phase-locked loops (PLLs), which serve as the time reference for control systems, RFID systems, clock generation, and other clock-dependent applications, including switching power converters and beyond [18,19,20,21,22].

CMOS-controlled oscillators (COs) are broadly classified into two main categories: LC tank oscillators and ring oscillators, where LC oscillators are preferred in applications demanding both high-quality factors (Q) and low-phase noise. However, their reliance on spiral inductors leads to large silicon area consumption and higher power consumption, making them unsuitable for ultra-low-power integrated circuits or applications where compact physical area is essential [23,24,25]. In contrast, ring oscillators (ROs) consisted of an odd number of typically identical delay stages connected in a loop, with the output of the last stage fed back to the input of the first. Due to their fully digital nature, ROs offer several advantages over LC oscillators, including smaller area, simpler design, better scalability with CMOS technology, and ease of integration. These properties make ROs well-suited for applications that prioritize low power and high integration, such as in wearable biomedical systems, IoT edge devices, and sensor nodes.

Based on the tuning mechanism, ring oscillators can be further classified as voltage-controlled or current-controlled. Controlled ring oscillator (CRO) designs offer additional benefits such as a wide frequency-tuning range, minimal power consumption, reduced design complexity, small layout area, and full compatibility with CMOS processes. While relaxation oscillators can achieve a wide tuning range but ring oscillators are notably more efficient in terms of power usage [26].

Several design strategies for low-power controlled oscillators (COs) have been studied in the literature to enhance the phase-noise and frequency-tuning range performance. One notable technique combines current-starving, commonly used in current-controlled oscillators, with a negatively skewed delay strategy to enhance the power-delay product, defined as the product of power consumption and the delay of a single gate [27]. Another approach involves a traditional voltage-controlled oscillator (VCO) enhanced with negative resistance, a multi-gate structure, and a bypass capacitor to reduce higher-order harmonics [28]. Additionally, a digital control circuit was designed to regulate the oscillation frequency [1]. An alternative design employs positive feedback to every stage, enabling operation with just two stages rather than three, which helps lower power consumption [29]. A delay cell for frequency tuning, composed of a PMOS and an NMOS transistor forming a transmission gate, has been utilized to adjust the oscillation frequency by modulating the gate voltage [30]. Finally, a dynamic threshold MOS (DTMOS) technique has been proposed to lower the Vth-threshold voltage of NMOS transistors in the delay cell, allowing for faster transitions and achieving a higher operating frequency [19].

The concept of controlling the ring oscillator (RO) frequency through the bulk terminal was explored, including the impact of bulk voltage fluctuations on phase-noise performance [31]. Additionally, an RO was integrated into an adaptive body-bias (ABB) generator for low-voltage CMOS VLSI circuits to facilitate delay characterization of CMOS gates [32]. However, most prior works do not explore body-biasing as a reliable current-controlled tuning method for sub-0.4 V operation, especially on differential architecture.

This work introduces a body-bias-controlled current-controlled ring oscillator (CCRO) that is optimized for ultra-low-power and ultra-low-voltage operation in 22 nm FDSOI technology. It was initially applied in the analog domain [33,34,35], including logic gates [36,37], and later adapted for setting the quiescent current in inverter stages [38] to design a current-controlled oscillator (CCO) that operates with low power and low voltage. The proposed design maintains a static output voltage at half the supply, while the bias current controls the oscillation frequency.

The effectiveness of body biasing also depends on the choice of forward or reverse biasing conditions, each impacting circuit performance differently. Forward biasing lowers the threshold voltage (Vth) and increases transconductance (g_m) for improved speed and efficiency [39]. In contrast, reverse biasing higher the threshold voltage (Vth), which reduces leakage but may introduce noise [39,40]. In noise-sensitive analog designs, forward biasing is often preferred [39,41,42]. Finally, employing a systematic body-biasing loop for delay control, the inverter stages achieve reliable cascading and eliminate input–output voltage transfer offsets. This approach significantly broadens the tuning range and enhances the robustness of RO against process, voltage, and temperature (PVT) variations. Moreover, the proposed CCRO demonstrates robust operation even at low supply voltages, comparable to the 0.4 V operation observed in 22 nm FDSOI technologies, thus ensuring energy-efficient performance. This also achieves favorable phase noise and a competitive figure of merit (FoM) compared to prior works, reinforcing its potential for low-power applications.

The manuscript is structured as follows: Section 2 provides a detailed description of the proposed body-bias-controlled current-controlled ring oscillator (CCRO) architecture, including its circuit-level implementation and design considerations. Section 3 presents comprehensive simulation results, including performance analysis under process, voltage, and temperature (PVT) variations, as well as phase noise, power consumption, and tuning characteristics. Finally, Section 4 concludes the paper by summarizing the key findings, highlighting the advantages of the proposed design, and outlining potential directions for future research.

2. Proposed Design

A ring oscillator consists of N inverter stages (delay stages) connected in a closed loop, producing square wave outputs. The oscillation frequency is determined by the number of inverter stages (N) and the delay time of each inverter (τ) following the relationship.

$$f_{osc}={\displaystyle \frac{1}{2N.\tau }}={\displaystyle \frac{I_D}{2N.C_i.∆V}}$$

(1)

where τ is the delay per stage, $C_i$ is the load capacitance at the output node, $∆V$ is the voltage swing (~$V_{DD}/2$), and $I_D$ is the current through each differential output node.

The delay of an inverter is influenced by its load capacitance and the biasing current. Consequently, adjusting the bias current allows for modification of the inverter delay, thereby altering the oscillation frequency.

The proposed current-controlled ring oscillator (CCRO), as shown in Figure 1, is designed with an N-stage ring oscillator. Each stage consists of a differential CMOS inverter with controllable bulk terminals. The advantage of the differential CMOS inverter is that it inherently relaxes the constraint of using an odd number of stages for designing a ring oscillator [43,44]. Unlike single-ended designs, differential ring oscillators can use an even number of stages with minimal changes in design [45,46,47].

Furthermore, to address the mismatch caused by the longer path between the first- and last-stage feedback, the delay cell can be arranged in a twisted configuration [15,48]. This problem especially happened when we required more delay cells (N-stage) in the design. Additionally, an output buffer is used to ensure balanced loading across delay cells and enhance output drive strength. While not shown in the schematic, it is highlighted in the layout.

To establish the typical oscillation frequency and mitigate sensitivity to parasitic effects, we include an output capacitor (C_i) at the output of each stage, as shown in Figure 1a. Further details of this design are discussed in the following section. The body bias voltages V_BP and V_BN for the transistors are produced using the auxiliary circuit shown in Figure 2 [38,49]. This auxiliary circuit maximizes the current in the reference inverter (M_B1-M_B2) when the input voltage reaches the logic threshold of V_DD/2. The reference inverter input is biased at V_DD/2 during quiescent operation, and this condition is mirrored at the output through the negative feedback provided by the error amplifier.

The quiescent current is controlled through the bulk terminals, where V_BP and V_BN are applied to the p-channel and n-channel transistors, respectively. These voltages are generated by amplifiers A₁ and A₂ using a method introduced in [33] and later adopted in [38].

The transistors M_B1 and M_B2 serve as reference devices, each with a V_GS value set to V_DD/2. Their quiescent drain current is maintained at I_BIAS through a local feedback loop controlled by the A₁ and A₂ auxiliary amplifiers, which provide the necessary bulk voltages V_BP and V_BN while applying the following conditions:

(a)

assigned aspect ratios of M_B1 and M_B2

(b)

I_D1,2 = kI_BIAS

(c)

V_SGR1= V_GSR2= V_DD/2

(d)

V_SDR1= V_DSR2= V_DD/2 [Assuming virtual ground]

The aspect ratios of M_B1 and M_B2 should be carefully selected to ensure that the bulk voltages remain within the V_DD/2 and ground limits. A precise layout is essential to reduce mirroring errors between the bias and reference branches. Any offset or mismatch in the error amplifiers (A₁ and A₂) could affect V_BN and V_BP, potentially leading to variations in the current flowing through the inverters. To mitigate this, careful layout techniques, such as common-centroid placement and symmetrical routing, are employed. Proper device sizing is also maintained to reduce mismatch sensitivity. This includes using similar channel lengths for all MOSFETs and choosing even-numbered multiplications for wider devices, which helps achieve better matching and a more compact layout. Auxiliary amplifiers A₁ and A₂ are required to deliver a rail-to-rail output, whereas the input common-mode range is non-critical due to the input voltage being fixed at V_DD/2. This allows the use of simple symmetrical operational transconductance amplifiers (OTAs) operating in the subthreshold region. A practical implementation of such an amplifier can be found in [38,50] and is shown in Figure 3.

The voltages V_BN and V_BP are supplied to the delay cells (inverters) forming the ring oscillator illustrated in Figure 1c,d. These voltages limit the maximum current flowing through the inverters to a specific value when the input voltage reaches the threshold. For example, the transistor M_N1 in the first inverter stage, shown in Figure 1a, operates under quiescent conditions where V_IN is maintained at V_DD/2. Under these conditions, M_B2 and M_N1 share the same source, gate, and bulk voltages, leading to M_N1’s drain current being directly mirrored from M_B2.

$$I_{D1,N1}={\displaystyle \frac{{(W/L)}_{N1}}{{(W/L)}_{MR2}}}{I}_{BIAS}$$

(2)

This equality is rigorously maintained due to the source-drain voltage of M_N1 being precisely biased at V_DD/2. The same principle applies to all the transistors within the ring oscillator. Essentially, both PMOS and NMOS devices have their currents regulated by I_BIAS through current–mirror relationships.

$$I_{D1,Pi}={\displaystyle \frac{{(W/L)}_{Pi}}{{(W/L)}_{MR1}}}{I}_{BIAS}$$

(3)

$$I_{D1,Ni}={\displaystyle \frac{{(W/L)}_{Ni}}{{(W/L)}_{MR2}}}{I}_{BIAS}$$

(4)

The aspect ratios of the respective p-type and n-type MOSFETs within the ROs are indicated by the terms (W/L)_Pi and (W/L)_Ni, where i = 1,2,…, N.

3. Simulation Results

The proposed design for the three-stage and four-stage current-controlled ring oscillators (CCROs) is implemented using 22 nm FDSOI technology and verified through schematic-level simulations. A regular threshold voltage Vth (RVT) device is used for the design to achieve symmetrical inverter behavior, balanced body effect coefficients, and uniform control bulk voltage ranges. The circuit is operated power supply of 0.4 V and a bias current of 70 nA. The operating temperature range, suitable for wearable and implantable devices, was set between 0 °C and 60 °C.

Table 1. Summary of design parameters employed in simulations.

Parameter	Value
VDD	0.4 V
IBIAS	70 # nA
(W/L)B1	960 nm/28 nm
(W/L)B2	200 nm/28 nm
A1, A2	33 dB
(W/L) Ni; Pi	500 nm/20 nm; 600 nm/20 nm
Ci	1 fF

^#: This value will be changed over the frequency range.

provides the transistor dimensions and other component parameters.

In OPAMP design, a slightly higher length of 60 nm is used to mitigate the short-channel effects. Based on the selected design parameters, the mirroring coefficient (K_i) and the transistors’ dimensions ratios, as expressed in Equations (2)–(4), are unified to a value of one. This design choice ensures that the nominal quiescent current per branch, equal to the short-circuit current of 70 nA, leads to a total nominal quiescent current of N × 70 nA, where N represents the number of delay cells or inverter stages. A coarse-tuning capacitor (C_i) of 1 fF is uniformly applied across all stages. The auxiliary amplifiers (A₁ and A₂) with transistors operating in the subthreshold region delivered an open-loop gain of approximately 33 dB and a phase margin of 94.8°. Figure 4 presents the Bode plots, illustrating both the magnitude and phase responses of the amplifier’s open-loop gain at the nominal temperature of 27 °C.

The stability of the quiescent conditions is confirmed through validation. The nominal bulk voltages, V_BP and V_BN, produced by the circuit shown in Figure 2, are measured at 202.34 mV and 202.4 mV, respectively. Monte Carlo (MC) simulation results show that the bias-generator circuit in Figure 2 delivers an average current of 678 nA, with a standard deviation of 32.15 nA.

Figure 5 illustrates how the body-bias voltages (V_BP and V_BN) of the transistors in the reference-inverting gate are impacted by the biasing current (I_BIAS), which is swept across a range of 30 nA to 130 nA. These voltages remain within the supply rails, and their symmetrical behavior indicates proper sizing and efficient use of the control voltage’s full dynamic range. Additionally, currents flowing into the transistor body terminal are analyzed, which are negligible (<<1 nA).

The increase in bias current (I_BIAS) from 30 nA to 130 nA in the differential delay cell leads to a proportional rise in drain current, which reduces the propagation delay of each stage. As shown in Equation (1), the oscillation frequency is inversely related to this delay, resulting in higher operating frequencies. Moreover, the higher current improves the transconductance (gm) of the differential pairs, enhancing the switching speed and strengthening the regenerative behavior of each stage. These effects collectively contribute to the broader tuning range and higher achievable operating frequencies. This relationship is clearly demonstrated in the simulation results shown in Figure 6, where the oscillator frequency scales effectively with changes in I_BIAS.

The three-stage CCRO output signal with C_i = 1 fF is illustrated in Figure 7 for three different biasing current values: 30 nA, 70 nA, and 130 nA, corresponding to the minimum, nominal, and maximum values, respectively.

The relationship between oscillation frequency and biasing current for C_i = 1 fF is illustrated in Figure 8. The oscillation frequency range is achieved from 537 MHz to 800 MHz, with a tuning sensitivity of approximately 2.63 MHz/nA, calculated as (f_MAX − f_MIN)/(I_{BIAS, MAX} − I_{BIAS, MIN}). This high tuning sensitivity provides wide frequency adjustability while consuming minimal current, making it highly efficient for low-power applications. The 2.63 MHz/nA slope enables significant frequency shifts with small changes in bias current, allowing precise control with low power overhead. Similarly, we have received the oscillation frequency ranges 388 MHz to 587 MHz for the four-stage RO with the sensitivity of 1.99 MHz/nA. While the predicted behavior suggests a linear relationship as derived from Equation (1), the observed results indicate a logarithmic dependence on I_BIAS. The oscillation frequency is highly sensitive to I_BIAS, which is externally supplied in this design for tuning the frequency. To ensure stable operation, a well-regulated and low-noise I_BIAS source is required to minimize the effects of temperature, supply noise, and process variations. While bandgap references or adaptive tuning can help stabilize I_BIAS, their effectiveness depends on the external circuitry [51,52]. Future improvements could explore on-chip compensation to further enhance robustness.

Phase noise is a critical parameter in a ring oscillator (RO), originating from thermal noise, flicker noise, and supply variations, including downscaling transistors at low-frequency noise [37], which influences the threshold voltage (Vth) and oscillation stability. Body-bias tuning further influences Vth, transconductance (g_m), and flicker noise, which directly impacts the phase-noise performance. However, body-biasing optimization, differential architectures, and advanced layout techniques (such as guard rings and symmetric design) have already been adopted in the design to improve the phase noise. Future designs can consider advanced techniques for phase-noise reduction, such as refining low-noise biasing circuits, improved power supply regulation through low-dropout regulators (LDOs), and decoupling capacitors. Additionally, optimizing transistor sizing and using noise-filtering techniques in the control circuitry can further suppress unwanted noise sources.

Finally, Figure 9 illustrates the phase-noise performance as a function of relative frequency (∆f). Phase noise is simulated across the different process corners, varying from −80.69 to −84.97 dBc/Hz,

Table 2. Corner analysis of the three-stage CCRO across different temperatures (TT—Typical–Typical, FF—Fast–Fast, SF—Slow–Fast, FS—Fast–Slow, SS—Slow–Slow).

Corner at T = 0 °C	TT	FF	SF	FS	SS
Osc. Frequency (MHz)	608.7	919.8	511.6	572.8	254.8
Average Power Consumption (µW)	9.51	15.94	10.71	7.54	4.96
Phase noise @1 MHz (dBc/Hz)	−83.43	−81.43	−82.49	−83.81	−84.97
Corner at T = 27 °C	TT	FF	SF	FS	SS
Osc. Frequency (MHz)	666.8	1149	576.5	745.3	373.4
Average Power Consumption (µW)	10.23	16.02	11.2	9.32	6.82
Phase Noise @1 MHz (dBc/Hz)	−83.12	−81.13	−82.1	−83.13	−84.02
Corner at T = 60 °C	TT	FF	SF	FS	SS
Osc. Frequency (MHz)	751.9	1225	598.3	800.6	496.9
Average Power Consumption (µW)	11.25	16.27	10.87	9.33	6.87
Phase Noise @1 MHz (dBc/Hz)	−82.71	−80.69	−81.65	−82.47	−83.19

. This low-phase noise performance enhances signal integrity and improves overall system reliability, making it well-suited for noise-sensitive applications.

However, this tuning flexibility comes with design trade-offs. A higher tuning range generally requires higher bias currents, leading to increased power consumption. Conversely, lower power consumption limits the tuning range, requiring a careful balance based on application requirements. Additionally, the capacitor size (C_i) significantly impacts oscillator performance: increasing (C_i) reduces phase noise but at the cost of a narrower and lower tuning range and higher power dissipation and area. Conversely, a smaller (C_i) extends the tuning range but may result in higher phase noise.

Furthermore, the number of stages affects oscillator frequency, power, and area. Increasing the number of stages generally lowers the oscillation frequency while increasing power consumption and chip area. Conversely, reducing the number of delay cells results in a higher frequency but may degrade phase noise due to reduced averaging. These trade-offs must be carefully considered based on power, area, and performance constraints for specific applications.

Corner analysis results for the three-stage ring oscillator operating at a nominal bias current (I_BIAS) of 70 nA are presented in Table 2. The analysis reveals a notable variation in oscillator frequency across PVT conditions. However, this variation can be effectively mitigated by fine-tuning the bias current (I_BIAS), offering a practical solution for achieving more stable performance under varying conditions. In real-world systems, adjusting I_BIAS effectively compensates for corner-induced frequency shifts. This flexible tuning capability allows the design to maintain stable operation without complex calibration circuits.

Figure 10 highlights the outcomes of mismatch Monte Carlo (MC) simulations conducted under standard conditions (V_DD = 0.4 V and T = 27 °C) at I_BIAS = 70 nA. The simulations provide insights into the impact of device mismatches on oscillator performance, specifically analyzing frequency variation due to inherent process variations. These results help assess the statistical robustness of the design and its ability to maintain consistent performance under real-world manufacturing conditions.

The layout of the three-stage CCRO with an output buffer is illustrated in Figure 11, occupying the area of 4.8 µm × 2.3 µm. This extremely compact layout is beneficial for large-scale system-on-chip (SoC) integration, making it ideal for space-constrained applications such as implantable devices and wearable devices. Post-layout simulations are performed to ensure the reliability of the presented results. The primary impact of the layout is the addition of parasitic capacitance of ~1 fF (to be more specific, 0.82 fF to 0.87 fF) at the CCRO’s output node. By compensating for this effect through a reduction in the stated tuning capacitance by an equivalent amount and the post-layout simulation results closely match those obtained at the schematic level.

A comparison of differential structure-based controlled oscillators (COs) topologies from the literature with the proposed design is presented in

Table 3. State-of-the-art comparison.

Reference	2023, [1]	2016, [44]	2019, [46]	2024, [47]	This Work
Tech. Node (nm)	180	65	65	28	22
Type of Control	Voltage	Voltage	Voltage	Voltage	Current
VDD (V)	0.5	0.6	0.5	1	0.4
N-Stages	4	3	4	4	3
Structure	Diff.	Diff.	Diff.	Diff.	Diff.
Osc. Frequency (MHz)	3.59–13.74	250–800	340–1360	734–975	537–800
Power Consumption (µW)	0.221	146.2	260	322.6	10.23
Phase Noise @1 MHz (dBc/Hz)	−95.01	−86.38	−90.2	−83.78	−83.12
FoM	−154.32	−153.2	−158.7	−148.47	−161.1

. The proposed CCRO outperforms others in terms of power consumption, achieving the best figure of merit.

(FoM) as defined by Equation (5), where the lower FoM (higher negative values) indicates better performance. This is a widely used benchmark for evaluating oscillator efficiency. These results demonstrate the superior trade-off between power efficiency and spectral purity, making the proposed design highly suitable for low-power and high-performance applications.

$$FoM=L\left\{∆f\right\}+10\log \left(P_{\left(mW\right)}\right)-20\mathrm{l}\mathrm{o}\mathrm{g}({\displaystyle \frac{fosc}{∆f}})$$

(5)

where $L\left\{∆f\right\}$ is the phase noise at a particular frequency offset (Δf), measured in dBc/Hz, $P_{\left(mW\right)}$, power consumption normalized to 1 mW, ${\displaystyle \frac{fosc}{∆f}}$ is the normalized frequency offset, where $fosc$ is the oscillation frequency.

The proposed design achieves an FoM of −161.1 dBc/Hz. This value represents the best performance among the evaluated oscillators, highlighting the effectiveness of the current control and body-biasing techniques used in this work. The extremely low power consumption of 10.23 µW, combined with a wide tuning range (537–800 MHz), contributes to this superior FoM. These features enable efficient frequency control with minimal power overhead, making the design highly suitable for low-power IoT and biomedical applications. Compared to state-of-the-art designs, the improved FoM demonstrates a better balance between phase noise and power efficiency, validating the design approach’s effectiveness. This performance advantage emphasizes the potential of the proposed CCRO for advanced SoC integration and space-constrained applications. However, further improvements could be explored for sub-0.4 V operation, as the current biasing approach may face limitations at ultra-low voltages. Especially, the op-amp may not be functioning properly at very low voltages. Future work could explore scalable methods for current control without excessive power consumption and examine alternative technologies or devices that support lower voltage operations.

4. Conclusions

This paper presents an innovative technique for adjusting the delay of the differential inverter cell in current-controlled ring oscillators (CCROs). The method allows precise control of the maximum current in each inverter through a body bias loop and facilitates tuning of the oscillation frequency by modulating a reference current.

CCROs with three and four stages are developed using a 22 nm commercial CMOS technology operating at a supply voltage of 0.4 V. Simulation results demonstrate a wide tuning range from 537 MHz to 800 MHz, extremely low power consumption of 10.23 µW, and a strong figure of merit (FoM) comparable to state-of-the-art designs. This balance of wide tunability, low power, and robust performance highlights the effectiveness of the proposed approach. Additionally, extensive corner and parametric simulations confirm the high resilience of the proposed CCROs to variations in process, voltage, and temperature (PVT), even when utilizing an advanced short-channel technology node.

Future work could explore implementing fractional-N PLL blocks to enhance frequency synthesis flexibility, and temperature compensation schemes could be investigated to improve stability under varying environmental conditions.