A 100 MHz 3 dB Bandwidth, 30 V Rail-to-Rail Class-AB Buffer Amplifier for Base Station ET-PA Hybrid Supply Modulator

Abstract

This paper presents the first hybrid supply modulator (HSM) designed for envelope tracking power amplifiers (ET-PAs) in base station applications. The focus is on a rail-to-rail Class-AB linear amplifier (LA) optimized for high-voltage and wide-bandwidth operation. The LA is designed using 130 nm BCD technology, utilizing Laterally Diffused Metal-Oxide Semiconductor (LDMOS) transistors for high-voltage operation and incorporating shielding MOSFETs to protect the low-voltage devices. The circuit utilizes dual power supply domains (5 V and 30 V) to improve power efficiency. The proposed LA achieves a bandwidth of 100 MHz and a slew rate of +1003/−852 V/$\mathsf{\mu }\mathrm{s}$, with a quiescent power consumption of 0.89 W. Transient simulations using a 50 MHz bandwidth 5G NR envelope input demonstrate that the proposed HSM achieves a power efficiency of 83%. Consequently, the proposed HSM supports high-output (100 W) wideband 5G NR transmission with enhanced efficiency.

1. Introduction

High peak-to-average power ratio (PAPR) and wideband signals in 5G systems demand power amplifiers (PAs) with improved efficiency [1,2]. In user equipment (UE), envelope tracking (ET) has been widely adopted to enhance PA efficiency while maintaining linearity [3,4,5,6,7,8,9,10,11,12,13,14].

While efficiency improvements in base station PAs have been achieved using Doherty amplifiers [15,16], research on the ET technique for base stations remains limited. As shown in

Table 1. Summary of commercial base station power amplifier key performance.

Spec	QPA4501	TGA2307-SM	BLM9D2327-26BZ	BLM10D3438-35AB
Supply Voltage (V)	28	28	28	26
Saturated Power (dBm)	43.5	47	45	45.5
Power Efficiency (%)	38	44.4	41.1	41
PA Type	GaN	GaN	LDMOS	LDMOS

, unlike UE, base station PAs require high output power and supply voltage operation. Considering the peak power and efficiency of the PA, the supply modulator (SM) must be capable of delivering peak output power exceeding 100 W to meet these demands. To address this, this work proposes a hybrid supply modulator (HSM) with a high-voltage linear amplifier (LA) based on Laterally Diffused Metal-Oxide Semiconductor (LDMOS) transistors. Integrated LDMOS-based SM reduces PCB-induced parasitic impedance, enabling wideband and high-voltage operation. LDMOS transistors provide high drain-to-source breakdown voltages (10–48 V) but have gate-to-source breakdown voltage limits below 5 V and significantly larger parasitic capacitance than CMOS transistors, which can limit speed and stability. Therefore, ensuring fast charging and discharging is critical for wideband ET.

This work presents a rail-to-rail Class-AB LA that satisfies the high voltage, fast transient, and wideband requirements of HSM for efficient 5G base station transmission. To enhance efficiency, the LA uses separate low-voltage (LV) and high-voltage (HV) domains. In Section 2, the output power range requirements and the topology of the proposed HSM for the base station PA are discussed. The design of the proposed wideband LA is also described in detail in the same section. In Section 3, the simulation results and performance evaluation of the proposed circuit are presented. Finally, Section 4 concludes this work.

2. HSM for Base Station PA

2.1. HSM Output Power Requirement

To design HSM, it is essential to understand the performance characteristics of the target PA. Figure 1 presents the performance of the TGA2307-SM PA for base station applications. In Figure 1a, the saturated output power (${\mathrm{P}}_{\mathrm{sat}}$) reaches 47 dBm. In Figure 1b, the corresponding drain current at ${\mathrm{P}}_{\mathrm{sat}}$ is approximately 4 A. Given a fixed supply voltage of 28 V, the SM must deliver up to 112 W.

For high linearity operation, the PA typically operates under power back-off (PBO). At 9 dB PBO, which corresponds to the average output power condition, Figure 1b shows that the drain current (${\mathrm{I}}_{\mathrm{d}}$) is 1.25 A. In (1), under a fixed supply operation at 28 V, the average supply power (${\mathrm{P}}_{\mathrm{o}\mathrm{u}\mathrm{t},\mathrm{a}\mathrm{v}\mathrm{g}}$) becomes 35 W. In (2), when operating with ET, the rms supply voltage (${\mathrm{V}}_{\mathrm{S}\mathrm{M},\mathrm{r}\mathrm{m}\mathrm{s}}$) is reduced to 17 V. Assuming the rms SM current (${\mathrm{I}}_{\mathrm{S}\mathrm{M},\mathrm{r}\mathrm{m}\mathrm{s}}$) is approximately equal to the ${\mathrm{I}}_{\mathrm{d}}$, the average supply power (${\mathrm{P}}_{\mathrm{S}\mathrm{M},\mathrm{a}\mathrm{v}\mathrm{g}}$) becomes 21.25 W. In (3), based on these values, the power saving compared to fixed supply operation is calculated as ${\displaystyle \frac{35 \mathrm{W}-21.25 \mathrm{W}}{35 \mathrm{W}}}$ ≈ 39.3%. In (4), the SM must maintain the supply voltage above the knee voltage (${\mathrm{V}}_{\mathrm{k}\mathrm{n}\mathrm{e}\mathrm{e}}$) to ensure proper PA operation.

Table 2. Target SM output power, voltage, and current performance.

${\mathbf{P}}_{\mathbf{S}\mathbf{M},\mathbf{o}\mathbf{u}\mathbf{t}}$	${\mathbf{V}}_{\mathbf{S}\mathbf{M},\mathbf{o}\mathbf{u}\mathbf{t}}$	${\mathbf{I}}_{\mathbf{S}\mathbf{M},\mathbf{o}\mathbf{u}\mathbf{t}}$
${\mathrm{P}}_{\mathrm{S}\mathrm{M},\mathrm{m}\mathrm{a}\mathrm{x}}=112 \mathrm{W}$	${\mathrm{V}}_{\mathrm{S}\mathrm{M},\mathrm{m}\mathrm{a}\mathrm{x}}=28 \mathrm{V}$	${\mathrm{I}}_{\mathrm{S}\mathrm{M},\mathrm{m}\mathrm{a}\mathrm{x}}=4 \mathrm{A}$
${\mathrm{P}}_{\mathrm{S}\mathrm{M},\mathrm{a}\mathrm{v}\mathrm{g}}=21.25 \mathrm{W}$	${\mathrm{V}}_{\mathrm{S}\mathrm{M},\mathrm{r}\mathrm{m}\mathrm{s}}=17 \mathrm{V}$	${\mathrm{I}}_{\mathrm{S}\mathrm{M},\mathrm{r}\mathrm{m}\mathrm{s}}=1.25 \mathrm{A}$
${\mathrm{P}}_{\mathrm{S}\mathrm{M},\mathrm{m}\mathrm{i}\mathrm{n}}=3 \mathrm{W}$	${\mathrm{V}}_{\mathrm{S}\mathrm{M},\mathrm{m}\mathrm{i}\mathrm{n}}=6 \mathrm{V}$	${\mathrm{I}}_{\mathrm{S}\mathrm{M},\mathrm{m}\mathrm{i}\mathrm{n}}=0.5 \mathrm{A}$

summarizes the target SM output power, voltage, and current based on the operating region of the TGA2307-SM PA.

$${\mathrm{P}}_{\mathrm{o}\mathrm{u}\mathrm{t},\mathrm{a}\mathrm{v}\mathrm{g}}={\mathrm{V}}_{\mathrm{f}\mathrm{i}\mathrm{x}\mathrm{e}\mathrm{d},\mathrm{V}\mathrm{D}\mathrm{D}}·{\mathrm{I}}_{\mathrm{d}}$$

(1)

$${\mathrm{P}}_{\mathrm{S}\mathrm{M},\mathrm{a}\mathrm{v}\mathrm{g}}={\mathrm{V}}_{\mathrm{S}\mathrm{M},\mathrm{r}\mathrm{m}\mathrm{s}}·{\mathrm{I}}_{\mathrm{S}\mathrm{M},\mathrm{r}\mathrm{m}\mathrm{s}}$$

(2)

$$\mathrm{P}\mathrm{o}\mathrm{w}\mathrm{e}\mathrm{r} \mathrm{S}\mathrm{a}\mathrm{v}\mathrm{i}\mathrm{n}\mathrm{g}\left(\%\right)={\displaystyle \frac{{\mathrm{P}}_{\mathrm{o}\mathrm{u}\mathrm{t},\mathrm{a}\mathrm{v}\mathrm{g}}-{\mathrm{P}}_{\mathrm{S}\mathrm{M},\mathrm{a}\mathrm{v}\mathrm{g}}}{{\mathrm{P}}_{\mathrm{o}\mathrm{u}\mathrm{t},\mathrm{a}\mathrm{v}\mathrm{g}}}}·100$$

(3)

$${\mathrm{V}}_{\mathrm{S}\mathrm{M},\mathrm{m}\mathrm{i}\mathrm{n}}\ge {\mathrm{V}}_{\mathrm{k}\mathrm{n}\mathrm{e}\mathrm{e}}$$

(4)

2.2. HSM Topology

Figure 2 illustrates the topology of the proposed HSM, which consists of a wideband LA and a high-efficiency Switching Amplifier (SA).

Figure 3 illustrates the operation of HSM. In the simulation shown in Figure 3, the PA was modeled as an equivalent resistance of 8 Ω for simplicity. To simplify the PA model, a decoupling capacitor (${\mathrm{C}}_{\mathrm{PA}}$) of 200 pF and an equivalent resistance (${\mathrm{R}}_{\mathrm{PA}}$) of 8 Ω were used. Although the PAs exhibit nonlinear impedance characteristics, such complexity is impractical for circuit-level simulations. Thus, a simplified resistive model was adopted. The selected resistance value was based on the target PA, TGA2307-SM, which specifies ${\mathrm{V}}_{\mathrm{SM},\mathrm{rms}}=17 \mathrm{V}$, ${\mathrm{I}}_{\mathrm{SM},\mathrm{rms}}=1.25 \mathrm{A}$ and ${\mathrm{P}}_{\mathrm{S}\mathrm{M},\mathrm{a}\mathrm{v}\mathrm{g}}=21.25 \mathrm{W}$, corresponding to ${\mathrm{R}}_{\mathrm{PA}}$ = ${\displaystyle \frac{17 \mathrm{V}}{1.25 \mathrm{A}}}$ = 13.6 Ω. To ensure sufficient drive strength and test under more demanding conditions, a lower resistance of 8 Ω was chosen.

The LA operates as a voltage source, generating an output voltage (${\mathrm{V}}_{\mathrm{S}\mathrm{M},\mathrm{o}\mathrm{u}\mathrm{t}}$), proportional to the input RF envelope signal (${\mathrm{V}}_{\mathrm{e}\mathrm{n}\mathrm{v}}$) with a system gain of 15. The sensing circuit determines whether LA generates sourcing or sinking current into the PA. This block generates two sensing currents through ${\mathrm{V}}_{\mathrm{b},\mathrm{p}}$ and ${\mathrm{V}}_{\mathrm{b},\mathrm{n}}$, which flow through sensing resistors to produce the corresponding voltages, ${\mathrm{V}}_{\mathrm{s}\mathrm{e}\mathrm{n},\mathrm{p}}$ and ${\mathrm{V}}_{\mathrm{s}\mathrm{e}\mathrm{n},\mathrm{n}}$. These voltages serve as inputs to a hysteretic comparator, which then drives the SA. Based on the comparator output, $V_{drive}$ controls the high- and low-side switches to regulate the LX node voltage and generate the SA current (${\mathrm{I}}_{\mathrm{b}\mathrm{u}\mathrm{c}\mathrm{k}}$). In (5), the total output current of the supply modulator (${\mathrm{I}}_{\mathrm{S}\mathrm{M},\mathrm{o}\mathrm{u}\mathrm{t}}$) consists of the sum of the ${\mathrm{I}}_{\mathrm{b}\mathrm{u}\mathrm{c}\mathrm{k}}$ and the LA current (${\mathrm{I}}_{\mathrm{l}\mathrm{i}\mathrm{n}\mathrm{e}\mathrm{a}\mathrm{r}}$). The $I_{buck}$ primarily supplies the low-frequency, near-DC current, while the ${\mathrm{I}}_{\mathrm{l}\mathrm{i}\mathrm{n}\mathrm{e}\mathrm{a}\mathrm{r}}$ handles the high-frequency AC current.

$${\mathrm{I}}_{\mathrm{S}\mathrm{M},\mathrm{o}\mathrm{u}\mathrm{t}} = {\mathrm{I}}_{\mathrm{l}\mathrm{i}\mathrm{n}\mathrm{e}\mathrm{a}\mathrm{r}}+{\mathrm{I}}_{\mathrm{b}\mathrm{u}\mathrm{c}\mathrm{k}}$$

(5)

2.3. Linear Amplifier Design

Figure 4 shows the schematic of the proposed LA. It consists of three gain stages: the first stage is a PMOS differential pair input stage, the second stage is implemented as a mirrored operational transconductance amplifier (OTA), and the third stage adopts a rail-to-rail Class-AB output stage. A reference current source based on a bandgap reference (BGR) generates stable bias currents. The amplifier employs a feedback network of ${\mathrm{R}}_{\mathrm{F}1}$, ${\mathrm{R}}_{\mathrm{F}2}$, and $C_{\mathrm{F}}$ to define the feedback factor and ensure loop stability.

2.3.1. LA Power Efficiency

In HSM applications, the LA provides wide bandwidth but suffers from low power efficiency. The efficiency decreases when the LA operates under a single high-voltage supply. The proposed LA improves power efficiency through a dual supply voltage domain architecture. The reference current source and first stage operate in a 5 V LV domain. The second and third stages, which drive large output swings, utilize a 30 V HV domain.

2.3.2. Shielding MOSFETs

MN10–MN12, MN19, and MP10 function as shielding MOSFETs, which block overvoltage from reaching the LV domain transistors. These MOSFETs also operate in a common-gate configuration, allowing high-voltage domain signals to be interfaced with lower-voltage blocks. MP10 is implemented as a PMOS transistor to ensure proper signal transmission. When configured as a common-gate device, a PMOS allows input signals to be applied at the source and propagated toward the drain, which is suitable for transferring signal variations.

2.3.3. Frequency Response of LA

Modern communication signals have wide bandwidths, requiring an LA with a wide bandwidth for accurate envelope tracking. Typically, the LA bandwidth must be 1.5 to 3 times larger than the envelope signal bandwidth to maintain sufficient tracking accuracy in HSM [18]. In the proposed design, two factors mainly limit the LA bandwidth. First, the floating current source introduces output impedance at nodes X and Y, connected to the gate of the PMOS and NMOS output transistors, respectively. Figure 5 illustrates the small-signal test setup used to analyze the impedance seen from node X of the floating current source.

By applying a test voltage ${\mathrm{v}}_{\mathrm{test}}$, a current ${\mathrm{i}}_{\mathrm{t}\mathrm{e}\mathrm{s}\mathrm{t}}$ flows through the network. The small-signal drain currents ${\mathrm{i}}_{\mathrm{d},\mathrm{n}}$ and ${\mathrm{i}}_{\mathrm{d},\mathrm{p}}$ flow through MP12 and MN16, respectively, and the remaining current ${\mathrm{i}}_{\mathrm{t}\mathrm{e}\mathrm{s}\mathrm{t}}-{\mathrm{i}}_{\mathrm{d},\mathrm{p}}-{\mathrm{i}}_{\mathrm{d},\mathrm{n}}$ flows through the parallel output resistances ${\mathrm{r}}_{\mathrm{o},\mathrm{P}12}\parallel {\mathrm{r}}_{\mathrm{o},\mathrm{N}16}$. From this configuration, the node voltage ${\mathrm{V}}_{\mathrm{test}}$ is given in (6), and the drain currents ${\mathrm{i}}_{\mathrm{d},\mathrm{p}}$ and ${\mathrm{i}}_{\mathrm{d},\mathrm{n}}$ are defined in (7) and (8), respectively. Inserting (7) and (8) into (6) gives (9), which simplifies (9a). The resistance of the floating current source seen from node X is given in (10) and further simplified to (10a) when ${\mathrm{g}}_{\mathrm{m}\mathrm{P}}$ = ${\mathrm{g}}_{\mathrm{m}\mathrm{N}}$

$${\mathrm{v}}_{\mathrm{t}\mathrm{e}\mathrm{s}\mathrm{t}}={(\mathrm{r}}_{\mathrm{o},\mathrm{P}12}\parallel {\mathrm{r}}_{\mathrm{o},\mathrm{N}16})·({\mathrm{i}}_{\mathrm{t}\mathrm{e}\mathrm{s}\mathrm{t}}-{\mathrm{i}}_{\mathrm{d},\mathrm{p}}-{\mathrm{i}}_{\mathrm{d},\mathrm{n}})+{\mathrm{r}}_{\mathrm{o},\mathrm{N}15}{\mathrm{i}}_{\mathrm{t}\mathrm{e}\mathrm{s}\mathrm{t}}$$

(6)

$${\mathrm{i}}_{\mathrm{d},\mathrm{p}}={\mathrm{g}}_{\mathrm{m}\mathrm{P}}·{\mathrm{v}}_{\mathrm{t}\mathrm{e}\mathrm{s}\mathrm{t}}$$

(7)

$${\mathrm{i}}_{\mathrm{d},\mathrm{n}}={\mathrm{g}}_{\mathrm{m}\mathrm{N}}·(-{\mathrm{i}}_{\mathrm{t}\mathrm{e}\mathrm{s}\mathrm{t}}{\mathrm{r}}_{\mathrm{o},\mathrm{N}15})$$

(8)

$${\mathrm{v}}_{\mathrm{t}\mathrm{e}\mathrm{s}\mathrm{t}}={(\mathrm{r}}_{\mathrm{o},\mathrm{P}12}\parallel {\mathrm{r}}_{\mathrm{o},\mathrm{N}16})·({\mathrm{i}}_{\mathrm{t}\mathrm{e}\mathrm{s}\mathrm{t}}-{\mathrm{g}}_{\mathrm{m}\mathrm{P}}{\mathrm{v}}_{\mathrm{t}\mathrm{e}\mathrm{s}\mathrm{t}}+{\mathrm{g}}_{\mathrm{m}\mathrm{N}}{\mathrm{i}}_{\mathrm{t}\mathrm{e}\mathrm{s}\mathrm{t}}{\mathrm{r}}_{\mathrm{o},\mathrm{N}15})+{\mathrm{r}}_{\mathrm{o},\mathrm{N}15}{\mathrm{i}}_{\mathrm{t}\mathrm{e}\mathrm{s}\mathrm{t}}$$

(9)

$${(1+{\mathrm{g}}_{\mathrm{m}\mathrm{P}}\mathrm{r}}_{\mathrm{o},\mathrm{P}12}\parallel {\mathrm{r}}_{\mathrm{o},\mathrm{N}16}){\mathrm{v}}_{\mathrm{test}}=[({\mathrm{r}}_{\mathrm{o},\mathrm{P}12}\parallel {\mathrm{r}}_{\mathrm{o},\mathrm{N}16})(1+{\mathrm{g}}_{\mathrm{m}\mathrm{N}}{\mathrm{r}}_{\mathrm{o},\mathrm{N}15})+{\mathrm{r}}_{\mathrm{o},\mathrm{N}15}]{\mathrm{i}}_{\mathrm{test}}$$

(9a)

$${\displaystyle \frac{{\mathrm{v}}_{\mathrm{t}\mathrm{e}\mathrm{s}\mathrm{t}}}{{\mathrm{i}}_{\mathrm{t}\mathrm{e}\mathrm{s}\mathrm{t}}}}\approx {\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}\mathrm{N}}}{{\mathrm{g}}_{\mathrm{m}\mathrm{P}}}}{\mathrm{r}}_{\mathrm{o},\mathrm{N}15}$$

(10)

$$\approx {\mathrm{r}}_{\mathrm{o},\mathrm{N}15}$$

(10a)

The resistance at node X is approximately ${\mathrm{r}}_{\mathrm{o},\mathrm{P}11}\parallel {\mathrm{r}}_{\mathrm{o},\mathrm{N}15}$ and a large gate capacitance ${\mathrm{C}}_{\mathrm{g},\mathrm{P}17}$ (~100 pF) is also present. Therefore, a dominant pole appears at node X, as shown in (11). Similarly, the pole at node Y is given in (12). The dominant pole of the system is determined by the lower frequency between the poles at nodes X and Y.

$${\mathsf{\omega }}_{\mathrm{p},\mathrm{X}}\approx {\displaystyle \frac{1}{{(\mathrm{r}}_{\mathrm{o},\mathrm{P}11}\parallel {\mathrm{r}}_{\mathrm{o},\mathrm{N}15})\cdot {\mathrm{C}}_{\mathrm{g},\mathrm{P}17} }}$$

(11)

$${\mathsf{\omega }}_{\mathrm{p},\mathrm{Y}}\approx {\displaystyle \frac{1}{{(\mathrm{r}}_{\mathrm{o},\mathrm{P}11}\parallel {\mathrm{r}}_{\mathrm{o},\mathrm{N}15})·{\mathrm{C}}_{\mathrm{g},\mathrm{N}21} }}$$

(12)

A second pole appears at the output. It is determined by the output impedance of the LA (${\mathrm{R}}_{\mathrm{o}\mathrm{u}\mathrm{t},\mathrm{L}\mathrm{A}}$), the PA equivalent resistance (${\mathrm{R}}_{\mathrm{P}\mathrm{A}}$), and a decoupling capacitance (${\mathrm{C}}_{\mathrm{P}\mathrm{A}}$), as shown in Figure 6. The ${\mathrm{R}}_{\mathrm{o}\mathrm{u}\mathrm{t},\mathrm{L}\mathrm{A}}$ is determined by the parallel combination of the output resistances of transistors ${ \mathrm{M}}_{\mathrm{P}17}$ and ${ \mathrm{M}}_{\mathrm{N}21}$. It can be expressed as ${\mathrm{R}}_{\mathrm{o}\mathrm{u}\mathrm{t},\mathrm{L}\mathrm{A}}\approx {\mathrm{r}}_{\mathrm{o},\mathrm{P}17}\parallel {\mathrm{r}}_{\mathrm{o},\mathrm{N}21}$. When ${\mathrm{R}}_{\mathrm{o}\mathrm{u}\mathrm{t},\mathrm{L}\mathrm{A}}\gg {\mathrm{R}}_{\mathrm{P}\mathrm{A}}$, the output pole can be approximated as shown in (13). In this design, ${\mathrm{R}}_{\mathrm{P}\mathrm{A}}=8 \mathsf{\Omega }$ and ${\mathrm{C}}_{\mathrm{PA}}=200 \mathrm{p}\mathrm{F}$, placing the second pole around $100 \mathrm{M}\mathrm{H}\mathrm{z}$.

$${\mathsf{\omega }}_{\mathrm{p},\mathrm{o}\mathrm{u}\mathrm{t}}\approx {\displaystyle \frac{1}{{\mathrm{R}}_{\mathrm{P}\mathrm{A}}\cdot {\mathrm{C}}_{\mathrm{P}\mathrm{A}} }}$$

(13)

The LA system contains two internal poles, along with an additional pole near the unity-gain bandwidth (UGBW), which may affect overall stability. To address this, a zero is introduced in the feedback path, as shown in Figure 7. The frequency-dependent feedback factor $\mathsf{\beta }(\mathrm{s})$ is expressed in (14) and is simplified in (14a) and (14b), where the resulting zero and pole are given in (15) and (16), respectively. With ${\mathrm{R}}_{\mathrm{F}1}=14 \mathrm{k}\mathsf{\Omega }$, ${\mathrm{R}}_{\mathrm{F}2}=1 \mathrm{k}\mathsf{\Omega }, {\mathrm{C}}_{\mathrm{F}}=133.25 \mathrm{f}\mathrm{F}$, the zero and pole are located at ${\mathrm{f}}_{\mathrm{z}}=80 \mathrm{M}\mathrm{H}\mathrm{z}$ and ${\mathrm{f}}_{\mathrm{p}}=1.1 \mathrm{G}\mathrm{H}\mathrm{z}$, as illustrated in Figure 8.

$$\mathsf{\beta }\left(\mathrm{s}\right)={\displaystyle \frac{{\mathrm{V}}_{\mathrm{F}\mathrm{B}}}{{\mathrm{V}}_{\mathrm{S}\mathrm{M},\mathrm{o}\mathrm{u}\mathrm{t}} }}$$

(14)

$$= {\displaystyle \frac{{\mathrm{R}}_{\mathrm{F}2}}{{(\mathrm{R}}_{\mathrm{F}1}\parallel \frac{1}{\mathrm{s}{\mathrm{C}}_{\mathrm{F}}})+{\mathrm{R}}_{\mathrm{F}2} }}$$

(14a)

$$= {\displaystyle \frac{{\mathrm{R}}_{\mathrm{F}2}\left(1+\mathrm{s}{\mathrm{R}}_{\mathrm{F}1}{\mathrm{C}}_{\mathrm{F}}\right)}{{\mathrm{R}}_{\mathrm{F}1}+{\mathrm{R}}_{\mathrm{F}2}+\mathrm{s}{\mathrm{R}}_{\mathrm{F}1}{\mathrm{R}}_{\mathrm{F}2}{\mathrm{C}}_{\mathrm{F}} }}$$

(14b)

$${\mathsf{\omega }}_{\mathrm{z},\mathrm{F}\mathrm{B}}={\displaystyle \frac{1}{{\mathrm{R}}_{\mathrm{F}1}{\mathrm{C}}_{\mathrm{F}}}}$$

(15)

$${\mathsf{\omega }}_{\mathrm{p},\mathrm{F}\mathrm{B}}={\displaystyle \frac{1}{{(\mathrm{R}}_{\mathrm{F}1}{\parallel \mathrm{R}}_{\mathrm{F}2}{)\mathrm{C}}_{\mathrm{F}}}}$$

(16)

Figure 9 shows the frequency response of the LA for different common-mode levels of $V_{env}$ (Min: 400 mV, Typical: 1.13 V, and Max: 1.86 V). The plots include both the loop gain and phase response of the LA. Owing to the feedback path, both the loop UGBW and phase margin (PM) are improved. The UGBW increases from 76 MHz to a maximum of 128 MHz, while the PM improves from 22.6° to 56°. At ${\mathrm{V}}_{\mathrm{e}\mathrm{n}\mathrm{v}}$ = 1.13 V, which corresponds to the Class-AB crossover point, the total transconductance of the output power transistors decreases, resulting in a reduced LA loop gain. The UGBW remains above 100 MHz across the remaining ${\mathrm{V}}_{\mathrm{e}\mathrm{n}\mathrm{v}}$ range from 400 mV to 1.86 V.

2.3.4. Slew Rate of LA

In [21,22], to accurately track high PAPR signals, the LA must provide not only wideband characteristics but also a high slew rate. As shown in Figure 10, nodes X and Y are the most critical nodes affecting the slew rate. The total capacitance at node X is dominated by the gate capacitance of MP17, while that of node Y is primarily determined by the gate capacitance of MN21. The output power transistors (MP17 and MN21) are sized large to handle output currents up to 2.5 A. Consequently, their gate capacitance becomes significant, consisting of both intrinsic capacitance (~100 pF) and additional parasitic capacitance from layout effects. To maintain high slew rate performance, these gate capacitances must be rapidly charged and discharged. Figure 11 compares the slew rate performance under sufficient and insufficient floating current source conditions. A 20 MHz envelope signal with a 1.13 V offset and 730 mV amplitude is applied, requiring the output voltage to swing from 6 V to 28 V. The results show that insufficient source current limits the gate charging speed, degrading the slew rate and impairing envelope tracking accuracy. To improve the slew rate, sufficient current must be provided to quickly charge and discharge the gate capacitance of the output power transistors, as defined by the relation Slew Rate = I/C. As illustrated in Figure 10, the tail current source was increased to 1.5 mA to enhance the available current for charging and discharging. In addition, the current mirror ratios for (MP8, MP11) and (MP7, MP9) were configured to 1:10, ensuring that the charging/discharging current at nodes X and Y is amplified accordingly to effectively drive the large gate capacitances of MP17 and MN21.

Figure 12 shows the transient response when a 50 MHz envelope signal with a 1.13 V offset and 340 mV amplitude is applied, resulting in a smaller output swing from 12 V to 22 V. Unlike the 20 MHz case, full swing from 6 V to 28 V is not achieved due to the higher slew rate requirement. Although a 50 MHz sine wave input requires a higher slew rate for accurate tracking, the actual 50 MHz envelope signal used in this work has its power spectral density mainly concentrated below 50 MHz. This implies that the measured slew rate is sufficient for tracking such practical envelope signals without distortion.

The maximum slew rate performance was evaluated by applying an input pulse to the LA input, with a 2.125 A DC current source connected at the output node to substitute for ${\mathrm{I}}_{\mathrm{b}\mathrm{u}\mathrm{c}\mathrm{k}}$, which primarily supplies the near-DC current component in HSM operation. The ${\mathrm{V}}_{\mathrm{S}\mathrm{M},\mathrm{o}\mathrm{u}\mathrm{t}}$ was driven to swing from 6 V to 28 V and from 28 V to 6 V, and the corresponding slew rates, calculated from the dV/dt of these transitions, were measured as a +1003/−852 V/$\mathsf{\mu }\mathrm{s}$, respectively.

3. Simulation Results

The proposed ET HSM was designed using a 130 nm BCD process, occupying a chip area of 6.36 mm². Figure 13 shows the chip layout of the proposed LA. Figure 14a presents the transient simulation results for a 50 MHz envelope input and the corresponding output voltage. Figure 14b illustrates the current waveforms of LA, SA, and the overall output. The HSM achieves a simulated power efficiency of 83%.

Table 3. Comparison table.

Reference	[4]	[21]	[23]	This Work
Process	180 nm CMOS	65 nm CMOS	180 nm CMOS	130 nm BCD
Application	UE	UE	UE	Base station
Supply voltage (V)	-	2.4	5	5 and 30
PA model	5$\mathsf{\Omega }$//100 pF	4.7$\mathsf{\Omega }$	6$\mathsf{\Omega }$	8$\mathsf{\Omega }$//200 pF
SM output voltage range (V)	Max: 6	-	0.3 to 4.6	6 to 28
Slew rate of LA (V/$\mathsf{\mu }\mathrm{s}$)	−1857/+1239	−307/+325	-	+1003/−852
Efficiency (%)	87.4	91	85	83
Signal bandwidth (Hz)	100 M	80 M	100 M	50 M
Protocol	5G NR	LTE	5G NR	5G NR

summarizes the performance metrics of the proposed HSM and provides a comparison with previously reported works.

This work is the first to implement HSM for base station PA applications, which require a wide output voltage range, 6 V to 28 V, and high output power. To meet these requirements, we employed LDMOS devices in a 130 nm BCDMOS process. Unlike conventional CMOS used in previous UE PA applications, LDMOS transistors include a drift region to support high-voltage operation, which increases the device parasitic capacitance and degrades bandwidth performance. Despite the bandwidth limitations of LDMOS, the proposed HSM successfully tracks a 50 MHz signal bandwidth.

While the efficiency is slightly lower than in previous low-voltage domains [4,21,23], this is mainly due to the higher supply voltage, 30 V, used in this work. Since power loss increases with higher supply voltage (P = V × I), achieving high efficiency becomes more challenging in high-voltage domains.

4. Conclusions

This work presents the first implementation of a 30 V rail-to-rail Class-AB buffer amplifier for ET-PA HSM. Using LDMOS transistors, the proposed HSM achieves a high output voltage swing of 6–28 V, suitable for high-power base station PAs. To enhance LA power efficiency, the design adopts dual supply rails of 5 V and 30 V. Incorporating an LA with a 100 MHz 3 dB bandwidth, the HSM successfully tracks a 50 MHz envelope signal and achieves a power efficiency of 83%.