Design and Verification of a Bridgeless Totem-Pole Power Factor Corrector

Abstract

A power factor corrector (PFC) is a device whose job is to improve the power factor of a device. Several connections of semiconductor converters are used for this purpose; one of them is the bridgeless totem-pole power factor correction converter (BLTP-PFC). The bridgeless totem-pole power factor correction converter (BLTP-PFC) is known for its advantages, including its simple topology, low interference capability, high efficiency, and environmental friendliness. Initially, this article focuses on a single-phase PFC, precisely the principle of operation of the BLTP-PFC converter and its simulation verification. Finally, an experimental prototype of an interlaced totem-pole bridgeless PFC converter is designed to verify the correctness and effectiveness of the proposed method.

1. Introduction

A power factor is defined as the ratio of energy a device can transmit to the output versus the total amount of energy it takes from the input power source. It is a key figure of merit for the design of electrical devices, especially due to the regulations put in place by countries and international organizations like the EU, which define the minimum power factor or maximum level of harmonics a device must have in order to be sold in the European market. Low-quality energy (reactive and deformation power) is a threat to the electrical network, increases heat loss, and can cause power outages. This is why so much attention is paid to improving the power factor of devices. The main causes of a poor power factor are phase shift and distortion, which we can compensate for either passively or actively [1,2,3,4,5,6].

As mentioned above [1], a high power factor (PF) and a low total harmonic distortion (THD) can save us energy and also reduce electromagnetic interference from other electronic devices. For this reason, power factor correction (PFC) converters are used primarily in power supplies to meet the required power quality standards [7,8,9,10,11,12].

Active methods represent a more efficient solution, using controlled semiconductor switches and passive elements (RLC). Closed-loop PFC operation ensures good performance with a wide range of output DC voltage regulation and high input PF. On the other hand, the disadvantages are the higher complexity, weight, dimensions, and price. The PFC circuit is usually connected as a front stage to meet the operational requirements (high PF and low THD).

The connection of a PFC circuit operating in continuous conduction mode (CCM) is a trendy solution for medium- and high-power applications (500 W to several kilowatts). This solution’s advantage is that the continuous waveform of the input current of the PFC converter leads to a low conducted electromagnetic interference (EMI) compared to other active PFC topologies such as buck-boost and buck converters [7].

Several issues, such as robustness, power density, efficiency, cost, and complexity, must be considered when selecting a PFC converter for a given application. In this context, several topologies have been proposed in recent years to improve the characteristics of the traditional converter used for PFC purposes.

The search for new topologies also brings new solutions for PFC converters. For the correct operation of the entire device, however, the input PFC converter must work reliably and stably even with changes in the input voltage. Classic PFC with a single voltage loop at a low load may show instability; other types of PFC have problems during the transition of the input current to zero. For this reason, the PFC converter must work reliably and stably, which ultimately ensures a high and stable PF and a reduced content of harmonic components of input currents, minimized EMI levels, high efficiency, a reduced size of magnetic components, and increased robustness [3,4]. A detailed comparison of individual single-phase topologies of PFC converters is presented in [5].

This article presents the design of a specific part of the converter, namely the bidirectional input–output converter—the bridgeless totem-pole PFC (BLTP-PFC)—which is ready for mass production. This bidirectional converter (BLTP-PFC) is part of a complex active compensation system (ACS) that actively compensates for the electrical grid parameters.

To mitigate conduction losses, this topology employs a full bridge, effectively reducing the number of devices in the conduction path to two. Another advantage of the BLTP-PFC is its bidirectional power flow capability, which contrasts with conventional PFC topologies.

This paper focuses on several key aspects:

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It clarifies the principle of operation of the BLTP-PFC and outlines its advantages over traditional boost PFC converters;

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It presents simulation models aimed at verifying the functionality and properties of BLTP-PFC (these simulations concentrate on the influence of parasitic inductances on the source pin and losses within semiconductor switches);

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It focuses on the dimensioning of key components of the converter (SiC transistors, drivers, inductors, and capacitors);

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It outlines a system control algorithm containing two loops (a current control loop and a voltage control loop, designed using small-signal modeling and a quasi-steady-state approach);

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It also includes the experimental verification and presentation of the measurement results (the measurements encompass the analysis of input current and voltage waveforms, converter efficiency in various operating modes, including rectifier and inverter, and the dynamic behavior of the converter under load changes).

This paper concludes with a summary of the achieved results. It outlines future research directions, explicitly focusing on applying SiC transistors with lower R_DS(on) and minimizing other losses to increase the converter’s overall efficiency.

This article does not focus on designing the converter to achieve the best possible efficiency; the goal is, instead, a design for serial production.

2. Bridgeless Totem-Pole PFC (BLTP-PFC)

A bridgeless totem-pole PFC (BLTP-PFC) is a single-phase PFC that further improves efficiency over conventional boost PFC by reducing the number of semiconductor devices in the conduction path from three to two. The silicon-based totem-pole PFC has been limited to critical conduction mode (CrM) due to silicon switches’ high reverse recovery charge (Qrr). CrM operation requires complex control and interleaving, making it less attractive to higher-power applications than the continuous conduction mode (CCM). Silicon carbide (SiC) transistors enable the CCM operation of BLTP-PFC for higher-power applications. Overall, this solution is more efficient and cost-effective. Industry leaders already deploy this solution in many fields, such as automotive on-board charging, telecom power supplies, data center servers, etc. [13,14,15,16,17,18].

2.1. Benefits of BLTP-PFC

Due to its high efficiency for alternating-current and direct-current (AC-DC) power converters of less than 7 kW, the single-phase bridgeless totem-pole PFC is a superior topology for titanium efficiency than conventional boost PFC. Conventional PFC converters use a full-wave diode rectifier to achieve input rectification and a subsequent boost converter to provide the desired direct-current (DC) output. This topology takes three semiconductor devices in the line-current path, as shown in Figure 1. The arrows indicate the current path in the positive half-cycle of the alternating-current (AC) linear input. To reduce the conduction loss, the totem-pole bridgeless topology uses a full bridge and reduces the number of devices in the conduction path to two, as shown in Figure 2 and [13,14,15,16,17,18].

Regarding power flow, classic PFC topologies are unidirectional, so they only work during the AC-DC stage. BLTP-PFC can be used for bidirectional power flow.

2.2. Electromagnetic Interference

In continuous conduction mode (CCM), the peak-to-peak current ripple of the PFC inductor is typically limited to 40% of the average current. On the other hand, in critical conduction mode (CrM), the turn-off current must be twice the input AC in every switching cycle, resulting in a peak-to-peak current ripple of 200%. This large current ripple generates switching frequency harmonics, contributing to differentially conducted EMI in high-power applications. For example, in a 3.6 kW totem-pole PFC (TP-PFC) operating at 230 V_AC (high line) input voltage, the peak of the average inductor current is 22 A, leading to a 44 A peak turn-off current in CrM if interleaving is not applied.

CCM requires hard switching for both active and freewheeling devices, necessitating a good reverse recovery performance for the freewheeling device. However, CCM benefits from a much simpler control algorithm, making implementation easier. In contrast, CrM achieves soft switching for both devices, with zero-current switching (ZCS) for turn-off in the freewheeling device and ZCS for turn-on in the active device, reducing reverse-recovery-related EMI and turn-on loss. When the freewheeling device is in synchronous rectification, CrM can also achieve zero-voltage switching (ZVS) for the active device by allowing the inductor current to dip slightly below 0 A. Despite these advantages, the high current ripple in CrM leads to increased turn-off switching losses for the active device and introduces high-frequency harmonics due to the fast dv/dt and di/dt slew rates [13,14,15,16,17,18].

2.3. Operation of the Bidirectional Totem-Pole PFC

Compared to the classic boost PFC, its main benefit is that it is a bridgeless circuit, meaning that it does not include a rectifier diode bridge at its input. Therefore, the associated rectifier bridge losses are eliminated, increasing efficiency and power density.

Table 1. Operation modes of BLTP-PFC.

Positive AC Voltage Half-Line	Negative AC Voltage Half-Line
S1: Switching as a synchronous switch	S1: Switching as a control switch
S2: Switching as a control switch	S2: Switching as a synchronous switch
S3: Permanently off	S3: Permanently on
S4: Permanently on	S4: Permanently off

shows the individual operating stages of the BLTP-PFC converter during the AC grid cycle’s positive and negative halves, shown in detail in Figure 3.

Two switches run at a high switching frequency with the function of the boost switch and rectifier switch, while the other two run at a line frequency with the function of the grid rectifier.

3. Simulation of BLTP-PFC

To verify the functionality and features of the functions that BLTP-PFC brings to the design, individual simulation models were created in Simetrix 8.30, Matlab Simulink R2023b, and OrCAD 16.6 simulation software. The Simetrix 8.30 hardware simulation (HW) model is presented in Figure 4. The reason for using different types of transistors is that, for the slow (low-frequency—LF) leg, expensive SiC transistors are unnecessary; slower MOSFETs are sufficient since the transistor is switched on for the entire half-cycle. On the contrary, fast transistors are used in the HF (high-frequency) leg for continuous switching. The simulation waveforms from the HW simulation for the rectifier full-power mode are shown in Figure 5. The input voltage V_IN represents the red waveform, the input current I_IN represents the green waveform, and the PFC inductance (switched) current I_LPFC represents the blue waveform. Figure 6 shows in detail the simulated drain-source voltage V_DS and gate-source voltage U_GS curves and the drain current I_D curve during the turn-off process of the HF low-side switch.

The simulation model highlights the impact of parasitic inductance on the source pin. A voltage drop in U_GS is observed during the transistor’s switching, leading to the transistor’s partial deactivation (debiasing). This voltage drop is caused by the steep current gradient passing through the source pin, which generates a voltage across the parasitic inductance given by Equation (1). This voltage opposes the gate drive voltage, increasing switching losses.

$$V_{S }=L_p{\displaystyle \frac{di}{dt}}$$

(1)

This issue arises from the TO247-3 transistor package, which was selected when the improved TO247-4 package with a Kelvin source clip was not widely available, and the selection of transistors with this feature was limited. At the time of writing, several newer, optimized packages are available, which reduce parasitic inductances and thus mitigate the described effect.

Table 2. Transistors’ simulated losses.

Device/Voltage [V]	Power Losses [W]
HF transistor/230 VAC	17
HF transistor/180 VAC	25
LF transistor/230 VAC	5
LF transistor/180 VAC	6.5

shows the power losses of the semiconductor switches obtained from the simulation. Several methods are available for determining these switch power losses [19,20,21].

The parasitic elements of the individual components of the simulation model were gradually configured based on measurements of real elements selected based on calculations and price evaluation.

4. Converter Component Dimensioning

4.1. Transistors

The wide range of SiC switching element components from different manufacturers presents several options for solving the technical problems associated with BLTP-PFC design, such as a rating voltage of 750 V of the SiC components allowing designs for 400 V or 500 V bus voltage applications. A low on-resistance and a low output capacitance cause a higher efficiency. The range of SiC threshold voltage is typically 2.5 V–4 V. Galvanic isolation for supply drivers is usually necessary due to the recommended negative turn-off voltage. Nowadays, we can find SiC transistors that can be safely driven at a standard gate drive voltage of 0 V to 12 V or 15 V.

We chose 750 V rating transistors, providing extra design flexibility for applications using 400 V or 500 V battery or bus voltages. Even with the higher voltage rating, these devices utilize advanced cell density to minimize drain-source on-resistance (R_DS(on)) per unit area, making them the industry leaders in low resistance. A high current capability is achieved through the use of advanced sintered die attach technology, which enhances thermal performance. In addition to their low on-resistance, these new SiC FETs improve efficiency in hard- and soft-switched circuits. In hard-switched applications like CCM BLTP-PFC or standard two-level inverters, the combination of low on-resistance per unit area and low output capacitance results in an excellent reverse recovery charge (Q_rr) and a reduced output capacitance energy/output charge (E_oss/Q_oss). Furthermore, the devices feature a highly efficient and durable built-in diode with a low forward voltage drop (VF) of less than 1.75 V

4.2. Drivers

In bridge topologies, Figure 7, when the V_DS voltage of one switch experiences a high negative slew rate, the Miller capacitance (C_GD) of the complementary switch injects the current toward the gate. This leads to a voltage spike at the switch gate caused by the voltage drop generated by the Miller current across the gate path impedance. If the resulting voltage spike surpasses the switch’s threshold voltage (V_GS(th)) during the rapid rise of V_DS, a shoot-through event can occur across the half-bridge. Devices with low threshold voltages, such as silicon carbide MOSFETs (SiC MOSFETs), are particularly vulnerable to unintentional turn-on, requiring careful design measures. The negative temperature coefficient of the threshold voltage can further exacerbate this issue. Lowering the gate’s off-resistance (R_Goff) value can be an effective solution to reduce the risk of parasitic capacitive turn-on. These glitch phenomena generally arise from applying a positive or negative dv/dt to the switching node, which causes an immediate gate-drain current (I_GD) to flow through MOSFET’s Miller capacitance (C_GD). Part of this current flows out through the gate terminal and back through the drive sink resistance, leading to a spurious voltage spike at the MOSFET gate. During the negative dv/dt at the turn-off of the complementary switch in a half-bridge topology, it is critical to ensure that the negative gate-source voltage (V_GS) peak stays within the device’s absolute maximum ratings (AMRs) to prevent damage to the gate oxide [22].

After evaluating all the requirements for a high-performance gate driver, UCC5350 was selected. Its key advantages include a high common-mode transient immunity (CMTI), a robust output of ±5 A, and, most importantly, the active Miller clamp feature, which enhances system reliability. The simulation of the transient phenomenon during the turn-off of the HF low-side transistor with the UCC 5350 circuit was realized in the OrCAD 16.6 environment, as shown in Figure 8.

On the left, the figure shows the transient turn-off without the Miller clamp, gate resistance, and R_G = 22 Ohm. After turning off the transistor, it may turn-on again unintentionally and consequently cause a failure. The voltage is V_GS > 5 V while V_GS(th) = 3.5 V.

On the right, the figure shows the transient turn-off with the Miller clamp and R_G = 22 Ohm. After turning off the transistor, a voltage of U_GS = 1 V, which is safely lower than U_GSth = 3.5 V, can be seen. The active Miller clamp function significantly increases reliability, especially at a unipolar excitation voltage, and reduces the turn-off losses at the same time.

4.3. Inductor

The inductance value is one of the most important parameters when designing the inductor for a totem-pole PFC. The inductance (measured in Henries, H) influences the converter’s ability to maintain a continuous current flow and limit the current ripple at the input.

Regarding the impact on the current ripple, a higher inductance results in a lower current ripple, which improves the power quality and reduces the electromagnetic interference (EMI). However, a larger inductor may increase the size and cost of the system.

Regarding the impact on efficiency, the inductance value must be optimized to ensure that the current stays continuous (continuous conduction mode, or CCM) while minimizing losses. An inadequate inductance can lead to a discontinuous conduction mode (DCM), which can increase the switching losses and degradation efficiency [21,22,23,24,25,26,27,28].

Choosing the proper inductance (according to Equations (2) and (3)) involves balancing ripple reduction, size, and efficiency.

$$\begin{gathered} L={\displaystyle \frac{1}{\mathrm{R}\mathrm{i}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{e}}}\ast {\displaystyle \frac{{V_{ac}}^2}{P_O}}\ast \left(1-{\displaystyle \frac{\sqrt{2}\ast V_{ac}}{V_O}}\right)\ast T \\ ={\displaystyle \frac{1}{0.2}}\ast {\displaystyle \frac{{230}^2}{2500}}\ast \left(1-{\displaystyle \frac{\sqrt{2}\ast 230}{415}}\right)\ast {\displaystyle \frac{1}{70\ast {10}^3}}=327 uH \end{gathered}$$

(2)

$$I_{Lmax}={\displaystyle \frac{\sqrt{2}\ast P_O}{V_{ac}}}\ast \left(1+{\displaystyle \frac{Ripple}{2}}\right)={\displaystyle \frac{\sqrt{2}\ast 2500}{230}}\ast \left(1+{\displaystyle \frac{0.2}{2}}\right)=16.9A$$

(3)

4.4. Capacitor

The DC-DC converter requires a stable DC voltage at its input to operate efficiently. However, the input voltage from the PFC stage often contains a significant 100 Hz ripple due to the nature of AC-DC conversion. A large portion of this ripple must be suppressed in the DC-link before reaching the DC-DC converter. The PFC is responsible for correcting the power factor by shaping the input current to be in phase with the input voltage. During this process, the output of the PFC stage, which feeds into the DC-link, can exhibit variations or ripples in the voltage. The DC-DC converter is not designed to efficiently handle large fluctuations in input voltage and current, which can lead to decreased efficiency and increased losses. Therefore, minimizing the ripple at the input of the DC-DC converter is crucial to ensure optimal performance and efficiency [23,29,30,31,32,33].

To select a capacitor correctly, we had to determine its minimum required capacitance. According to Equations (4) and (5), we determined it by choosing the larger value from the results of two methods: the hold-up time method and the maximum ripple voltage method on the capacitor. According to price and parameters, EKMZ451VSN821MR60S was chosen.

$$C_O\ge {\displaystyle \frac{2\ast P_O\ast \mathrm{T}\mathrm{h}\mathrm{o}\mathrm{l}\mathrm{d}}{{{V_O}^2}^2-{{V_{Omin}}^2}^2}}={\displaystyle \frac{2\ast 2500\ast 0.01}{{415}^2-{330}^2}}=789uF$$

(4)

$$C_O\ge {\displaystyle \frac{P_O}{2\ast \mathsf{\pi }\ast \mathrm{f}\ast {∆V}_O\ast V_O}}={\displaystyle \frac{2500}{2\ast \mathsf{\pi }\ast 50\ast 25\ast 415}}=767uF$$

(5)

Section 4 focuses on dimensioning the main components of the hardware part (transistors, drivers, inductors, and capacitors) to achieve optimal properties and low production costs. However, the correct design of the software part, which is closely linked to the hardware part, is also very important for properly operating the entire system. The system control algorithm is described in the following section.

5. System Control Algorithm

The PFC (power factor correction) control system requires two key control loops: the current control loop and the voltage control loop. These loops manage both the inductor current and the DC-link voltage [34,35,36]. They are designed using small-signal modeling and a quasi-steady-state approach, where the nonlinear behavior of transistor currents and voltages is approximated by linearizing them around their switching-period averages.

In the current control loop, the inductor current’s average during each switching period is shaped to follow a sinusoidal waveform aligned with the main voltage. In the case of inverter applications, the current is shifted by 180 degrees. The voltage control loop, on the other hand, regulates the average DC-link voltage to a specified DC level. Both loops use PI controllers to achieve their control objectives.

While the current control loop uses a single PI controller, the voltage control loop employs two PI controllers, though not simultaneously. Under regular operation, a slower PI controller is engaged, operating with a response time of 20 ms. However, when the measured DC-link voltage (V_DC) reaches critical thresholds due to sudden load changes, a faster version of the PI controller is activated, with a loop response time of 28.4 μs.

The complete PFC control system is illustrated in Figure 9. This figure shows that the controllers receive input measurements, including the inductor AC (I_AC), AC voltage (V_AC), and the instantaneous DC-link voltage (V_DC). The system’s output is the boost duty cycle (d), fed into the pulse width modulation (PWM) system. It is assumed that all the necessary current and voltage measurements can be made. However, AC voltage measurements require an isolation transformer to ensure safe separation between the control system and the grid.

The results of the simulation model are shown in Figure 10 and Figure 11. These figures show the waveforms of the basic quantities, namely the input voltage V_IN (red color), the I_LPFC inductor current (blue color), the DC bus voltage V_DC (green color), and the input current I_IN (magenta color). We will first deal with the valid results for a total output power of 2 kW in the rectifier mode of the inverter, as shown in Figure 10, and then also the results in the inverter mode, shown in Figure 11, at the same power. At the input of the inverter, we expect to be connected to a power grid, so it is more appropriate to focus on the shape of the input current I_IN, which is directly related to THD. Another quantity worth paying attention to is the current through the main inductor of the I_LPFC.

The simulation results show suitable properties for applying BLTP-PFC in the ACS. Based on these results, it is possible to proceed to the realization of an experimental prototype of BLTP-PFC for its verification under laboratory conditions. For the correct operation of the entire BLTP-PFC, measuring the required circuit quantities is necessary. The following chapter describes the measuring sensors and control circuits used in the prototype of BLTP-PFC.

6. Measurement

The correct measurement of all required circuit quantities is essential for correctly operating the entire system.

A current sensor type ACS733 with a high bandwidth, namely 1 MHz, was used to measure the PFC inductor current, as shown in Figure 12. The sensor allows a bidirectional current measurement, and its output is galvanically isolated from the input, which has advantages in terms of cost in reducing the number of components. Another helpful feature is the implemented comparator with a fast response to overcurrent, which we used as a source of information for a microcontroller for overcurrent protection.

For controlling the PFC converter, we used the TMS320F28035 digital signal processor (DSP), part of Texas Instruments’ C2000™ family, known for its high performance and efficiency in real-time control applications. This processor features a 32-bit CPU, well-suited for handling complex control algorithms with precise timing requirements. One of the key advantages of the TMS320F28035 is its CLA (control law accelerator), a co-processor designed specifically to offload control loop calculations from the main CPU. Utilizing the CLA, we could perform high-speed control tasks, such as executing fast current and voltage regulation loops, without consuming significant resources from the central processor. This optimization not only saved computational time but also freed up the CPU for other tasks, improving the overall performance and responsiveness of the system.

The PFC converter’s switching frequency was set to 70 kHz, a value carefully chosen to minimize electromagnetic interference (EMI) in the spectrum above 150 kHz and reduce switching losses. This resulted in a switching period of 14.2 μs. The current control loop was designed to execute every second PWM cycle, meaning that it operated with a control period of 28.4 μs.

For the control of the DC-link voltage (V_DC), two control loops were implemented:

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The slow V_DC regulator, which ran every 20 ms to handle long-term voltage stability;

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The fast V_DC regulator, synchronized with the current control loop, which ran every 28.4 μs to ensure a rapid response to voltage changes.

By leveraging the advanced features of the TMS320F28035, such as the CLA unit and its real-time control capabilities, we achieved a precise and efficient control system for the PFC converter.

7. Experimental Verification

The parameters of the designed prototype of the BLTP-PFC converter are shown in

Table 3. Designed prototype specifications.

Parameter	Value
Nominal power [kW]	2
Nominal input voltage [V]	230
Switching frequency [kHz]	70
Nominal capacitor voltage [V]	415

. The designed converter, shown in Figure 13, was verified and tested under laboratory conditions.

With its small dimensions of only 52 mm × 264 mm, the BLTP-PFC converter provided the required power, a bidirectional power flow, a high PF, and a low THD. Under the rectifier mode, it provided input voltage regulation for charging the system batteries, while, under inverter mode, it provided power supply from the batteries to the power grid. The secondary inverter of the ACS provided bidirectional voltage regulation between the BLTP-PFC and the battery itself.

The measurement in the rectifier mode was carried out at an output power of 2 kW. Figure 14 shows the input voltage V_IN (magenta) waveforms and the input current I_IN (yellow). The waveform of the switching current I_LFPC (yellow) flowing through the inductance L_PFC is shown in Figure 15, where the input voltage is V_IN (magenta). The input voltage and current are in phase, so the inverter draws the required power from the grid.

The measurement under the inverter mode was performed at full power, i.e., 2 kW. Figure 16 shows the waveforms of the grid voltage (V_IN = V_GRID, magenta) and the current supplied to the network (I_IN = I_OUT, yellow). The current supplied to the grid is in the opposite phase of grid voltage, so the required power is provided to the grid.

The properties of the designed converter could be evaluated based on Figure 17, which shows the converter’s dynamic behavior during the load’s step change. During this measurement, the power suddenly changed from 0 W to the maximum power (P_MAX), expressed as current I_IN (yellow), and a voltage V_DC (magenta) drop of only 50 V could be seen. This was because a fast V_DC regulator was applied in the control, activated when the V_DC voltage exceeded the set values. If this fast V_DC regulator had not been used and, instead, a classic V_DC regulator had affected the current regulator only every 20 ms, the dynamic response to a step change would have been represented by a voltage drop of more than 120 V.

The designed converter was subjected to further experimental measurements. At a power of 2280 W, an apparent power of 2281 VA (which corresponded to almost 115% of the nominal power), PF = 1, Cos ϕ = 1, THDi = 1.43%, and THDu = 0.90% were determined.

Table 4. BLTP-PFC measurement under the rectifier mode.

Parameter	1	2	3	4	5	6	7	8	9	10
Power [kW]	0.24	0.456	0.665	0.876	1.086	1.294	1.502	1.712	1.912	1.959
PF [-]	0.87	0.96	1	1	1	1	1	1	1	1
Cos ϕ [-]	0.96	0.99	1	1	1	1	1	1	1	1
Efficiency [%]	92.02	95.8	97.66	98.9	98.37	98.37	98.37	98.5	98.7	98.7

shows other measurement results (power, PF, Cos ϕ, and efficiency) for the rectifier mode of the inverter operation (battery-charging mode). Similar measurements are shown in

Table 5. BLTP-PFC measurement under the inverter mode, with SR OFF.

Parameter	1	2	3	4	5	6	7	8	9	10
Power [kW]	−0.11	−0.331	−0.546	−0.75	−0.954	−1.153	−1.345	−1.552	−1.745	−1.928
PF [-]	−0.59	−0.91	−0.98	−0.99	−0.99	−0.99	−1	−1	−1	−1
Cos ϕ [-]	−0.71	−0.95	−0.99	−0.99	−1	−1	−1	−1	−1	−1
Efficiency [%]	87.02	94.01	96.2	96.64	97.1	97.01	97.05	96.8	96.2	96.01

for the inverter mode of operation of the converter, without using the synchronous rectifier mode. Finally,

Table 6. BLTP-PFC measurement under the inverter mode, with SR ON.

Parameter	1	2	3	4	5	6	7	8	9	10
Power [kW]	−0.12	−0.347	−0.547	−0.746	−0.95	−1.151	−1.348	−1.549	−1.739	−1.922
PF [-]	−0.61	−0.95	−0.98	−0.99	−0.99	−1	−1	−1	−1	−1
Cos ϕ [-]	−0.74	−0.96	−0.99	−1	−1	−1	−1	−1	−1	−1
Efficiency [%]	89.1	95.1	96.9	97.1	97.53	97.45	97.42	97.6	97.25	97.1

presents the measurement results for the converter’s inverter mode of operation using the synchronous rectifier mode. Figure 18 compares the converter’s efficiency achieved during individual modes of operation.

8. Conclusions

This article presented the BLTP-PFC’s design process, ready for mass production, and its subsequent verification on an experimental prototype. The topology was chosen based on the results of other articles, research, and simulations. Simulations were concentrated on the influence of parasitic inductances on the source pin and losses within semiconductor switches. A system control algorithm, comprising two loops—a current control loop and a voltage control loop—was described (these loops were designed using small-signal modeling and a quasi-steady-state approach). The design process was then detailed, including the selection and dimensioning of semiconductor switches, drivers, PFC inductors, and capacitors. The individual design steps were supplemented by simulation results that confirmed the correctness of the design. Finally, this article presented a prototype of the experimental BLTP-PFC converter, tested under both required operating modes (rectifier mode and inverter mode) and the entire power range. It is evident from the presented results that the converter worked correctly under each individual mode.

The BLTP-PFC converter achieved a high efficiency under each individual operating modes, namely 98.9% under the rectifier mode, 97.1% under the inverter mode without the use of a synchronous rectifier, and 97.6% under the inverter mode with the use of a synchronous rectifier. Also, the PF was high, and the total harmonic distortion of the THDi current taken or supplied by the converter was less than 1.5%. The stability of the designed converter was verified in the load change mode, from 0 to 100%.

Future works on BLTP-PFC will focus on applying SiC transistors with a lower R_DS(on) and minimizing other power losses to increase the inverter’s overall efficiency. The next step will be finalizing and testing the entire ACS under various operating modes.