Transistor Frequency-Response Analysis: Recursive Shunt-Circuit Transformations

Abstract

Frequency-response analysis is critical in circuit design. Frequency response encodes crucial information, like gain, accuracy, bandwidth, response time, phase shift, stability, and more. Unfortunately, existing methods are either algebraic and obscure or approximations with inaccuracies. So applying them to more complex circuits is often arduous or unreliable. This paper proposes recursive shunt-circuit transformations: a simple, rigorous, and insightful analytical method for conceptualizing and designing electronic circuits. The method asserts that (a) each equivalent capacitance shunts away its parallel resistance past its RC frequency. This (b) decreases the gain (induces a pole) and (c) changes the circuit. (d) The next dominant capacitance shunts its parallel resistance past the next pole and so on until all remaining capacitances shunt their parallel resistances past the poles they establish. The method also asserts that (e) bypass capacitances increase gain (induce zeros) and (f) cross-amp capacitances couple stages and poles. By applying this method and concepts, designers can (i) simplify an arbitrarily complex circuit into simpler coupled/decoupled stages and (ii) determine and manage poles and zeros with insight. This method was applied to design and analyze single- and multi- stage amplifier circuits and results were benchmarked against traditional methods and NGSPICE simulations, demonstrating its accuracy and broad applicability.

1. Introduction: Frequency Response in Electronic Circuits

Electronic circuits have carved for themselves a very fundamental place in today’s modern world. From the smallest mobile phone to the largest spaceships, everything runs on semiconductor integrated circuit (IC) chips. These ICs have various electronic circuits designed for specific applications.

The design of a circuit is typically done by investigating its poles and zeros, i.e., the transfer function and frequency response. Figure 1 shows a general representation of an electronic circuit transfer function in terms of the input and output signals and impedances, i.e., A_Z = v_O/i_I.

Equations (1) and (2) show the transfer function of the system in terms of the DC gain A_S0 and its various negative, real-valued poles and real zeros in the s-domain.

$${\mathrm{A}}_{\mathrm{S}}={\mathrm{A}}_{\mathrm{S}0}\left[{\displaystyle \frac{\left(1\pm \frac{\mathrm{s}}{2\mathsf{\pi }{\mathrm{z}}_1}\right)\left(1\pm \frac{\mathrm{s}}{2\mathsf{\pi }{\mathrm{z}}_2}\right)\dots \left(1\pm \frac{\mathrm{s}}{2\mathsf{\pi }{\mathrm{z}}_{\mathrm{M}}}\right)}{\left(1+\frac{\mathrm{s}}{2\mathsf{\pi }{\mathrm{p}}_1}\right)\left(1+\frac{\mathrm{s}}{2\mathsf{\pi }{\mathrm{p}}_2}\right)\dots \left(1+\frac{\mathrm{s}}{2\mathsf{\pi }{\mathrm{p}}_{\mathrm{N}}}\right)}}\right],$$

(1)

and

$$\mathrm{s}=\mathrm{i}2\mathsf{\pi }{\mathrm{f}}_{\mathrm{O}}.$$

(2)

The transfer function can also be written in terms of its gain and phase as:

$${\mathrm{A}}_{\mathrm{S}}=\left|{\mathrm{A}}_{\mathrm{S}}\right|\mathrm{\angle }{\mathrm{A}}_{\mathrm{S}},$$

(3)

where the gain is calculated by taking the modulus of the transfer function as:

$$\left|{\mathrm{A}}_{\mathrm{S}}\right|={\mathrm{A}}_{\mathrm{S}0}\left[{\displaystyle \frac{\sqrt{1+{\left(\frac{{\mathrm{f}}_{\mathrm{O}}}{{\mathrm{z}}_1}\right)}^2}\sqrt{1+{\left(\frac{{\mathrm{f}}_{\mathrm{O}}}{{\mathrm{z}}_2}\right)}^2}\dots \sqrt{1+{\left(\frac{{\mathrm{f}}_{\mathrm{O}}}{{\mathrm{z}}_{\mathrm{M}}}\right)}^2}}{\sqrt{1+{\left(\frac{{\mathrm{f}}_{\mathrm{O}}}{{\mathrm{p}}_1}\right)}^2}\sqrt{1+{\left(\frac{{\mathrm{f}}_{\mathrm{O}}}{{\mathrm{p}}_2}\right)}^2}\dots \sqrt{1+{\left(\frac{{\mathrm{f}}_{\mathrm{O}}}{{\mathrm{p}}_{\mathrm{N}}}\right)}^2}}}\right],$$

(4)

and the phase is calculated by summing the different arguments in the transfer function as:

$$\begin{gathered} \mathrm{\angle }{\mathrm{A}}_{\mathrm{S}}=\pm {\tan }^{-1}\left({\displaystyle \frac{{\mathrm{f}}_{\mathrm{O}}}{{\mathrm{z}}_1}}\right)\pm {\tan }^{-1}\left({\displaystyle \frac{{\mathrm{f}}_{\mathrm{O}}}{{\mathrm{z}}_2}}\right)\dots \pm {\tan }^{-1}\left({\displaystyle \frac{{\mathrm{f}}_{\mathrm{O}}}{{\mathrm{z}}_{\mathrm{M}}}}\right) \\ -{\tan }^{-1}\left({\displaystyle \frac{{\mathrm{f}}_{\mathrm{O}}}{{\mathrm{p}}_1}}\right)-{\tan }^{-1}\left({\displaystyle \frac{{\mathrm{f}}_{\mathrm{O}}}{{\mathrm{p}}_2}}\right)\dots -{\tan }^{-1}\left({\displaystyle \frac{{\mathrm{f}}_{\mathrm{O}}}{{\mathrm{p}}_{\mathrm{N}}}}\right). \end{gathered}$$

(5)

As can be seen from Equations (3)–(5), the poles decrease both gain and phase. Contrarily, the zeros increase the gain but add/subtract phase depending on whether they are in-phase “non-inverting” zeros or out-of-phase “inverting” zeros. These will be discussed further in Section 4.3 and Section 5.3.

The frequency response of an electronic system is a useful tool in the designer’s belt because it immediately makes evident the DC gain, bandwidth, minimum phase, poles and zeros of the system, phase loss/recovery of up to 90° by each pole/zero, phase difference of up to 90° between successive poles/zeros, gain plot slope after each pole/zero, etc. as seen in Figure 2. Therefore, it simplifies the analysis and makes drawing reliable conclusions pertaining to the gain, speed, and stability of the system intuitive and quicker.

Because frequency response is such a useful tool, over the years, there has been a lot of interest in plotting it [1,2,3,4,5,6,7,8,9,10]. The most notable methods to obtain the transfer function and the frequency response are exact analysis using Kirchhoff’s laws (KCL and KVL) [11,12,13], Miller’s decomposition [4,6,11,14,15,16,17], Huijsing’s shorting capacitance approximation [18,19], method of time constants [5,8,16,17,20,21,22,23,24,25,26,27], Middlebrook’s generalized N-extra element theorem [28,29,30], and graphical analyses [31,32].

All the above methods are rigorous and mathematically intensive, but except for [18], lacking in insight. [18] develops insight for simpler higher order pole calculations but is often incorrect due to its misguided intuition (i.e., incorrect approximation that capacitances short beyond their poles). Therefore, there is a lack of an insightful method to calculate frequency responses of complex circuits accurately and hence, designers turn to numerical/symbolic simulations for reliable calculation of higher order poles/zeros to make design decisions [33,34,35,36].

In this paper, the authors propose an insightful design-oriented circuit analysis method to calculate poles and zeros and by extension, frequency responses accurately. They note that capacitances do not short past their RC frequencies, rather, they shunt their equivalent parallel resistances to reduce gain to the output and induce poles. They also remark that bypass capacitances increase gain to the output and induce zeros and cross-amplifier capacitances couple subsequent stages and poles.

They employ these and other fundamental concepts [1,37] to offer designers an intuitive and straightforward method for identifying and regulating circuit elements to achieve the desired frequency response during circuit design. Thus, the proposed insightful design-based analysis approach helps the designer conceptualize circuits, reduces his dependence on circuit simulations, alleviates challenges, and enhances the efficiency of circuit analysis and design by simplifying the analyses.

Section 2 introduces the readers to the tools required to apply the proposed method. Section 3, Section 4 and Section 5 show the treatment of basic single-stage amplifier circuits. Section 6 depicts the application of the method on multi-stage amplifier circuits. Section 7 comments on the accuracy and benefits of the method. Section 8 reiterates the findings of the paper by presenting the conclusions.

2. Proposed Frequency-Response Analysis

This section showcases and strengthens the four basic concepts the reader should know to apply the proposed frequency response analysis. Wherever applicable, it also mentions the concepts’ intended use in the method. It culminates in an integrated idea which will be built upon in the following sections.

A short note on voltage/current naming convention: Uppercase variables with uppercase subscripts are dc signals. Lowercase variables with lowercase subscripts are ac signals and lowercase variables with uppercase subscripts are complete signals, i.e., ac riding on dc.

2.1. Shunt Circuits

A shunt circuit is a parallel combination of a signal source, R_SH and C_SH as depicted in the left part of Figure 3. Any circuit can be represented as a shunt circuit in its Norton equivalent. And every shunt circuit will have a RC pole frequency p_SH (given by (7)) when C_SH′s impedance equals R_SH as seen in (6).

Above p_SH, the C_SH bypasses R_SH by presenting the input with a lesser impedance path to ground and as a result, the effects of the resistance at the output begin fading. Sufficiently above p_SH (f_O > 10p_SH), R_SH completely disappears. See Figure 3. Simply put, C_SH shunts parallel R_SH past p_SH or, R_SH fades past p_SH because:

$$|{\mathrm{Z}}_{\mathrm{C}}|={\left.{\displaystyle \frac{1}{2\mathsf{\pi }{\mathrm{f}}_{\mathrm{O}}{\mathrm{C}}_{\mathrm{S}\mathrm{H}}}}\right|}_{{\mathrm{f}}_{\mathrm{O}}\ge {\mathrm{p}}_{\mathrm{S}\mathrm{H}}}\le {\mathrm{R}}_{\mathrm{S}\mathrm{H}},$$

(6)

and

$${\mathrm{p}}_{\mathrm{S}\mathrm{H}}={\displaystyle \frac{1}{2\mathsf{\pi }{\mathrm{R}}_{\mathrm{S}\mathrm{H}}{\mathrm{C}}_{\mathrm{S}\mathrm{H}}}}.$$

(7)

The gain and phase error per pole/zero incurred by this simplification as compared to an exact analysis is given by:

$${\left|{\mathrm{A}}_{\mathrm{V}\left(\mathrm{E}\mathrm{r}\mathrm{r}\mathrm{o}\mathrm{r}\right)}\right|}_{{\mathrm{f}}_{\mathrm{O}}=10{\mathrm{p}}_{\mathrm{S}\mathrm{H}}}=\left|{\displaystyle \frac{{\mathrm{A}}_{\mathrm{G}0}{\mathrm{R}}_{\mathrm{S}\mathrm{H}}{\mathrm{C}}_{\mathrm{S}\mathrm{H}}}{1+\mathrm{s}{\mathrm{R}}_{\mathrm{S}\mathrm{H}}{\mathrm{C}}_{\mathrm{S}\mathrm{H}}}}\right|-\left|{\displaystyle \frac{{\mathrm{A}}_{\mathrm{G}0}}{\mathrm{s}{\mathrm{C}}_{\mathrm{S}\mathrm{H}}}}\right|={\displaystyle \frac{{\mathrm{A}}_{\mathrm{G}0}{\mathrm{R}}_{\mathrm{S}\mathrm{H}}}{\sqrt{101}}}-{\displaystyle \frac{{\mathrm{A}}_{\mathrm{G}0}{\mathrm{R}}_{\mathrm{S}\mathrm{H}}}{10}}\approx 0.5\%$$

(8)

and

$${\left.\angle {\mathrm{A}}_{\mathrm{V}\left(\mathrm{E}\mathrm{r}\mathrm{r}\mathrm{o}\mathrm{r}\right)}\right|}_{{\mathrm{f}}_{\mathrm{O}}=10{\mathrm{p}}_{\mathrm{S}\mathrm{H}}}=-{\tan }^{-1}\left({\displaystyle \frac{{\mathrm{f}}_{\mathrm{O}}}{{\mathrm{p}}_{\mathrm{SH}}}}\right)-\left(-90°\right)=-84°+90°=6°.$$

(9)

Therefore, this simplification is a very good approximation to exact analysis that helps the designer gain insight into the circuit across frequency.

2.2. Feedback–Forward Split

Figure 4 shows an amplifier A_G0 with a cross-amplifier capacitance C_X between the input and output nodes. At any given frequency, the capacitance C_X can be written as an equivalent two-port Norton input-Norton output circuit (refer middle third of Figure 4). The split can be defined in terms of the Y-parameters as:

$$\left\{\begin{array}{c}{\mathrm{i}}_1={\mathrm{y}}_{11}{\mathrm{v}}_{\mathrm{I}}+{\mathrm{y}}_{12}{\mathrm{v}}_{\mathrm{O}}\\ {\mathrm{i}}_2={\mathrm{y}}_{21}{\mathrm{v}}_{\mathrm{I}}+{\mathrm{y}}_{22}{\mathrm{v}}_{\mathrm{O}}\end{array}\right..$$

(10)

The equivalent input impedance is calculated by removing the load’s feedback current (i.e., v_O = 0) as:

$${\mathrm{Z}}_{\mathrm{C}\mathrm{I}}={\displaystyle \frac{1}{{\mathrm{y}}_{11}}}={\left.{\displaystyle \frac{{\mathrm{v}}_{\mathrm{I}}}{{\mathrm{i}}_{\mathrm{I}}}}\right|}_{{\mathrm{v}}_{\mathrm{O}}=0}={\displaystyle \frac{1}{\mathrm{s}{\mathrm{C}}_{\mathrm{X}}}}.$$

(11)

The forward effect is the current C_X feeds to the unloaded (shorted) output (i.e., v_O = 0):

$${\mathrm{i}}_{\mathrm{F}\mathrm{W}}={\mathrm{v}}_{\mathrm{I}}{\mathrm{y}}_{21}={\mathrm{v}}_{\mathrm{I}}{\mathrm{A}}_{\mathrm{F}\mathrm{W}}={\mathrm{v}}_{\mathrm{I}}{\left.\left({\displaystyle \frac{{\mathrm{i}}_{\mathrm{F}\mathrm{W}}}{{\mathrm{v}}_{\mathrm{I}}}}\right)\right|}_{{\mathrm{v}}_{\mathrm{O}}=0}={\displaystyle \frac{{\mathrm{v}}_{\mathrm{I}}}{{\mathrm{Z}}_{\mathrm{C}\mathrm{I}}}}={\mathrm{v}}_{\mathrm{I}}\mathrm{s}{\mathrm{C}}_{\mathrm{X}}.$$

(12)

Similarly, the equivalent output impedance is calculated by removing the source’s forward effect (i.e., v_I = 0):

$${\mathrm{Z}}_{\mathrm{C}\mathrm{O}}={\displaystyle \frac{1}{{\mathrm{y}}_{22}}}={\left.{\displaystyle \frac{{\mathrm{v}}_{\mathrm{O}}}{{\mathrm{i}}_{\mathrm{O}}}}\right|}_{{\mathrm{v}}_{\mathrm{I}}=0}={\displaystyle \frac{1}{\mathrm{s}{\mathrm{C}}_{\mathrm{X}}}},$$

(13)

and the feedback effect is the current C_X feeds to the shorted input (i.e., v_I = 0):

$${\mathrm{i}}_{\mathrm{F}\mathrm{B}}={\mathrm{v}}_{\mathrm{O}}{\mathrm{y}}_{12}={\mathrm{v}}_{\mathrm{O}}{\mathrm{A}}_{\mathrm{F}\mathrm{B}}={\mathrm{v}}_{\mathrm{O}}{\left.\left({\displaystyle \frac{{\mathrm{i}}_{\mathrm{F}\mathrm{B}}}{{\mathrm{v}}_{\mathrm{O}}}}\right)\right|}_{{\mathrm{v}}_{\mathrm{I}}=0}={\displaystyle \frac{{\mathrm{v}}_{\mathrm{O}}}{{\mathrm{Z}}_{\mathrm{C}\mathrm{O}}}}{=\mathrm{v}}_{\mathrm{O}}\mathrm{s}{\mathrm{C}}_{\mathrm{X}}.$$

(14)

These feedback and forward effects of C_X affect the higher order pole/zero calculations.

2.3. Cross-Amp Capacitance Split

At any given frequency, the cross-amp capacitance C_X in Figure 5 can also be split into an equivalent input/output capacitance C_XI/C_XO. This capacitance draws the same input/output current i_XI/i_XO as before, i.e., i_I/i_O.

By definition, the frequency-dependent voltage gain from the input to the output is:

$${\mathrm{A}}_{\mathrm{V}}={\displaystyle \frac{{\mathrm{v}}_{\mathrm{O}}}{{\mathrm{v}}_{\mathrm{I}}}}.$$

(15)

Therefore, the equivalent input conductance, i.e., the ratio of current through the equivalent input capacitance to the input voltage is:

$${\mathrm{G}}_{\mathrm{X}\mathrm{I}}={\displaystyle \frac{{\mathrm{i}}_{\mathrm{X}\mathrm{I}}}{{\mathrm{v}}_{\mathrm{I}}}}={\displaystyle \frac{{\mathrm{i}}_{\mathrm{C}\mathrm{I}}-{\mathrm{i}}_{\mathrm{F}\mathrm{B}}}{{\mathrm{v}}_{\mathrm{I}}}}={\displaystyle \frac{{\mathrm{v}}_{\mathrm{I}}/{\mathrm{Z}}_{\mathrm{C}\mathrm{I}}-{\mathrm{v}}_{\mathrm{O}}\mathrm{s}{\mathrm{C}}_{\mathrm{X}}}{{\mathrm{v}}_{\mathrm{I}}}}=\left(1-{\mathrm{A}}_{\mathrm{V}}\right)\mathrm{s}{\mathrm{C}}_{\mathrm{X}}\equiv \mathrm{s}{\mathrm{C}}_{\mathrm{X}\mathrm{I}},$$

(16)

and similarly, the equivalent output conductance is:

$${\mathrm{G}}_{\mathrm{X}\mathrm{O}}={\displaystyle \frac{{\mathrm{i}}_{\mathrm{X}\mathrm{O}}}{{\mathrm{v}}_{\mathrm{O}}}}={\displaystyle \frac{{\mathrm{i}}_{\mathrm{C}\mathrm{O}}-{\mathrm{i}}_{\mathrm{F}\mathrm{W}}}{{\mathrm{v}}_{\mathrm{O}}}}={\displaystyle \frac{{\mathrm{v}}_{\mathrm{O}}/{\mathrm{Z}}_{\mathrm{C}\mathrm{O}}-{\mathrm{v}}_{\mathrm{I}}\mathrm{s}{\mathrm{C}}_{\mathrm{X}}}{{\mathrm{v}}_{\mathrm{O}}}}=\left(1-{\displaystyle \frac{1}{{\mathrm{A}}_{\mathrm{V}}}}\right)\mathrm{s}{\mathrm{C}}_{\mathrm{X}}\equiv \mathrm{s}{\mathrm{C}}_{\mathrm{X}\mathrm{O}}.$$

(17)

As seen in (16), the feedback effect increases the capacitance manyfold. The forward effect in (17), in contrast, decreases the capacitance. Since the voltage gain considered is frequency dependent, this cross-amplifier splitting concept, and the effects observed due to it are exact and rigorous across frequency. This is the same as Miller’s effect and is used to transform the circuit to its shunt-circuit equivalent.

2.4. Recursive Shunt-Circuit Transformations

By the repeated application of concepts discussed in Section 2.1, Section 2.2 and Section 2.3, any circuit can be represented as an N-stage shunt-circuit, as observed in Figure 6. By employing the method of open-circuit time constants (OCTC) with the dominant pole approximation, p₁ is approximately the pole from an arbitrary X1th stage (Xi is a general index for the stage with the ith pole):

$${\mathrm{p}}_1\approx {\displaystyle \frac{1}{2\mathsf{\pi }{\mathrm{M}\mathrm{a}\mathrm{x}}_{\mathrm{k}=1}^{\mathrm{N}}\left\{{{\mathrm{R}}_{\mathrm{k}}}^{\prime }{{\mathrm{C}}_{\mathrm{k}}}^{\prime }\right\}}}={\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{X}1}}^{\prime }{{\mathrm{C}}_{\mathrm{X}1}}^{\prime } }}.$$

(18)

Where R_k′/C_k′ denotes resistance/capacitance at the kth-stage in the 1st-pole shunt circuit. In general, R_k′^M/C_k′^M denotes resistance/capacitance at the kth-stage in the Mth-pole shunt circuit. It is important to note that Xi may not be the ith stage.

The circuit is now changed to reflect R_X1′ being shunted away. A new shunt-circuit equivalent is calculated by merging the remaining capacitances and splitting the resulting cross-amp capacitances. p₂ at the X2th stage (may not be the stage right after X1) is then computed by applying OCTC and dominant pole approx. again, albeit without R_X1′:

$${\mathrm{p}}_2\approx {\displaystyle \frac{1}{2\mathsf{\pi }{\mathrm{M}\mathrm{a}\mathrm{x}}_{\mathrm{k}=1,\mathrm{k}\ne \mathrm{X}1}^{\mathrm{N}}\left\{{{\mathrm{R}}_{\mathrm{k}}}^{″}{{\mathrm{C}}_{\mathrm{k}}}^{″}\right\}}}={\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{X}2}}^{″}{{\mathrm{C}}_{\mathrm{X}2}}^{″} }}.$$

(19)

Now the circuit is again changed to reflect the shunting away of R_X2‴. Similarly, the Mth pole of the circuit is given by applying OCTC and dominant pole approximation without R_X1′^(M−1), R_X2′^(M−1)…R_X(M-1)′^(M−1) as:

$${\mathrm{p}}_{\mathrm{M}}\approx {\displaystyle \frac{1}{2\mathsf{\pi }\mathrm{M}\mathrm{a}{\mathrm{x}}_{\mathrm{k}=1,\mathrm{k}\ne \left\{\mathrm{X}\mathrm{i}\right\}}^{\mathrm{N}}\left\{{{\mathrm{R}}_{\mathrm{k}}}^{\prime \mathrm{M}}|{{\mathrm{C}}_{\mathrm{k}}}^{\prime \mathrm{M}}\right\}}}={\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{X}\mathrm{M}}}^{\prime \mathrm{M}}{{\mathrm{C}}_{\mathrm{X}\mathrm{M}}}^{\prime \mathrm{M}}}}.$$

(20)

Above this frequency, R_X1′^M, R_X2′^M…R_XM′^M have been shunted away. Therefore, the general idea thus becomes as follows: Apply suitable transformations to construct a shunt circuit. Then calculate the p₁ using OCTC and dominant pole approx. Now, shunt R_X1 away and apply transformations to get another shunt circuit and repeat.

Note: The methodology proposed in this section applies most directly to analog broadband circuits like op-amps, voltage references, linear regulators, comparators, data converters, etc. whose sensitivity to on-chip and bond-wire introduced parasitic nH-pH inductances is often negligible. Therefore, the analysis only considers parasitic capacitances to calculate the poles/zeros (and frequency response).

3. Common-Gate Stage

Figure 7 shows a general single-stage common-gate circuit. This circuit has two independent nodes v_I and v_O, and no cross-amp capacitances.

3.1. Low-Frequency Circuit for Common-Gate Stage

Figure 8 shows the small-signal equivalent circuit. It is important to note that in this and subsequent figures, for the sake of compactness, the symbol for M₁ with a gray background represents the low-frequency small-signal model (with the “–g_mv_gs” current source i_g1 and resistance r_ds1 absorbed in it, i.e., resistive and transconductive components are included and capacitive and large-signal static dc components are excluded).

For low frequencies, the capacitances open and the circuit only presents resistive and transconductive components. The equivalent input resistance of this circuit includes R_S1, the resistance looking up into the source of M₁ and is given by:

$${\mathrm{R}}_{\mathrm{I}}={\mathrm{R}}_{\mathrm{S}}||{\mathrm{R}}_{\mathrm{S}1}={\mathrm{R}}_{\mathrm{S}}||{\displaystyle \frac{{\mathrm{r}}_{\mathrm{d}\mathrm{s}1}+{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}||{\mathrm{R}}_{\mathrm{L}\mathrm{D}}}{1+{\mathrm{g}}_{\mathrm{m}1}{\mathrm{r}}_{\mathrm{d}\mathrm{s}1}}}\approx {\mathrm{R}}_{\mathrm{S}}||{\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}1}}},$$

(21)

and the equivalent output resistance of the circuit includes R_D1, the resistance looking down into the drain of source degenerated M₁ and is given by:

$${\mathrm{R}}_{\mathrm{O}}={\mathrm{R}}_{\mathrm{D}1}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}||{\mathrm{R}}_{\mathrm{L}\mathrm{D}}=\left({\mathrm{R}}_{\mathrm{S}}+{\mathrm{r}}_{\mathrm{d}\mathrm{s}1}+{\mathrm{g}}_{\mathrm{m}1}{\mathrm{r}}_{\mathrm{d}\mathrm{s}1}{\mathrm{R}}_{\mathrm{S}}\right)||{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}||{\mathrm{R}}_{\mathrm{L}\mathrm{D}}\approx {\mathrm{r}}_{\mathrm{d}\mathrm{s}2}||{\mathrm{R}}_{\mathrm{L}\mathrm{D}}.$$

(22)

Therefore, the low-frequency transimpedance gain is given by:

$${\mathrm{A}}_{\mathrm{Z}0}={\displaystyle \frac{{\mathrm{v}}_{\mathrm{o}}}{{\mathrm{i}}_{\mathrm{s}}}}={\mathrm{R}}_{\mathrm{I}}{\mathrm{A}}_{\mathrm{V}0}={\mathrm{R}}_{\mathrm{I}}{\mathrm{g}}_{\mathrm{m}1}{\mathrm{R}}_{\mathrm{O}}\approx \left({\mathrm{R}}_{\mathrm{S}}||{\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}1}}}\right){\mathrm{g}}_{\mathrm{m}1}\left({\mathrm{r}}_{\mathrm{d}\mathrm{s}2}||{\mathrm{R}}_{\mathrm{L}\mathrm{D}}\right).$$

(23)

3.2. First-Pole Shunt Circuit for Common-Gate Stage

At intermediate frequencies, the circuit is shown in Figure 8. Now, input and output RC frequencies are compared to find the dominant pole.

Figure 8. Small-signal model for the common-gate stage.

Figure 8. Small-signal model for the common-gate stage.

The input resistance R_I′ is same as R_I calculated for A_Z0 and is the parallel combination of resistances connecting v_i to ground:

$${{\mathrm{R}}_{\mathrm{I}}}^{\prime }={\mathrm{R}}_{\mathrm{S}}||{\displaystyle \frac{{\mathrm{r}}_{\mathrm{d}\mathrm{s}1}+{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}||{\mathrm{R}}_{\mathrm{L}\mathrm{D}}}{1+{\mathrm{g}}_{\mathrm{m}1}{\mathrm{r}}_{\mathrm{d}\mathrm{s}1}}}\approx {\mathrm{R}}_{\mathrm{S}}||{\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}1}}}.$$

(24)

The equivalent input capacitance C_I′ is the parallel combination of capacitances connecting v_i to ground:

$${{\mathrm{C}}_{\mathrm{I}}}^{\prime }={\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}.$$

(25)

Similarly, the equivalent output resistance R_O′ is the parallel combination of all the resistances (to ground) at v_o:

$${{\mathrm{R}}_{\mathrm{O}}}^{\prime }={\mathrm{R}}_{\mathrm{L}\mathrm{D}}{||\mathrm{r}}_{\mathrm{d}\mathrm{s}2}||\left({\mathrm{r}}_{\mathrm{d}\mathrm{s}1}+{\mathrm{R}}_{\mathrm{S}}+{\mathrm{g}}_{\mathrm{m}1}{\mathrm{r}}_{\mathrm{d}\mathrm{s}1}{\mathrm{R}}_{\mathrm{S}}\right)\approx {\mathrm{R}}_{\mathrm{L}\mathrm{D}}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}.$$

(26)

The equivalent output capacitance C_O′ is the parallel combination of all the capacitances (to ground) at v_o:

$${{\mathrm{C}}_{\mathrm{O}}}^{\prime }={\mathrm{C}}_{\mathrm{L}\mathrm{D}}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}2}\approx {\mathrm{C}}_{\mathrm{L}\mathrm{D}}.$$

(27)

Usually, f_O is dominant because of much higher R_O′ in (26) yielding the highest RC product. Therefore, p₁ is given by:

$${\mathrm{p}}_1={\mathrm{f}}_{\mathrm{O}}={\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{O}}}^{\prime }{{\mathrm{C}}_{\mathrm{O}}}^{\prime }}}\approx {\displaystyle \frac{1}{2\mathsf{\pi }\left({\mathrm{R}}_{\mathrm{L}\mathrm{D}}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}\right){\mathrm{C}}_{\mathrm{L}\mathrm{D}}}}.$$

(28)

This p₁ is same as what Miller’s approximation calculates.

3.3. Second-Pole Shunt Circuit for Common-Gate Stage

At frequencies much greater than p₁, R_O′ fades away. Now, v_i is the only node with a resistance (refer (29)) and thus, produces p₂ with C_I″ in the input to output gain translation. The new input resistance R_I″ reflects the fading of R_O′ and is:

$${{\mathrm{R}}_{\mathrm{I}}}^{″}={\mathrm{R}}_{\mathrm{S}}||{\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}1}}}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}1}\approx {\mathrm{R}}_{\mathrm{S}}||{\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}1}}}.$$

(29)

The new equivalent input capacitance C_O’’ is:

$${{\mathrm{C}}_{\mathrm{I}}}^{″}={\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}.$$

(30)

Therefore, p₂ is given by:

$${{\mathrm{p}}_2=\mathrm{f}}_{\mathrm{I}}\approx {\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{I}}}^{″}{{\mathrm{C}}_{\mathrm{I}}}^{″} }}\approx {\displaystyle \frac{1}{2\mathsf{\pi }\left({\mathrm{R}}_{\mathrm{S}}||\frac{1}{{\mathrm{g}}_{\mathrm{m}1}}\right)\left({\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}\right)}}.$$

(31)

3.4. Frequency Response for Common-Gate Stage

Figure 9 shows the Bode plot overlay of the frequency response calculated from proposed method over the simulated response from NGSPICE. Recall that the circuit has two independent nodes.

As observed in the previous sections, each independent node has a pair of equivalent shunt capacitance and resistance that produce a pole. Therefore, the Bode plot is expected to, and observed, to have two poles, each losing up to 90° of phase. It is evident that the calculated response tracks the simulated one closely.

Table 1. Transistor Parameters Used in Simulations.

Parameters
ICS = 10 μA	WCS = 20 μm	L = 1 μm
ICD = 1 mA	WCD = 5 mm	LOL = 30 nm
ICG = 10 μA	WCG = 50 μm	KN′ = 200 μA/V 2
COX″ = 7 fF/μm 2	λN/P = 2%	KP′ = 40 μA/V 2
RS(CS/CD) = 5 MΩ 1	${\mathrm{R}}_{\mathrm{LD}} \to \infty$ Ω	VDD = 5 V
fT(CS) = 470 MHz 2	fT(CD) = 290 MHz 2	fT(CG) = 280 MHz 2
VTN0 = |VTP0| = 0.4 V	CJ0 = 50 fF	tf = 100 ps
β0 = 100 A/A	I2/4(CE-CD) = 200 μA	VA = 50 V
IS = 1fA	I3/4(CS-CG-CD) = 10 μA	γ = 600 mV

¹ R_S used for the common-gate stage is 200 Ω; ² Calculated as per ${\mathrm{f}}_{\mathrm{T}}={\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}}}{2\mathsf{\pi }\left({\mathrm{C}}_{\mathrm{G}\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}}\right)}}$.

presents the 180-nm transistor model parameters used in the circuits in Section 3, Section 4, Section 5 and Section 6. As R_I′/R_I″ is highly sensitive to R_S, choosing a small R_S of the order of ~1/g_m helps emphasize the g_m translation in it. Another factor motivating a small R_S is the mitigation of the source degenerating effect of R_S on g_m. Hence, a small R_S was chosen to aid in demonstrating the rigor of the method.

Note: For all the MOSFETs, body effect was neglected in Section 3, Section 4 and Section 5 for the sake of simplicity and clarity. However, including it is straightforward by adding back g_mb to transconductances and resistances (refer Section 6.1 and Section 6.2). The reader is encouraged to interact with the designed circuit, adapt the equations to their circuit and verify their correctness.

Table 2 in Section 7 shows the comparison results between this work and poles extracted from other methods.

4. Common-Source Stage

Figure 10 shows a generalized single-stage common-source circuit. This circuit has two independent nodes v_I and v_O, and one cross-amp capacitance C_GD1.

4.1. Low-Frequency Circuit for Common-Source Stage

Figure 11 shows the small-signal equivalent circuit. Once again, M₁ represents i_g1 and r_ds1. Again, for low frequencies, the capacitances open. Therefore, the low-frequency transimpedance gain is given by:

$${\mathrm{A}}_{\mathrm{Z}0}={\displaystyle \frac{{\mathrm{v}}_{\mathrm{o}}}{{\mathrm{i}}_{\mathrm{s}}}}{=\mathrm{R}}_{\mathrm{S}}{\mathrm{A}}_{\mathrm{V}0}={\mathrm{R}}_{\mathrm{S}}\left(-{\mathrm{g}}_{\mathrm{m}1}\right)\left({\mathrm{r}}_{\mathrm{d}\mathrm{s}1}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}||{\mathrm{R}}_{\mathrm{L}\mathrm{D}}\right).$$

(32)

4.2. First-Pole Shunt Circuit for Common-Source Stage

At intermediate frequencies, the circuit in Figure 10 can be redrawn as Figure 11 by employing the cross-amp capacitance splitting concept. The equivalent input resistance for the circuit is:

$${{\mathrm{R}}_{\mathrm{I}}}^{\prime }={\mathrm{R}}_{\mathrm{S}}.$$

(33)

The equivalent input capacitance is the parallel combination of the capacitances connecting the input node v_i to ground, including the cross-amp capacitance that was split:

$${{\mathrm{C}}_{\mathrm{I}}}^{\prime }={\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1\mathrm{I}}\approx {\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}\left(-{\mathrm{A}}_{\mathrm{V}0}\right).$$

(34)

Note: the cross-amp capacitance splitting has magnified C_GD1 by a factor of A_V0.

Similarly, the output resistance is calculated by considering all the resistances connecting v_o to ground as:

$${{\mathrm{R}}_{\mathrm{O}}}^{\prime }={\mathrm{r}}_{\mathrm{d}\mathrm{s}1}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}||{\mathrm{R}}_{\mathrm{L}\mathrm{D}}.$$

(35)

The equivalent output capacitance also includes the effect of the cross-amp capacitance splitting. It is given by:

$${{\mathrm{C}}_{\mathrm{O}}}^{\prime }={\mathrm{C}}_{\mathrm{G}\mathrm{D}1\mathrm{O}}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}2}+{\mathrm{C}}_{\mathrm{L}\mathrm{D}}\approx {\mathrm{C}}_{\mathrm{G}\mathrm{D}1}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}2}+{\mathrm{C}}_{\mathrm{L}\mathrm{D}}.$$

(36)

Note: the cross-amp capacitance splitting yields negligible effect at the output for circuits when voltage gain A_V0 is much lesser than −1.

Again, both the input and output RC corner frequencies are compared, and f_I is found to be dominant due to the highest RC product as a result of the capacitance multiplicative effect at the input in (31). Therefore, p₁ is equal to f_I, as noted below:

$${\mathrm{p}}_1={\mathrm{f}}_{\mathrm{I}}\approx {\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{I}}}^{\prime }{{\mathrm{C}}_{\mathrm{I}}}^{\prime }}}\approx {\displaystyle \frac{1}{2\mathsf{\pi }{\mathrm{R}}_{\mathrm{S}}\left[{\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}\left(-{\mathrm{A}}_{\mathrm{V}0}\right)\right]}}.$$

(37)

This p₁ is same as what Miller’s approximation calculates.

4.3. Second-Pole Shunt Circuit for Common-Source Stage

At frequencies much greater than p₁, R_I′ fades away. Thus, the circuit is analyzed by breaking C_GD1 using the feedback-forward split from Section 2. Other concepts can be used to redraw the circuit [4,6], but they are more mathematical whereas this tends to be simpler and gives more insight into the circuit, and is thus, preferred.

Now, the first thing to do is calculate the zero. This is because the effect of the forward component i_FW of C_GD1 is exactly accountable at this stage. i_FW mixes with the current source i_g1 in M₁ and results in a frequency dependent transconductance G_M:

$${\mathrm{G}}_{\mathrm{M}}={\left.{\displaystyle \frac{{\mathrm{i}}_{\mathrm{F}\mathrm{W}}-{\mathrm{i}}_{\mathrm{g}1}}{{\mathrm{v}}_{\mathrm{I}}}}\right|}_{{\mathrm{v}}_{\mathrm{o}}=0}={\mathrm{v}}_{\mathrm{i}}\left({\displaystyle \frac{\mathrm{s}{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}-{\mathrm{g}}_{\mathrm{m}1}}{{\mathrm{v}}_{\mathrm{i}}}}\right)=-{\mathrm{g}}_{\mathrm{m}1}\left(1-{\displaystyle \frac{\mathrm{s}{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}}{{\mathrm{g}}_{\mathrm{m}1}}}\right).$$

(38)

This G_M has a right half plane, positive, out-of-phase “inverting” zero. This zero occurs when i_FW of C_GD1 competes with and overpowers i_g1 of M₁ (refers (38) and (39)) and as a result, inverts the transconductance from negative to positive values. Beyond this zero, i_g1 slowly fades away. Since the zero is drawing current from the system, it subtracts up to 90° of phase.

$${\mathrm{i}}_{\mathrm{F}\mathrm{W}}={\left.{\mathrm{v}}_{\mathrm{i}}\mathrm{s}{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}\right|}_{{\mathrm{f}}_{\mathrm{O}}\ge {\mathrm{z}}_{\mathrm{C}\mathrm{S}}}\ge {\mathrm{i}}_{\mathrm{g}1}={\mathrm{v}}_{\mathrm{i}}{\mathrm{g}}_{\mathrm{m}1}$$

(39)

and

$${\mathrm{z}}_1={\mathrm{z}}_{\mathrm{C}\mathrm{S}}={\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}1}}{2\mathsf{\pi }{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}}}.$$

(40)

Once the zero has been noted, the forward components can be dropped to redraw the circuit. C_GD1 can be rejoined to study the feedback effects affecting the second pole. Since the forward and feedback effects are linear, they can be decoupled, analyzed individually and later clubbed using superposition; this makes the analysis simpler. The circuit is given by Figure 12.

Figure 12 shows that C_GD1, C_S and C_GS1 form a voltage divider from v_o to v_i. This feedback effect tends to diode connect M₁, as any change in v_o changes v_gs1 (and i_g1). It appears as an equivalent resistance at the v_o given by:

$${\mathrm{R}}_{\mathrm{G}\mathrm{M}1}={\displaystyle \frac{{\mathrm{v}}_{\mathrm{o}}}{{\mathrm{i}}_{\mathrm{g}1}}}={\displaystyle \frac{{\mathrm{v}}_{\mathrm{o}}}{{\mathrm{g}}_{\mathrm{m}1}{\mathrm{v}}_{\mathrm{i}}}}={\displaystyle \frac{{\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}}{{\mathrm{g}}_{\mathrm{m}1}{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}}}\approx {\displaystyle \frac{{\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}}{{\mathrm{g}}_{\mathrm{m}1}{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}}}.$$

(41)

Thus, the equivalent output resistance has contributions from R_LD, r_ds1, r_ds2 and the voltage-divided g_m resistance R_GM1:

$${{\mathrm{R}}_{\mathrm{O}}}^{″}={\mathrm{R}}_{\mathrm{G}\mathrm{M}1}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}1}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}||{\mathrm{R}}_{\mathrm{L}\mathrm{D}}\approx {\mathrm{R}}_{\mathrm{G}\mathrm{M}1}.$$

(42)

This voltage divider also effects the output capacitance C_O″ by appearing as an additional capacitance at v_o. A note on convention: $\oplus$ denotes a series connection, which means series capacitances are mathematically parallel, i.e., ${\mathrm{C}}_{\mathrm{A}}\oplus {\mathrm{C}}_{\mathrm{B}}=\left({\mathrm{C}}_{\mathrm{A}}{\mathrm{C}}_{\mathrm{B}}\right)/\left({\mathrm{C}}_{\mathrm{A}}+{\mathrm{C}}_{\mathrm{B}}\right)$.

$${{\mathrm{C}}_{\mathrm{O}}}^{″}=\left[\left({\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}\right)\oplus {\mathrm{C}}_{\mathrm{G}\mathrm{D}1}\right]+{\mathrm{C}}_{\mathrm{G}\mathrm{D}2}+{\mathrm{C}}_{\mathrm{L}\mathrm{D}}.$$

(43)

Therefore, p₂ at the output node v_o is given by:

$${\mathrm{p}}_2={\mathrm{f}}_{\mathrm{O}}\approx {\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{O}}}^{″}{{\mathrm{C}}_{\mathrm{O}}}^{″}}}\approx {\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}1}{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}}{2\mathsf{\pi }\left({\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}\right){{\mathrm{C}}_{\mathrm{O}}}^{″}}}.$$

(44)

4.4. Frequency Response for Common-Source Stage

Figure 13 shows the Bode plot overlaying the frequency response calculated from the proposed method over a NGSPICE simulation. The circuit has two independent nodes and one cross-amp capacitance.

Recall that each independent node has a pair of equivalent shunt capacitance and resistance that produce a pole. Similarly, each cross-amp capacitance mixes with its transistor’s i_g current source to produce a zero. Therefore, the Bode plot is expected to, and observed, to have two poles and a zero.

Each pole is losing up to 90° of phase and the inverting zero is losing another 90° of phase. It is evident that the calculated response tracks the simulated one closely. Table 2 in Section 7 shows a comparison of poles/zeros extracted from the proposed method versus the state-of-the-art methods.

5. Common-Drain Stage

Figure 14 shows a general single-stage common drain circuit. This circuit also has two nodes and a cross-amp capacitance. Therefore, it is also expected to have two poles and a zero.

5.1. Low-Frequency Circuit for Common-Drain Stage

Figure 15 shows the small-signal equivalent circuit. M₁ represents i_g1 and r_ds1. The low-frequency transimpedance gain is given by:

$${\mathrm{A}}_{\mathrm{Z}0}={\displaystyle \frac{{\mathrm{v}}_{\mathrm{o}}}{{\mathrm{i}}_{\mathrm{s}}}}={\mathrm{R}}_{\mathrm{S}}{\mathrm{A}}_{\mathrm{V}0}={\mathrm{R}}_{\mathrm{S}}\left({\mathrm{g}}_{\mathrm{m}1}\right)\left({\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}1}}}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}1}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}||{\mathrm{R}}_{\mathrm{L}\mathrm{D}}\right)\approx {\mathrm{R}}_{\mathrm{S}}.$$

(45)

5.2. First-Pole Shunt Circuit for Common-Drain Stage

At intermediate frequencies, the circuit is drawn as Figure 15 by employing the cross-amp capacitance splitting concept on C_GS1. The equivalent input resistance for the circuit is:

$${{\mathrm{R}}_{\mathrm{I}}}^{\prime }={\mathrm{R}}_{\mathrm{S}}.$$

(46)

The equivalent input capacitance is the parallel combination of the capacitances connecting the input node v_i to ground, including the effect of the cross-amp capacitance that was split:

$${{\mathrm{C}}_{\mathrm{I}}}^{\prime }={\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}1\mathrm{I}}\approx {\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}.$$

(47)

Similarly, the output resistance is calculated by considering all the resistances connecting v_o to ground. This includes the 1/g_m1 resistance observed when looking up into the source of M₁:

$${{\mathrm{R}}_{\mathrm{O}}}^{\prime }={\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}1}}}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}1}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}||{\mathrm{R}}_{\mathrm{L}\mathrm{D}}\approx {\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}1}}}.$$

(48)

The equivalent output capacitance also includes the effect of the cross-amp capacitance splitting. It is given by:

$${{\mathrm{C}}_{\mathrm{O}}}^{\prime }={\mathrm{C}}_{\mathrm{G}\mathrm{S}1\mathrm{O}}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}2}+{\mathrm{C}}_{\mathrm{L}\mathrm{D}}\approx {\mathrm{C}}_{\mathrm{G}\mathrm{D}2}+{\mathrm{C}}_{\mathrm{L}\mathrm{D}}\approx {\mathrm{C}}_{\mathrm{L}\mathrm{D}}.$$

(49)

Again, the input and output RC frequencies are compared, and f_I is found to be dominant due to the much higher R_I′ in (46) yielding a higher RC product. Therefore, p₁ equals f_I, as noted below:

$${\mathrm{p}}_1={\mathrm{f}}_{\mathrm{I}}\approx {\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{I}}}^{\prime }{{\mathrm{C}}_{\mathrm{I}}}^{\prime }}}\approx {\displaystyle \frac{1}{2\mathsf{\pi }{\mathrm{R}}_{\mathrm{S}}\left({\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}\right)}}.$$

(50)

p₁ is the result one would have obtained by applying Miller’s approximation. Note: An important consequence of the cross-amp capacitance splitting concept is that in systems with positive voltage gain, the equivalent input/output capacitance decreases. If ${\mathrm{A}}_{\mathrm{V}}$ is approximately one, like in the present case, C_XI/O disappears. Refers (16), (17), (47) and (49).

5.3. Second-Pole Shunt Circuit for Common-Drain Stage

At frequencies much greater than p₁, R_I′ fades away. Thus, the circuit is analyzed by breaking C_GS1 using the feedback-forward split from Section 2.

Once again, the zero is calculated. It accounts for the forward effects of the cross-amplifier capacitance, C_GS1. i_FW and i_g1 in M₁ mix to give a frequency dependent G_M as:

$${\mathrm{G}}_{\mathrm{M}}={\left.{\displaystyle \frac{{\mathrm{i}}_{\mathrm{F}\mathrm{W}}+{\mathrm{i}}_{\mathrm{g}1}}{{\mathrm{v}}_{\mathrm{i}}}}\right|}_{{\mathrm{v}}_{\mathrm{o}}=0}={\mathrm{v}}_{\mathrm{i}}\left({\displaystyle \frac{\mathrm{s}{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}+{\mathrm{g}}_{\mathrm{m}1}}{{\mathrm{v}}_{\mathrm{i}}}}\right)={\mathrm{g}}_{\mathrm{m}1}\left(1+{\displaystyle \frac{\mathrm{s}{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}}{{\mathrm{g}}_{\mathrm{m}1}}}\right).$$

(51)

This G_M has a left half plane, negative, in-phase “non-inverting” zero. This zero occurs when i_FW overpowers i_g1 in magnitude (refers (51) and (52)) by providing the source with a lower impedance path to the output. Beyond this frequency, i_g1 will slowly fade away. Since the zero is feeding current into the system, it recovers up to 90° of phase:

$${\mathrm{i}}_{\mathrm{F}\mathrm{W}}={\left.{\mathrm{v}}_{\mathrm{i}}\mathrm{s}{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}\right|}_{{\mathrm{f}}_{\mathrm{O}}\ge {\mathrm{z}}_{\mathrm{C}\mathrm{D}}}\ge {\mathrm{i}}_{\mathrm{g}1}={\mathrm{g}}_{\mathrm{m}1}{\mathrm{v}}_{\mathrm{i}}$$

(52)

and

$${\mathrm{z}}_1={\mathrm{z}}_{\mathrm{C}\mathrm{D}}={\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}1}}{2\mathsf{\pi }{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}}}.$$

(53)

Once the zero has been noted, the forward components can be dropped to redraw the circuit as Figure 16. C_GS1 is rejoined to study the feedback effects affecting the second pole. The only node with a resistance is v_o, so the pole appears at v_o.

Here, C_GS1, C_S and C_GD1 form a voltage divider from v_o to v_i. This feedback effect tends to diode connect M₁, as any change in v_o changes v_gs1 (and i_g1). It appears as an equivalent resistance at the v_o given by:

$${\mathrm{R}}_{\mathrm{G}\mathrm{M}1}={\displaystyle \frac{{\mathrm{v}}_{\mathrm{o}}}{{\mathrm{i}}_{\mathrm{g}1}}}={\displaystyle \frac{{\mathrm{v}}_{\mathrm{o}}}{{\mathrm{g}}_{\mathrm{m}1}{\mathrm{v}}_{\mathrm{g}\mathrm{s}}}}={\displaystyle \frac{{\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}}{{\mathrm{g}}_{\mathrm{m}1}\left({\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}\right)}}\approx {\displaystyle \frac{{{\mathrm{C}}_{\mathrm{S}}+\mathrm{C}}_{\mathrm{G}\mathrm{S}1}}{{\mathrm{g}}_{\mathrm{m}1}{\mathrm{C}}_{\mathrm{S}}}}.$$

(54)

Thus, the equivalent output resistance has contributions from R_LD, r_ds1, r_ds2 and the voltage-divided g_m resistance R_GM1:

$${{\mathrm{R}}_{\mathrm{O}}}^{″}={\mathrm{R}}_{\mathrm{G}\mathrm{M}1}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}1}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}||{\mathrm{R}}_{\mathrm{L}\mathrm{D}}\approx {\mathrm{R}}_{\mathrm{G}\mathrm{M}1}.$$

(55)

This voltage divider also effects the output capacitance C_O″ by appearing as an additional capacitance in parallel at v_o. It is given by:

$${{\mathrm{C}}_{\mathrm{O}}}^{″}=\left[\left({\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}\right)\oplus {\mathrm{C}}_{\mathrm{G}\mathrm{S}1}\right]+{\mathrm{C}}_{\mathrm{G}\mathrm{D}2}+{\mathrm{C}}_{\mathrm{L}\mathrm{D}}.$$

(56)

Therefore, p₂ at the output node v_o is given by:

$${\mathrm{p}}_2={\mathrm{f}}_{\mathrm{O}}\approx {\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{O}}}^{″}{{\mathrm{C}}_{\mathrm{O}}}^{″}}}\approx {\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}1}{\mathrm{C}}_{\mathrm{S}}}{2\mathsf{\pi }\left({\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}\right){{\mathrm{C}}_{\mathrm{O}}}^{″}}}.$$

(57)

5.4. Frequency Response for Common-Drain Stage

Figure 17 shows the Bode plot overlay of the frequency response calculated from proposed method over the simulated response from NGSPICE. Each pole is losing up to 90° of phase and the non-inverting zero is recovering up to 90° of phase. It is evident that the calculated response tracks the simulated one closely. Table 2 in Section 7 shows a comparison of poles/zeros extracted from the proposed method versus the state-of-the-art methods.

Table 1 shows the design parameters used to simulate the circuit. R_GM1 is noted to be very sensitive to the source capacitance. Any appreciable C_S will minimize the voltage division to produce a ~1/g_m result as a simplification of the form in (54). Therefore, the circuit was designed without it.

6. Clustered Poles

In complex designs, the N-stage shunt circuit often exhibits closely spaced poles. This occurs when two or more capacitances shunt their respective parallel resistances less than a decade apart; this spacing is insufficient for the capacitances to fully shunt their parallel resistances. Consequently, the impedances interact as they are being shunted and the successive pole calculation sees the effect of the resistance from the “previous pole”. In such scenarios, the treatment is dependent on whether the components exhibiting the pole are coupled or decoupled, as explained below.

6.1. Coupled Poles

A circuit has coupled stages when capacitances couple the shunt resistances connected at its ends. Therefore, a cross-amp. capacitance couples the input and output nodes it is connected across. The possibilities for such coupling appear in circuits with common-source/emitter stages through the C_GD or C_BC/C_μ capacitance as shown in gray in Figure 18, or common-drain/collector stages through the C_GS or C_BE/C_π capacitance as shown in gray in Figure 19.

For two coupled poles p₁ and p₂ set by the RC corner frequencies f_I and f_O with f_I < f_O, f_I is RC frequency at the input node and is given by:

$${\mathrm{f}}_{\mathrm{I}}={\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{I}}}^{\prime }{{\mathrm{C}}_{\mathrm{I}}}^{\prime } }}.$$

(58)

Similarly, f_O is the RC corner frequency at the output node and is given by:

$${\mathrm{f}}_{\mathrm{O}}={\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{O}}}^{\prime }{{\mathrm{C}}_{\mathrm{O}}}^{\prime } }}.$$

(59)

Since the individual RCs are close together, their impedances interact and the effect of their RCs add. Therefore, the first pole, p₁, is approximated by their combined time constants as:

$${\mathrm{p}}_1\approx {\displaystyle \frac{1}{2\mathsf{\pi }\left({{\mathrm{R}}_{\mathrm{I}}}^{\prime }{{\mathrm{C}}_{\mathrm{I}}}^{\prime }+{{\mathrm{R}}_{\mathrm{O}}}^{\prime }{{\mathrm{C}}_{\mathrm{O}}}^{\prime }\right)}}={\displaystyle \frac{1}{1/{\mathrm{f}}_{\mathrm{I}}+1/{\mathrm{f}}_{\mathrm{O}}}}={\mathrm{f}}_{\mathrm{I}}||{\mathrm{f}}_{\mathrm{O}}.$$

(60)

This means that the first pole is the parallel combination of the individual RC frequencies and is lower than the lowest of the two. The higher pole (lower time constant), p₂, tends to be higher than the first pole in the ratio of the individual time constants and can be mathematically expressed as:

$${\mathrm{p}}_2\approx {\displaystyle \frac{1}{2\mathsf{\pi }\left({{\mathrm{R}}_{\mathrm{I}}}^{\prime }{{\mathrm{C}}_{\mathrm{I}}}^{\prime }+{{\mathrm{R}}_{\mathrm{O}}}^{\prime }{{\mathrm{C}}_{\mathrm{O}}}^{\prime }\right){{\mathrm{R}}_{\mathrm{O}}}^{\prime }{{\mathrm{C}}_{\mathrm{O}}}^{\prime }/\left({{\mathrm{R}}_{\mathrm{I}}}^{\prime }{{\mathrm{C}}_{\mathrm{I}}}^{\prime }\right) }}={\mathrm{p}}_1\left({\displaystyle \frac{{{\mathrm{R}}_{\mathrm{I}}}^{\prime }{{\mathrm{C}}_{\mathrm{I}}}^{\prime }}{{{\mathrm{R}}_{\mathrm{O}}}^{\prime }{{\mathrm{C}}_{\mathrm{O}}}^{\prime }}}\right)={\mathrm{p}}_1\left({\displaystyle \frac{{\mathrm{f}}_{\mathrm{O}}}{{\mathrm{f}}_{\mathrm{I}}}}\right).$$

(61)

Common Emitter–Common Drain Design Example

Figure 20 shows a general cascaded common emitter–common drain circuit. Since this circuit has cross-amp capacitances between subsequent nodes (and a wire short between o/p of Q₁ and i/p of M₃), this is an example of a coupled stage. Its transistor parameters are given in Table 1. It has three independent nodes v_I, v_X, and v_O and two cross-amp capacitances (C_μ1, C_GS3). Therefore, it is expected to have three poles and two zeros.

• Low-Frequency Common Emitter–Common Drain Circuit

Figure 21 shows the small-signal equivalent. Here, Q₁ represents i_g1, r_π1, and r_o1 and M₃ represents i_g3, r_ds3. The low-frequency transimpedance gain is given by:

$$\begin{gathered} {\mathrm{A}}_{\mathrm{Z}0}={\mathrm{R}}_{\mathrm{I}}{\mathrm{A}}_{\mathrm{V}0}={\mathrm{R}}_{\mathrm{S}}||{\mathrm{r}}_{\mathsf{\pi }1}{\mathrm{A}}_{\mathrm{V}10}{\mathrm{A}}_{\mathrm{V}30} \\ \approx -{\mathrm{R}}_{\mathrm{I}}{\mathrm{g}}_{\mathrm{m}1}\left({\mathrm{r}}_{\mathrm{o}1}||{\mathrm{R}}_2\right){\mathrm{g}}_{\mathrm{m}3}\left({\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}3}}}||{\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}\mathrm{b}3}}}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}3}||{\mathrm{R}}_4\right). \end{gathered}$$

(62)

2.

First-Pole Common Emitter–Common Drain Shunt-Circuit

At intermediate frequencies, the capacitances come into play and the circuit is drawn by employing the cross-amp capacitance splitting concept on C_BC1 and C_GS3. The poles at each node are compared, and f_I is found to be dominant due to the highest RC product because of the capacitance multiplicative effect at the input. Therefore, p₁ equals f_I, as noted below:

$${\mathrm{p}}_1={\mathrm{f}}_{\mathrm{I}}\approx {\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{I}}}^{\prime }{{\mathrm{C}}_{\mathrm{I}}}^{\prime }}}\approx {\displaystyle \frac{1}{2\mathsf{\pi }\left({\mathrm{R}}_{\mathrm{S}}||{\mathrm{r}}_{\mathsf{\pi }1}\right)\left[{\mathrm{C}}_{\mathsf{\mu }1}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}\left(-{\mathrm{A}}_{\mathrm{V}10}\right)\right]}}.$$

(63)

3.

Second-Pole Common Emitter–Common Drain Shunt Circuit

At frequencies much greater than p₁, R_I′ fades away. Thus, the circuit is redrawn as Figure 22 using concepts from Section 2. C_μ1 now diode connects Q₁ and will lead to a voltage-divided gm at v_x. First, the forward effect is accounted for to get the zero from the common-emitter stage as:

$${\mathrm{z}}_{\mathrm{C}\mathrm{E}}={\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}1}}{2\mathsf{\pi }{\mathrm{C}}_{\mathsf{\mu }1}}}.$$

(64)

Now, the RC product of R_X″ and C_X″ is computed. R_X″ is given as:

$${{\mathrm{R}}_{\mathrm{X}}}^{″}={\mathrm{R}}_{\mathrm{G}\mathrm{M}1}||{\mathrm{r}}_{\mathrm{o}1}||{\mathrm{R}}_2\approx {\mathrm{R}}_{\mathrm{G}\mathrm{M}1},$$

(65)

where R_GM1 is the voltage-divided g_m resistance given by:

$${\mathrm{R}}_{\mathrm{G}\mathrm{M}1}={\displaystyle \frac{{\mathrm{C}}_{\mathsf{\pi }1}+{\mathrm{C}}_{\mathsf{\mu }1}}{{\mathrm{g}}_{\mathrm{m}1}{\mathrm{C}}_{\mathsf{\mu }1}}}\approx {\displaystyle \frac{{\mathrm{C}}_{\mathsf{\pi }1}}{{\mathrm{g}}_{\mathrm{m}1}{\mathrm{C}}_{\mathsf{\mu }1}}}.$$

(66)

The equivalent capacitance at C_X″ is:

$$\begin{gathered} {{\mathrm{C}}_{\mathrm{X}}}^{″}=\left[{\mathrm{C}}_{\mathsf{\pi }1}\oplus {\mathrm{C}}_{\mathsf{\mu }1}\right]+{\mathrm{C}}_{\mathrm{G}\mathrm{D}3}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}3\mathrm{I}} \\ =\left[{\mathrm{C}}_{\mathsf{\pi }1}\oplus {\mathrm{C}}_{\mathsf{\mu }1}\right]+{\mathrm{C}}_{\mathrm{G}\mathrm{D}3}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}3}\left(1-{\mathrm{A}}_{\mathrm{V}30}\right), \end{gathered}$$

(67)

Then, the RC product of R_O″ and C_O″ is computed. R_O″ is given by:

$${{\mathrm{R}}_{\mathrm{O}}}^{″}={\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}3}}}||{\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}\mathrm{b}3}}}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}3}||{\mathrm{R}}_4.$$

(68)

The net capacitance at C_O″ is:

$${{\mathrm{C}}_{\mathrm{O}}}^{″}={\mathrm{C}}_{\mathrm{G}\mathrm{S}3\mathrm{O}}+{\mathrm{C}}_{\mathrm{L}\mathrm{D}}={\mathrm{C}}_{\mathrm{G}\mathrm{S}3}\left(1-{\displaystyle \frac{1}{{\mathrm{A}}_{\mathrm{V}30}}}\right)+{\mathrm{C}}_{\mathrm{L}\mathrm{D}},$$

(69)

Then, the RC products of R_X″C_X″ and R_O″C_O″ are compared to find that they are similar in magnitude with R_O″C_O″ being slightly larger (f_O″ < f_X″). Therefore, p₂ in the i_s to v_o gain translation is given by:

$${\mathrm{p}}_2\approx {\displaystyle \frac{1}{2\mathsf{\pi }\left({{\mathrm{R}}_{\mathrm{O}}}^{″}{{\mathrm{C}}_{\mathrm{O}}}^{″}+{{\mathrm{R}}_{\mathrm{X}}}^{″}{{\mathrm{C}}_{\mathrm{X}}}^{″}\right)}}={{\mathrm{f}}_{\mathrm{O}}}^{″}||{{\mathrm{f}}_{\mathrm{X}}}^{″}.$$

(70)

4.

Third-Pole Common Emitter–Common Drain Shunt Circuit

Typically, at frequencies much greater than p₂, R_O″ fades away. However, as R_O″C_O″ ≈ R_X″C_X″ in this design, R_O″ persists for p₃ calculation. Thus, the circuit is redrawn as Figure 23 using concepts from Section 2. First, the forward effect is accounted for to get the zero from the common-drain stage:

$${\mathrm{z}}_{\mathrm{C}\mathrm{D}}={\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}3}}{2\mathsf{\pi }{\mathrm{C}}_{\mathrm{G}\mathrm{S}3}}}.$$

(71)

Then, the next pole is calculated by employing the theory developed at the beginning of this section as:

$${\mathrm{p}}_3\approx {\displaystyle \frac{1}{2\mathsf{\pi }\left({{\mathrm{R}}_{\mathrm{O}}}^{″}{{\mathrm{C}}_{\mathrm{O}}}^{″}+{{\mathrm{R}}_{\mathrm{X}}}^{″}{{\mathrm{C}}_{\mathrm{X}}}^{″}\right){{\mathrm{R}}_{\mathrm{X}}}^{″}{{\mathrm{C}}_{\mathrm{X}}}^{″}/\left({{\mathrm{R}}_{\mathrm{O}}}^{″}{{\mathrm{C}}_{\mathrm{O}}}^{″}\right) }}={\mathrm{p}}_2\left({\displaystyle \frac{{{\mathrm{R}}_{\mathrm{O}}}^{″}{{\mathrm{C}}_{\mathrm{O}}}^{″}}{{{\mathrm{R}}_{\mathrm{X}}}^{″}{{\mathrm{C}}_{\mathrm{X}}}^{″}}}\right)={\mathrm{p}}_2\left({\displaystyle \frac{{{\mathrm{f}}_{\mathrm{X}}}^{″}}{{{\mathrm{f}}_{\mathrm{O}}}^{″}}}\right).$$

(72)

5.

Frequency Response for Common Emitter–Common Drain Circuit

Figure 24 shows the Bode plot overlay of the calculated poles/zeros from proposed method over the simulated response from NGSPICE. Table 3 in Section 7 shows the calculated results.

As can be seen from Table 3 and Figure 24, since the successive poles/zeros are within 1.5x of each other, they all act as clustered poles/zeros and influenced the circuit analysis/design accordingly. The proposed method was successfully able to predict the location of the poles by identifying the contributing element, enabling the circuit designer to control them as per the requirements of the design.

6.2. Decoupled Poles

Whenever a circuit decouples two nearby shunt resistances, it has decoupled stages which lead to decoupled poles. Therefore, the absence of a shorting connection (i.e., cross-amp capacitance) between the output of the first stage and the input of the next decouples the successive stages. The only possibility of such decoupling in a circuit is with a common-gate/base stage as shown in Figure 25.

For two decoupled poles p₁ and p₂ set by the RC corner frequencies f_I and f_O with f_I < f_O, the poles are given by the individual RC frequencies independent of the other. The first pole becomes the one with the larger RC product. Therefore, p₁ is given by:

$${\mathrm{p}}_1\approx {\mathrm{f}}_{\mathrm{I}}={\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{I}}}^{\prime }{{\mathrm{C}}_{\mathrm{I}}}^{\prime } }}.$$

(73)

Similarly, p₂ is given by the lower RC product as:

$${\mathrm{p}}_2\approx {\mathrm{f}}_{\mathrm{O}}={\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{O}}}^{\prime }{{\mathrm{C}}_{\mathrm{O}}}^{\prime } }}.$$

(74)

Common Source–Common Gate–Common Drain Design Example

Figure 26 shows a general cascaded common source–common gate–common drain circuit. Since v_X and v_Y do not have a shorting connection between them, the common-source stage is decoupled from the common-drain stage. Its transistor parameters are also given in Table 1. It has four independent nodes v_I, v_X, v_Y, and v_O and two cross-amp capacitances (C_GD1, C_GS5). Therefore, it is expected to have four poles and two zeros.

• Low-Frequency Common Source–Common Gate–Common Drain Circuit

Figure 27 shows the small signal equivalent circuit (where the body terminals have been dropped to favor clarity). Here, M_i represents i_gi, and r_dsi. The low-frequency transimpedance gain depends on the different resistances in the signal path from i_S to v_O. The equivalent resistance at the drain of M₁ is:

$${\mathrm{R}}_{\mathrm{D}1}={\mathrm{r}}_{\mathrm{d}\mathrm{s}1}||{\displaystyle \frac{{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}+{\mathrm{r}}_{\mathrm{d}\mathrm{s}3}}{{1+(\mathrm{g}}_{\mathrm{m}2}+{\mathrm{g}}_{\mathrm{m}\mathrm{b}2}){\mathrm{r}}_{\mathrm{d}\mathrm{s}2}}}\approx {\displaystyle \frac{2}{{\mathrm{g}}_{\mathrm{m}2}+{\mathrm{g}}_{\mathrm{m}\mathrm{b}2}}}.$$

(75)

Similarly, the equivalent resistance at the drain of M₂ is:

$${\mathrm{R}}_{\mathrm{D}2}={\mathrm{r}}_{\mathrm{d}\mathrm{s}3}||\left({\mathrm{r}}_{\mathrm{d}\mathrm{s}1}+{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}+{\mathrm{g}}_{\mathrm{m}2}{\mathrm{r}}_{\mathrm{d}\mathrm{s}1}{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}\right)\approx {\mathrm{r}}_{\mathrm{d}\mathrm{s}3}.$$

(76)

The equivalent resistance at the source of M₅ is:

$${\mathrm{R}}_{\mathrm{S}5}={\mathrm{r}}_{\mathrm{d}\mathrm{s}4}||{\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}5}+{\mathrm{g}}_{\mathrm{m}\mathrm{b}5}}}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}5}\approx {\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}5}+{\mathrm{g}}_{\mathrm{m}\mathrm{b}5}}}.$$

(77)

Therefore, the low-frequency transimpedance gain is:

$$\begin{array}{ll}{\mathrm{A}}_{\mathrm{Z}0}& ={\mathrm{R}}_{\mathrm{I}}{\mathrm{A}}_{\mathrm{V}0}={\mathrm{R}}_{\mathrm{S}}{\mathrm{A}}_{\mathrm{V}10}{\mathrm{A}}_{\mathrm{V}20}{\mathrm{A}}_{\mathrm{V}50}\\ & =-{\mathrm{R}}_{\mathrm{I}}{\mathrm{g}}_{\mathrm{m}1}{\mathrm{R}}_{\mathrm{D}1}{\mathrm{g}}_{\mathrm{m}2}{\mathrm{R}}_{\mathrm{D}2}{\mathrm{g}}_{\mathrm{m}5}{\mathrm{R}}_{\mathrm{S}5}\approx -2{\mathrm{R}}_{\mathrm{S}}{\mathrm{g}}_{\mathrm{m}1}{\mathrm{r}}_{\mathrm{d}\mathrm{s}3}.\end{array}$$

(78)

2.

First-Pole Common Source–Common Gate–Common Drain Shunt Circuit

At intermediate frequencies, the circuit is still given by Figure 27 with the capacitances being finite. The RC corner frequencies at each node are compared, and it is found that f_I $\approx$ f_Y with R_I′C_I′ being slightly larger. The equivalent input resistance is:

$${{\mathrm{R}}_{\mathrm{I}}}^{\prime }={\mathrm{R}}_{\mathrm{S}}.$$

(79)

The equivalent input capacitance after application of the cross-amp capacitance split is:

$${{\mathrm{C}}_{\mathrm{I}}}^{\prime }={\mathrm{C}}_{\mathrm{G}\mathrm{S}1}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}\left(1-{\mathrm{A}}_{\mathrm{V}10}\right).$$

(80)

The equivalent resistance at the node v_y is the parallel combination of the output resistance of source degenerated M₂ and r_ds3. Usually, r_ds3 is much lesser and survives:

$${{\mathrm{R}}_{\mathrm{Y}}}^{\prime }={\mathrm{R}}_{\mathrm{D}2}\approx {\mathrm{r}}_{\mathrm{d}\mathrm{s}3}.$$

(81)

The equivalent capacitance at v_y after application of the cross-amp capacitance split is:

$${{\mathrm{C}}_{\mathrm{Y}}}^{\prime }={\mathrm{C}}_{\mathrm{G}\mathrm{D}2}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}3}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}5}+{\mathrm{C}}_{\mathrm{G}\mathrm{S}5}\left(1-{\mathrm{A}}_{\mathrm{V}50}\right).$$

(82)

Since f_I $\approx$ f_Y with R_I′C_I′ being slightly larger, p₁ equals f_I, as noted below:

$${\mathrm{p}}_1\approx {\mathrm{f}}_{\mathrm{I}}={\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{I}}}^{\prime }{{\mathrm{C}}_{\mathrm{I}}}^{\prime }}}={\displaystyle \frac{1}{2\mathsf{\pi }{\mathrm{R}}_{\mathrm{S}}\left({\mathrm{C}}_{\mathrm{G}\mathrm{S}1}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}\left(1-{\mathrm{A}}_{\mathrm{V}10}\right)\right)}}.$$

(83)

3.

Second-Pole Common Source–Common Gate–Common Drain Shunt Circuit

Typically, at frequencies much greater than p₁, R_I′ fades away. However, as R_I′C_I′ ≈ R_Y′C_Y′ in this design, R_I′ persists for p₂ calculation. Thus, the circuit is still given by Figure 27. First, the forward effect is accounted for to get the zero from the common-source stage:

$${\mathrm{z}}_{\mathrm{C}\mathrm{S}}={\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}1}}{2\mathsf{\pi }{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}}}.$$

(84)

Then, the RC product at node v_y is computed to find the next pole as:

$${\mathrm{p}}_2={\mathrm{f}}_{\mathrm{Y}}\approx {\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{Y}}}^{\prime }{{\mathrm{C}}_{\mathrm{Y}}}^{\prime } }}.$$

(85)

4.

Third-Pole Common Source–Common Gate–Common Drain Shunt Circuit

At frequencies much greater than p₂, R_I′ and R_Y′ fade away. Thus, the circuit is redrawn as Figure 28 using cross-amp capacitance splitting for M₅. Again, the RC products are compared to find f_O as the dominant pole. The equivalent output resistance in this new shunt circuit is:

$${{\mathrm{R}}_{\mathrm{O}}}^{‴}\approx {\mathrm{R}}_{\mathrm{S}5}={\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}5}+{\mathrm{g}}_{\mathrm{m}\mathrm{b}5}}}.$$

(86)

The equivalent output capacitance after the application of cross-amp capacitance split for M₅ is:

$${{\mathrm{C}}_{\mathrm{O}}}^{‴}={{\mathrm{C}}_{\mathrm{G}\mathrm{S}5}\left(1-{\displaystyle \frac{1}{{\mathrm{A}}_{\mathrm{V}50}}}\right)+\mathrm{C}}_{\mathrm{G}\mathrm{D}4}+{\mathrm{C}}_{\mathrm{L}\mathrm{D}}.$$

(87)

Therefore, p₃ is given by:

$${\mathrm{p}}_3={\mathrm{f}}_{\mathrm{O}}\approx {\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{O}}}^{‴}{{\mathrm{C}}_{\mathrm{O}}}^{‴}}}.$$

(88)

5.

Fourth-Pole Common Source–Common Gate–Common Drain Shunt Circuit

At frequencies much greater than p₃, R_O‴ fades away. Thus, the circuit is redrawn as Figure 29 by using the feedback-forward splitting concept. First, the forward effect is accounted for to get the zero from the common-drain stage as:

$${\mathrm{z}}_{\mathrm{C}\mathrm{D}}={\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}5}}{2\mathsf{\pi }{\mathrm{C}}_{\mathrm{G}\mathrm{S}5}}}.$$

(89)

Then, the equivalent resistance at v_x is calculated as:

$${{\mathrm{R}}_{\mathrm{X}}}^{\prime \prime \prime \prime }={\mathrm{R}}_{\mathrm{G}\mathrm{M}1}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}1}||{\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}2}+{\mathrm{g}}_{\mathrm{m}\mathrm{b}2}}}||{\mathrm{r}}_{\mathrm{d}\mathrm{s}2}\approx {\mathrm{R}}_{\mathrm{G}\mathrm{M}1}||{\displaystyle \frac{1}{{\mathrm{g}}_{\mathrm{m}2}+{\mathrm{g}}_{\mathrm{m}\mathrm{b}2}}},$$

(90)

where R_GM1 is the voltage-divided g_m resistance of M₁ given by:

$${\mathrm{R}}_{\mathrm{G}\mathrm{M}1}={\displaystyle \frac{{\mathrm{C}}_{\mathrm{G}\mathrm{S}1}+{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}}{{\mathrm{g}}_{\mathrm{m}1}{\mathrm{C}}_{\mathrm{G}\mathrm{D}1}}}.$$

(91)

The equivalent capacitance at v_x includes the effect of the voltage divider established by C_GD1 and C_GS1 in M₁ and is given by:

$${{\mathrm{C}}_{\mathrm{X}}}^{\prime \prime \prime \prime }=\left({\mathrm{C}}_{\mathrm{G}\mathrm{D}1}\oplus {\mathrm{C}}_{\mathrm{G}\mathrm{S}1}\right)+{\mathrm{C}}_{\mathrm{G}\mathrm{S}2}.$$

(92)

Therefore, p₄ is given by:

$${\mathrm{p}}_4={\mathrm{p}}_{\mathrm{X}}\approx {\displaystyle \frac{1}{2\mathsf{\pi }{{\mathrm{R}}_{\mathrm{X}}}^{\prime \prime \prime \prime }{{\mathrm{R}}_{\mathrm{X}}}^{\prime \prime \prime \prime } }}.$$

(93)

6.

Frequency Response for Common Source–Common Gate–Common Drain Circuit

Figure 30 shows the Bode plot overlay of the calculated poles/zeros from proposed method over the simulated response from NGSPICE. Table 3 in Section 7 shows the calculated results.

As can be seen from Table 3 and Figure 30, there is a double pole at 1 MHz which is correctly predicted by the proposed method. Moreover, it identifies the contributing component for each pole and gives the designer a way to insightfully control such clustered poles reliably.

7. Benefits for Design

This section introduces the reader to the design perspective of an IC designer and the appropriate analytical methods investigated for analyzing and designing electronic circuits. It then compares them with the proposed methodology to validate its strength as compared to the others. Finally, the section concludes with comments upon the benefit of using the proposed methodology in addition to commercial circuit simulation tools.

7.1. Design Perspective

An IC design engineer is looking for small-signal circuit analysis methods which allow the engineer to readily and insightfully conceptualize and analyze a circuit to predict performance as reliably as commercial circuit simulation tools. The ability to conceptualize a circuit and decompose it into its fundamental components, helps the engineer to simplify and quicken the design process, since he is designing based on his conceptual understanding, and not trial-and-error using simulations.

This implies that range of applicability, ease of application and computation time are of utmost importance in these methods. Thus, Kirchoff’s circuit laws [11], Miller’s decomposition [14], Huijsing’s capacitance short approximation [18], Andreani and Mattisson’s modification [20] to Cochrun-Grabel’s method [8] and graphical analyses [31,32] are identified as the state-of-the-art (SoA) methods to compare against.

7.2. Direct Analysis

Applying Kirchoff’s laws gets the designer the circuit’s exact transfer function. However, it is a tedious and purely mathematical process. For complicated circuits, the transfer function’s poles and zeros become unsolvable by hand.

A numerical solver can be used to aid the analysis. If the poles are clustered together, the solver may return pairs of complex conjugate poles instead of real ones. In this case, a dominant terms approximation can be used.

To apply the approximation, first, the denominator of the transfer function of the circuit is written in the form of a polynomial as:

$$\mathrm{f}\left(\mathrm{s}\right)={\mathrm{a}}_{\mathrm{n}}{\mathrm{s}}^{\mathrm{n}}+{\mathrm{a}}_{\mathrm{n}-1}{\mathrm{s}}^{\mathrm{n}-1}+\dots +{\mathrm{a}}_1\mathrm{s}+1.$$

(94)

According to this approximation, at extremely low frequencies (for p₁), the linear and constant terms dominate and p₁ is given by:

$${\left.\mathrm{f}\left(\mathrm{s}\right)\right|}_{\mathrm{f}\to {\mathrm{p}}_1}\approx {\mathrm{a}}_1\mathrm{s}+1=0\Rightarrow {\mathrm{p}}_1\approx -{\displaystyle \frac{1}{2\mathsf{\pi }{\mathrm{a}}_1}}$$

(95)

At intermediate frequencies (e.g., p₂), the quadratic and linear terms dominate the expression. This implies that p₂ is given by the following equation:

$${\left.\mathrm{f}\left(\mathrm{s}\right)\right|}_{\mathrm{f}\to {\mathrm{p}}_2}\approx {\mathrm{a}}_2{\mathrm{s}}^2+{\mathrm{a}}_1\mathrm{s}=0\Rightarrow {\mathrm{p}}_2\approx -{\displaystyle \frac{{\mathrm{a}}_1}{2\mathsf{\pi }{\mathrm{a}}_2}}$$

(96)

At even higher frequencies, the subsequent terms dominate and the calculation repeats. Therefore, the p_n becomes:

$${\left.\mathrm{f}\left(\mathrm{s}\right)\right|}_{\mathrm{f}\to {\mathrm{p}}_{\mathrm{n}}}\approx {\mathrm{a}}_{\mathrm{n}}{\mathrm{s}}^{\mathrm{n}}+{\mathrm{a}}_{\mathrm{n}-1}{\mathrm{s}}^{\mathrm{n}-1}=0\Rightarrow {\mathrm{p}}_{\mathrm{n}}\approx -{\displaystyle \frac{{\mathrm{a}}_{\mathrm{n}-1}}{2\mathsf{\pi }{\mathrm{a}}_{\mathrm{n}}}}$$

(97)

Verification: Let $\mathrm{f}\left(\mathrm{s}\right)={\mathrm{s}}^4+57{\mathrm{s}}^3+361{\mathrm{s}}^2+555\mathrm{s}+250.$ The exact roots are −1, −1, −5, and −50 rad/s. The approximation yields −0.45, −1.5, −6.3, and −57 rad/s. Note: This approximation is extremely accurate when each pole is at least a decade away from the others. It is a less accurate but still extremely useful estimate for the locations of clustered poles. However, as explained above, obtaining the circuit’s transfer function (or characteristic equation) for such an analysis becomes a daunting task as the circuit complexity increases.

7.3. Graphical Analyses

As an alternative to the daunting direct analysis, [31] uses driving port impedances combined with signal flow graphs to compute both, the poles, and zeros. While the process is easy to follow and exact, it is mathematically involved and becomes abstruse with increasing circuit complexity. In contrast, [32] develops insight into pole placement and their root-loci but does not connect the poles with changes occurring in the circuit because of them. Therefore, both these methods fail to equip the designer with a streamlined process to control each pole individually.

7.4. Short-Circuit Approximation

Instead of applying the above methods, designers can use an amalgamation of methods [14,18,20] for finding the poles/zeros of a transfer function. Ref. [14] brings insight for the lowest frequency pole. Ref. [18] introduces insight for higher poles but is misguided due to the underlying short circuit assumption– it assumes that capacitances short past their poles and diode-connect their corresponding transistors. This assumption produces 1/g_m instead of the voltage-divided-g_m suggested by (41) or (54) for R_O″ and often leads to errors in the final answer (refer common-source/drain p_O in Table 2).

Zero calculation using [20] is exact but mathematically intensive due to the calculation of multiple driving port time constants. It requires the designer to familiarize himself with two uncommon and not-so-straightforward components: the norator and nullator. It is also devoid of intuition into the circuit behaviour across the entire frequency spectrum.

To emphasize, the SoA methods either ascertain only the poles or zeros or calculate both but are tedious to apply on complicated circuits. Either way, they lack the beauty and simplicity of insight. Ref. [18] is a good compromise as it is the only insightful method (resulting in a simpler design process for larger, complex circuits) amongst the SoA. However, it is limited to the poles and often yields incorrect results.

7.5. Proposed Shunt-Circuit Approximation

The proposed method to calculate frequency response surpasses the SoA by not needing complex mathematical operations regardless of the circuit’s complexity. It offers the design engineer insightful and accurate circuit analysis to predict both poles and zeros across the frequency range while retaining simplicity without losing sight of the circuit’s functionality. It employs a shunt circuit approximation because, capacitances do not short past their poles, instead, their parallel resistances fade. It swiftly makes evident the circuit element responsible for each pole/zero and provides a way to control/account for it in subsequent analyses during circuit design. To reiterate, the proposed method is a physical model (not a mathematical one) based on intuition which is used to conceptualize, analyze and design circuits and not simulating them.

Table 2 compares the poles/zeros (rounded off to two significant figures) calculated using SPICE simulations, Kirchoff’s circuit laws (direct analysis), the SoA comprising of the combination of methods from [14] (p₁), [18] (p₂) and [20] (z₁), and the proposed method. The extraction of poles/zeros from the simulation was straightforward. p₁ is the frequency where the gain drops by 3 dB below the dc value (alternatively, phase loses 45° from the corresponding dc value) and p₂ is the frequency where the phase loses 90° (additional 45º from p₁ and 45º from p₂) from p₁′s phase value. For an inverting zero (e.g., z_CS), z₁ is the frequency where it loses 90° (additional 45° from p₂ and 45° from z₁) from p₂′s phase. On the other hand, for a non-inverting zero (e.g., z_CD), z₁ is the frequency where it partially cancels up to 45° of p₂′s additional loss to return to the same phase value as that of p₂.

Table 2. Simulated Versus Calculated Single-Stage Amplifiers.

Stage	Pole Zero	Sim.	Direct	SoA	Error with Sim.	This Work	Error with Sim.
CG	pO	5.0 MHz	4.9 MHz	4.9 MHz	−2.5%	4.9 MHz	−2.5%
	pI	3.6 GHz	3.6 GHz	3.6 GHz	+1.9%	3.6 GHz	+1.9%
CS	pI	10 kHz	10 kHz	10 kHz	−1.9%	10 kHz	−1.9%
	pO	34 MHz	35 MHz	310 MHz	+810%	34 MHz	−2.6%
	zCS	11 GHz	11 GHz	11 GHz	+0.9%	11 GHz	+0.9%
CD	pI	30 kHz	30 kHz	31 kHz	+3.3%	31 kHz	+3.3%
	pO	3.1 MHz	3.0 MHz	58 MHz	+1800%	3.0 MHz	−3.2%
	zCD	280 MHz	300 MHz	300 MHz	+7.1%	300 MHz	+7.1%

Table 2. Simulated Versus Calculated Single-Stage Amplifiers.

Stage	Pole Zero	Sim.	Direct	SoA	Error with Sim.	This Work	Error with Sim.
CG	pO	5.0 MHz	4.9 MHz	4.9 MHz	−2.5%	4.9 MHz	−2.5%
	pI	3.6 GHz	3.6 GHz	3.6 GHz	+1.9%	3.6 GHz	+1.9%
CS	pI	10 kHz	10 kHz	10 kHz	−1.9%	10 kHz	−1.9%
	pO	34 MHz	35 MHz	310 MHz	+810%	34 MHz	−2.6%
	zCS	11 GHz	11 GHz	11 GHz	+0.9%	11 GHz	+0.9%
CD	pI	30 kHz	30 kHz	31 kHz	+3.3%	31 kHz	+3.3%
	pO	3.1 MHz	3.0 MHz	58 MHz	+1800%	3.0 MHz	−3.2%
	zCD	280 MHz	300 MHz	300 MHz	+7.1%	300 MHz	+7.1%

Since the common-gate circuit did not have a cross-amplifier capacitance, there were fewer approximations in the equations and all the three methods resulted in very similar poles.

For all the methods, the zero expressions were identical to each other. The primary reason being that Kirchoff’s circuit laws and the method in [20], are exact. As are the expressions derived in this work due to complete consideration of the forward effects.

As can be seen from Table 2, the direct analysis gets the closest results to the simulation. This work provides an alternative close approximation to the simulation that is quick and easy to use and provides insight into actual changes in the circuit. Therefore, for demonstrating the strength of the method for multi-stage amplifiers, it will be compared to results obtained from direct analysis.

Table 3. Calculated Multi-Stage Amplifier Examples.

Stage	Pole Zero	Direct	SoA	This Work
CE-CD	pI	4.9 MHz	5.0 MHz	5.0 MHz
	pO	230 MHz 1	450 MHz	280 MHz
	pX	370 MHz 1	950 MHz	390 MHz
	zCD	800 MHz	800 MHz	800 MHz
	zCE	46 GHz	46 GHz	46 GHz
CS-CG-CD	pI	500 kHz 1	1.0 MHz	1.0 MHz
	pY	2.0 MHz 1	17 MHz	1.0 MHz
	pO	60 MHz	70 MHz	70 MHz
	pX	680 MHz	730 MHz	680 MHz
	zCD	2 GHz	2 GHz	2 GHz
	zCD	20 GHz	20 GHz	20 GHz

¹ Calculated using dominant terms method.

Table 3. Calculated Multi-Stage Amplifier Examples.

Stage	Pole Zero	Direct	SoA	This Work
CE-CD	pI	4.9 MHz	5.0 MHz	5.0 MHz
	pO	230 MHz 1	450 MHz	280 MHz
	pX	370 MHz 1	950 MHz	390 MHz
	zCD	800 MHz	800 MHz	800 MHz
	zCE	46 GHz	46 GHz	46 GHz
CS-CG-CD	pI	500 kHz 1	1.0 MHz	1.0 MHz
	pY	2.0 MHz 1	17 MHz	1.0 MHz
	pO	60 MHz	70 MHz	70 MHz
	pX	680 MHz	730 MHz	680 MHz
	zCD	2 GHz	2 GHz	2 GHz
	zCD	20 GHz	20 GHz	20 GHz

¹ Calculated using dominant terms method.

As can be seen from Table 3, this work is very close to the direct analysis even for multi-stage circuits with clustered poles. As shown in Section 6, any large circuit of arbitrary complexity can be decomposed into a combination of the three primitive single-stage transistors stages presented in Section 3, Section 4 and Section 5. With the analyses formally discussed above, any combination of the primitive transistor stages can be completely analyzed and understood.

Once a large circuit is decomposed into its primitive stages (fundamental components), using the method proposed in this work, the design engineer can accurately predict the frequency response during circuit inspection. The accurately calculated poles and zeros streamline the design process and help the designer achieve the desired response in the preliminary design without multiple iterations. With the insight thusly gained, the design engineer can minutely control poles and zeros of any CMOS and bipolar technology circuit without having to rely solely on commercial circuit simulators or symbolic circuit analysis tools for making design decisions. Thus, the method can be very easily used to insightfully understand and design frequency responses of large circuits of arbitrary complexity simply.

Often, symbolic circuit analysis tools used to calculate poles/zeros produce complex equations that are hard to grasp and simplifying them might lead to significant pole/zero displacements from the original locations [33]. Circuit simulators, used to bridge this gap, are inadequate because they depend on numerical factors the engineer may not fully understand– this leads to circuits designed by “trial and error” as opposed to insight. This work enables the engineer to effectively address the aforementioned gap with insight. Since the preliminary design has the desired frequency response, supplementing it with simulations leads to a higher quality design with fewer iterations in the transistor parameters, i.e., the proposed method simplified the analysis and design of the circuit.

After the design engineer has designed a circuit, it needs to be stabilized. Typically, for analog broadband circuits considered in this paper, both open loop and closed loop (with negative feedback) stability are ensured using either dominant-pole compensation or pole-splitting compensation (Miller’s compensation and its variants). This can be achieved using algebraic manipulation [38,39] to extract parameter values, graphical methods [32,40] to vary parameters until desired specifications are met, or solving for phase margin [41] to check stability while varying parameters.

Apart from [41], none of the other methods are as straightforward to employ with increasing circuit complexity. In a similar vein as [41], using the proposed method to predict the poles and zeros, designers can very easily check the stability of the circuit by inspecting the phase margin. Since the proposed method also equips the designer with the insight to control the poles and zeros, tweaking them (in the feedback network or otherwise) to meet specifications becomes a trivial matter. Hence, the proposed method is a design-oriented analytical method which organically lends itself to also simplifying feedback control of circuits regardless of circuit complexity.

8. Conclusions

This paper proposes an insightful design-based frequency response analysis of transistor circuits that also serves as the reference analysis for all single-stage amplifier primitives. The biggest challenge in a frequency response analysis is the lack of an easy, conceptual method to deduce the higher order poles. State-of-the-art (SoA) methods like short-circuit approximations in [18] are applicable but lead to a tedious procedure with often incorrect results. The proposed design-oriented analytical method outperforms the SoA by its ability to predict (without abstract math) and control circuit components that establish poles and zeros in a circuit. It recognizes that shunt capacitances reduce gain to the output, thereby inducing poles. Similarly, bypass capacitances increase gain to the output and induce zeros in the circuit. The proposed method also notes that resistances fade when their parallel capacitances shunt them past their respective RC frequencies. As the resistances fade, the circuit changes and this method equips the design engineer to track all such changes across the entire frequency spectrum while ensuring comprehensive and rigorous results without sacrificing generality. Further, this work also identifies that cross-amplifier capacitances couple subsequent stages and lead to coupled poles in a circuit. By applying this method, the designer can recognize capacitances that cause poles/zeros as well as the coupled/decoupled stages in the circuit during inspection itself. It also provides the engineer with insight into how poles/zeros alter gain in circuits.

This was demonstrated by applying the methodology to design and analyze single-stage common-gate, common-source and common-drain stages and multi-stage cascaded common emitter–common drain and common source–common gate–common drain amplifiers. The results from the method were compared with those from established methods in the literature and NGSPICE simulations. The results agreed with the simulated values in a relatively tight ~5% error band as opposed to 800%+ error in the SoA. This establishes it as an invaluable tool for designers thanks to the insight provided and easier design and control of a stable circuit facilitated, as opposed to designing using abstract algebraic equations which hide concepts and make individual effects of components harder to decipher.