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Volume 14
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Article

Low-Delay AES Key Expansion Units Based on DDBT Structure †

by
Xinxing Zheng
1,2,
Han Yan
3,4,
Zhiwei Peng
3,4 and
Xiaoqiang Zhang
3,4,*
1
School of Information and Artificial Intelligence, Wuhu Institute of Technology, Wuhu 241006, China
2
Wuhu Engineering Technology Research Center of Vehicle Intelligent Product Development and Application, Wuhu 241006, China
3
Anhui Engineering Research Center of Vehicle Display Integrated Systems, Anhui Polytechnic University, Wuhu 241000, China
4
Joint Discipline Key Laboratory of Touch Display Materials and Devices in Anhui Province, Wuhu 241000, China
*
Author to whom correspondence should be addressed.
†
This paper is an extended version of our paper published in Zhang, X.; Peng, Z.; Yan, H.; Zheng, X.; Xu, M. A Low-Delay Circuit Structure Construction Method for AES Key Expansion Units. In Proceedings of the IEEE 19th Conference on Industrial Electronics and Applications, Kristiansand, Norway, 5–8 August 2024.
Electronics 2025, 14(2), 384; https://doi.org/10.3390/electronics14020384
Submission received: 4 October 2024 / Revised: 2 January 2025 / Accepted: 17 January 2025 / Published: 19 January 2025
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Abstract

Advanced Encryption Standard (AES) key expansion unit is usually implemented by chain structure with a long critical path length. That makes key expansion unit become the bottleneck of high-speed AES implementations. In this paper, a design method of low-delay AES key expansion unit is proposed. The proposed design method is based on a delay-drive binary tree (DDBT) structure, which has been proven that it has the shortest critical path length. Based on the proposed design method, a low-delay AES encryption key expansion unit and a low-delay AES encryption/decryption unified key expansion unit are designed in this paper. Both hardware complexity analysis and integrated circuit synthesis indicate that our DDBT-structure-based designs can reduce the delay greatly compared to traditional chain structures. Furthermore, compared to previous works, our designs can achieve the largest throughput.
Keywords: AES; key expansion unit; critical path delay; low-delay circuit structure AES; key expansion unit; critical path delay; low-delay circuit structure

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MDPI and ACS Style

Zheng, X.; Yan, H.; Peng, Z.; Zhang, X. Low-Delay AES Key Expansion Units Based on DDBT Structure. Electronics 2025, 14, 384. https://doi.org/10.3390/electronics14020384

AMA Style

Zheng X, Yan H, Peng Z, Zhang X. Low-Delay AES Key Expansion Units Based on DDBT Structure. Electronics. 2025; 14(2):384. https://doi.org/10.3390/electronics14020384

Chicago/Turabian Style

Zheng, Xinxing, Han Yan, Zhiwei Peng, and Xiaoqiang Zhang. 2025. "Low-Delay AES Key Expansion Units Based on DDBT Structure" Electronics 14, no. 2: 384. https://doi.org/10.3390/electronics14020384

APA Style

Zheng, X., Yan, H., Peng, Z., & Zhang, X. (2025). Low-Delay AES Key Expansion Units Based on DDBT Structure. Electronics, 14(2), 384. https://doi.org/10.3390/electronics14020384

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