Design Strategies for BCAT Structures: Enhancing DRAM Reliability and Mitigating Row Hammer Effect

Abstract

This study investigates the impact of four parameters—gate angles, fin height controlled through gate overlaps and the distance from fin to source/drain, and substrate bottom doping concentration—on the row hammer effect (RHE) in DRAM cells. The influence of adjacent and passing gates on the DRAM cell body potential was identified as a key factor in D0 and D1 failures. The tolerance for D1 and D0 failures was analyzed, defined as the threshold number of pulses required to induce a 0.6 V change in the storage node voltage (from 1.2 V to 0.6 V for a D1 failure or from 0 V to 0.6 V for a D0 failure). D1 (D0) failure tolerances with the slope from the top of the top gate (θ_angle) of 3°, the height of the TiN gate covering the fin (H_{fin_overlap}) of 12.5 nm, and the height of the fin (H_fin) of 12.5 nm are 1.26 × 10⁶ (4.8 × 10⁶), 1.14 × 10⁶ (4 × 10⁷), and 7.5 × 10⁵ (4.8 × 10⁵), respectively. Higher θ_angles and smaller fin heights generally result in higher RHE tolerances. Although decreasing the fin height reduced the RHE, it also decreased the on-current and resulted in an increase in the threshold voltage (V_T) and the subthreshold swing (SS). In addition, by increasing the substrate bottom doping concentration (P_{dop_bot}), we improve RHE tolerance twice its original level without reducing the on-current. Therefore, designing a buried channel array transistor (BCAT) structure requires careful consideration of these trade-offs, and a thorough understanding of the underlying mechanism is crucial to devising strategies that reduce RHE tolerance. The findings of this study are expected to contribute significantly to the development of next-generation DRAM architectures, enhancing stability and performance. By addressing the reliability challenges posed by advanced scaling, this study paves the way for the ongoing advancement of DRAM technology for high-density and high-performance applications.

1. Introduction

Advances in the miniaturization of dynamic random access memory (DRAM) components have significantly enhanced performance and increased density, representing key milestones in semiconductor technology. However, the aggressive scaling of DRAM has resulted in significant reliability challenges that threaten the integrity and functionality of these devices [1,2,3]. Among other issues, the row hammer effect (RHE) has become a growing concern. RHE refers to the repeated activation of a particular word line in a DRAM, which can induce unintended charge loss into neighboring word lines and potentially result in data corruption. As DRAMs become denser, the spacing between cells becomes tighter, making them more vulnerable to electrical interference. Therefore, if a word line is accessed very quickly and frequently, there is an increased risk that charge loss builds up in cells adjacent to that word line, causing a bit flip. This impact threatens the reliability of circuit-level DRAMs and fabricated buried channel array transistor (BCAT) structures due to the RHE [4,5]. Two types of RHEs—D1 failures, characterized by data flipping from 1 to 0, and D0 failures, characterized by data flipping from 0 to 1—present two critical challenges in DRAM technology. D1 failure occurs when repeated access to a row of memory cells disturbs adjacent rows, causing unintended bit flips [6,7,8]. Conversely, D0 failure arises from parasitic coupling and interference between pass gates, leading to leakage currents and potential data corruption [9,10]. In addition to compromising the reliability of DRAM, this phenomenon can also leave serious system-wide vulnerabilities from a security perspective. For example, scenarios have been proposed where an attacker deliberately targets specific cells to flip bits in neighboring cells to compromise data integrity [11]. Currently, there is extensive research on reducing bit flip through systematic solutions such as error correcting codes (ECCs) to prevent bit flip due to row hammer at the software and system level [12,13,14]. However, on the device side, there is a lack of research on analyzing and optimizing D0 and D1 failures due to RHE. Furthermore, although certain studies have identified the limitations of gate formation in BCAT DRAM structures—either by applying angled gates in simulations or by examining actual TEM images— research considering these findings to address D0 and D1 failures caused by the RHE is still limited and insufficient [15,16,17,18].

In this paper, we investigate the electrical characteristics and reliability of the RHE in DRAM cells with geometric and doping modifications using TCAD Sentaurus simulations from Synopsys. This study explains the causes of row hammer in DRAM cell arrays and the pulse operation schemes of single row hammer D1 (SH D1) and D0 (SH D0), while evaluating key parameters in the BCAT structure. We extensively analyze the structural parameters of DRAM cells, focusing on the gate angle, shaped by aspect ratio limitations; the height of the TiN gate covering the fin, which directly contributes to the RHE; and variations in bottom substrate doping, affecting electron migration. Additionally, the transient and DC characteristics of these four parameters are analyzed to evaluate the performance of DRAM cells and D0/D1 failures within the DRAM array. By examining their impact on device performance and reliability, we derive practical implications for future process and design optimization.

2. Device Structure and Mechanism

Figure 1a shows the 3D structure of the saddle-FinFET in DRAM cells using a TCAD simulation. To represent the detailed DRAM cell structure, cross-sectional views of the saddle-FinFET along C2-C2′ (Figure 1b) and C3-C3′ (Figure 1c) are provided, with a particular focus on parameters such as the slope from the top of the top gate (θ_angle), the height of the TiN gate covering the fin (H_{fin_overlap}), the height of the fin (H_fin), and the substrate bottom doping concentration (P_{dop_bot}). The corresponding device parameters, along with their respective values, are presented in

Table 1. Device structure parameter.

Structure Condition	Units	Structure Condition	Units
Total thickness (Ttotal)	300 nm	Gate oxide thickness (Tox)	6 nm
Storage node length (LSN)	20 nm	Poly-Si gate thickness (Tpoly)	30 nm
Bit line node length (LBL)	22 nm	TiN gate thickness (TTiN)	86 nm
Junction thickness (Tj)	50 nm	Θangle	0°
Bulk thickness (Tbulk)	100 nm	Hfin_overlap	50 nm
Top gate length (LTG)	14 nm	Hfin	50 nm
Bottom gate length (LBG)	14 nm	Pdop_bot	1018 cm−3

. This simulation follows the structural parameters of the 10 nm-class technology of saddle-FinFET DRAM [19]. This BCAT structure uses a double gate, and the top metal gate uses n⁺ poly-Si doped at a concentration of 10²⁰ cm⁻³ with an electron affinity of 4.0 eV to reduce gate-induced drain leakage (GIDL), and the bottom gate metal uses TiN with a large work function of 4.6 eV to increase V_T to minimize leakage current and low gate resistance [20]. In this simulation, the non-local path band-to-band tunneling model was adopted to accurately model GIDL current. The doping-dependent mobility model with high field saturation and Lombardi interface charge effects was applied to account for carrier mobility. Recombination processes were modeled using the Shockley–Read–Hall (SRH) recombination model with doping-dependent parameters.

Figure 2a shows a diagram of the DRAM cell array depicting the RHE. Figure 2b illustrates the pulse scheme for single hammer D1 (SH D1), while Figure 2c represents the pulse scheme for single hammer D0 (SH D0). In the SH D1 scheme, the write ‘1’ voltages are applied to the WL3 and BL to write ‘1’ in the cell capacitor (D1, 1.2 V in storage node). Subsequently, repetitive pulses with a 22 ns period (t_r = 1 ns, t_f = 1 ns, t_on = 10 ns, t_off = 10 ns) are applied to the WL2 (aggressor). In the SH D0, the write ‘0’ voltages are applied to the WL2 and BL, as the data are initially set to ‘0’ in the cell capacitor (D0, 0 V in storage node). Then, repetitive pulses with a 22 ns period (t_r = 1 ns, t_f = 1 ns, t_on = 10 ns, t_off = 10 ns) are applied to the WL4 (aggressor). In practice, the row active time (tRAS) value of DRAM is in the range of tens of nanoseconds. However, to observe effective difference based on parameter modulations, the on/off times of the word line and associated timings were considered shorter in this study. Figure 2d shows the D1 failure mechanism, which occurs in DRAM devices when repeated access to a specific word line (the aggressor, WL2) induces disturbances in an adjacent storage node (the victim). This disturbance results from charge loss caused by frequent activation of the aggressor (WL2), potentially leading to unintended bit flip in the nearby victim cell. This phenomenon is particularly pronounced in modern DRAM technologies with smaller process nodes, where the reduced physical distance between cells increases the likelihood of interference, thereby compromising data integrity and security [21]. Figure 2e shows the D0 failure mechanism, which arises from capacitive coupling between neighboring word lines (WL4). When a word line is activated, the resulting electric field can influence neighboring lines, causing unintended disturbances [22]. These disturbances can shift the threshold voltage of nearby victim cells, potentially leading to data errors. As DRAM technology scales down, the susceptibility to coupling-induced error increases, thereby worsening the problem. Building on these insights, the mechanisms of SH D1, where data change from 1 to 0 due to the influence of adjacent gates, and SH D0, where data shift from 0 to 1 due to the influence of pass gates, underscore significant reliability challenges in memory devices.

3. Analysis of Characteristics Through BCAT Structure Modifications

To address reliability degradation caused by row hammer, the BCAT structure of DRAM cell should be investigated by varying key structural parameters related to D0 and D1 failures. First, the effect of the θ_angle on D0 and D1 failures is analyzed as the θ_angle increases from 0° to 3°, considering the limitation aspect ratio in DRAM miniaturization processes, as shown in Figure 3a. In Figure 3a, the left image shows the DRAM cell with the shallow trench isolation (STI) and gate oxide, both composed of SiO₂, removed along the C1-C1′ line, while the right image shows a cross-section along the C2-C2′ line. Figure 3b,c show that the DRAM cell with a θ_angle of 3° achieved the highest on-current at V_WL = 3 V. As shown in Figure 4a,b, the channel length of a DRAM cell decreases from 126 nm at a θ_angle of 0° to 116 nm at a θ_angle of 3°, while the width remains constant. Consequently, as the θ_angle increases, the channel length of the DRAM cell decreases, resulting in an increase in on-current at the same feature size. Figure 3d,e illustrate the effects of D1 failure and D0 failure under varying θ_angle from 0° to 3°. The initial potential of the storage node (V_SN) was set to 1.2 V for D1 failure and 0 V for D0 failure, respectively. As summarized in

Table 2. Gate angle difference.

Gate Angle [°]	Channel Length [nm]	Gate Area (C1-C1′ Line) [nm2]	Distance Between Adjacent Fins [nm]
0	126	1624	22
1	123	1276	26
2	119	1032	29
3	116	777	33

, the gate area decreases with increasing θ_angle, which reduces the impact of the gates on the channel or body of the DRAM cell. Figure 4c and Table 2 show that the distance between adjacent fins (L_fins) increases from 22 nm to 33 nm as the θ_angle increases, thereby improving tolerance. This adjustment enhances device robustness against D1 and D0 failures. The results show that increasing the θ_angle reduced the impact of both D1 failure and D0 failure.

Figure 5a shows the geometric modification of a DRAM cell with varying gate overlap lengths. Similar to Figure 3, the left image of Figure 5a shows the DRAM cell with the SiO₂ removed along the C1-C1′ line, while the right image shows a cross-section along the C3-C3′ line. Figure 5b,c show that as H_{fin_overlap} increases from 12.5 to 50 nm, the on-current also increases, indicating improved gate controllability with a larger H_{fin_overlap}. Figure 5d,e show the vulnerability of DRAM cells to D1 failure and D0 failure at the highest H_{fin_overlap}, following the trend that increased gate overlap leads to greater gate controllability and influence over adjacent gates.

In Figure 6, electrical characteristics of the DRAM cell are analyzed by adjusting the U-shaped fin length to control H_fin, which induces variations in the distances from the source/drain regions to top of fins (L_S/D). In the same way as the previously discussed structural modification illustrations, Figure 6a shows cross-sectional views along C1-C1′ and C3-C3′ of simulated DRAM cells with L_S/D, where H_fin = 12.5 nm. Figure 6b,c show simulated I_SN-V_WL curves of DRAM cells as a parameter of H_fins. The on-current of DRAM cells increases because the channel length decreases as H_fin increases from 12.5 to 50 nm. Operating mechanisms of the D1 and D0 failure with different H_fins (50 nm and 12.5 nm) are investigated in Figure 7. When aggressive signals are applied through the WL2 (aggressor), the electrons that should flow into the bit line node are diverted to the victim node on the right. As shown in Figure 7, the L_S/D decreases as the H_fin increases, leading to a higher current flow. Consequently, more electrons are transported, increasing the number of electrons crossing over to the victim cell, which worsens the occurrence of D1 failure. Furthermore, when examining the D0 failure phenomenon, applying aggressive signals to the WL4 (aggressor) pushes the electrons stored in the victim cell toward the lower region due to the positive voltage. Compared with H_fin of 50 nm on the left, H_fin of 12.5 nm increases the L_S/D, increasing the electron migration distance from 126 to 201 nm. Consequently, electrons escape from the victim cell become more difficult. Therefore, both D1 and D0 failures increase as H_fin increases, as shown in Figure 6d,e.

Figure 8 analyzes the effect of varying the substrate bottom doping concentration (P_{dop_bot}). In Figure 8a, the left image represents the case where P_{dop_bot} is 10¹⁸ cm⁻³, and the right plot corresponds to P_{dop_bot} of 4 × 10¹⁸ cm⁻³ along the C1-C1′ line, respectively. Figure 8b,c show I_SN-V_WL curves, where it can be observed that varying the P_{dop_bot} does not significantly alter the overall I_SN-V_WL curve. This is because the doping changes occur in the deeper substrate regions, rather than the channel region where carriers primarily flow, resulting in minimal impact on the on-current. Furthermore, as shown in Figure 8d,e, higher P_{dop_bot} effectively reduces both D0 and D1 failures. This phenomenon is further analyzed in Figure 9a, which presents the electron current density at T1 = 111 ns, immediately after the WL2 voltage is turned off, as depicted in the pulse scheme of Figure 9b. The left plot corresponds to P_{dop_bot} of 10¹⁸ cm⁻³, and the right plot corresponds to 4 × 10¹⁸ cm⁻³. As the P_{dop_bot} increases, the depletion region expands upward, effectively blocking electrons from entering the storage node of the victim cell, as evidenced by the reduced electron current density. This reduction in electron migration contributes to mitigating D1 failure and can similarly explain the reduction in D0 failure. In Figure 9c, the energy band along the D-D line, where increasing the P_{dop_bot} further suppresses electron migration. However, excessively high P_{dop_bot} can induce gate-induced junction leakage (GIJL), highlighting the importance of optimizing the doping levels.

Figure 10 evaluates the maximum number of pulses the victim cell can withstand. This evaluation is based on D1 and D0 failure tolerance graphs obtained from the four previously discussed modifications. The failure tolerance is defined as the threshold number of pulses required to induce a voltage change in the victim cell, from 1.2 V to 0.6 V (D1 failure) or from 0 V to 0.6 V (D0 failure). Figure 10a shows the D1 failure tolerance of the DRAM victim cell with varying θ_angle, H_{fin_overlap}, H_fin, and P_{dop_bot}, specifically θ_angle = 0°, 1°, and 2°, H_{fin_overlap} = 25, 37.5, and 50 nm, and P_{dop_bot} = 10¹⁸, 2 × 10¹⁸, 3 × 10¹⁸, 4 × 10¹⁸ cm⁻³. Figure 10b shows the D1 failure tolerance for θ_angle = 3°, H_{fin_overlap} = 12.5 nm, and H_fin = 12.5 nm. Higher θ_angles and smaller fin heights generally result in higher tolerances, with significantly higher tolerances observed when θ_angle = 3° and when both H_fin and H_{fin_overlap} were 12.5 nm. Figure 10c shows the D0 failure tolerance of the DRAM victim cell with varying θ_angle, H_{fin_overlap}, H_fin, and P_{dop_bot}, featuring θ_angle = 0°, 1°, and 2°, H_{fin_overlap} = 25, 37.5, and 50 nm, P_{dop_bot} = 10¹⁸, 2 × 10¹⁸, 3 × 10¹⁸, 4 × 10¹⁸ cm⁻³. Figure 10d presents the D0 failure tolerance for θ_angle = 3°, H_{fin_overlap} = 12.5 nm, and H_fin = 12.5 nm. Similar to the D1 failure trend, higher θ_angles and smaller fin heights generally resulted in higher D0 failure tolerances, particularly when the θ_angle = 3° and both H_fin and H_{fin_overlap} were 12.5 nm. These simulation results indicate that reducing the fin height and increasing the θ_angle can mitigate the D1 and D0 failure phenomena induced by miniaturization processes.

Figure 11 demonstrates a decline in device performance when H_fin and H_{fin_overlap} decrease from 50 nm to 12.5 nm in 12.5 nm steps. Specifically, Figure 11a,b show that as H_{fin_overlap} and H_fin decrease from 50 nm to 12.5 nm, the on-current at a word line voltage of 3 V drops by 9.6% and 32.7%, respectively. In Figure 11c, further analysis reveals that a reduction in the fin height from its original 50 nm leads to significant changes in both the threshold voltage (V_T) and the subthreshold swing (SS). For V_T, the value increases from 0.997 at 50 nm to 1.176 for H_{fin_overlap} = 12.5 nm and 1.202 for H_fin = 12.5 nm. Similarly, the SS increase from 119.102 at 50 nm to 144.201 for H_{fin_overlap} = 12.5 nm and 141.602 for H_fin = 12.5 nm. These results indicate that while reducing the fin height enhances resistance to the RHE, excessively low fin heights can lead to increased threshold voltage and degraded subthreshold swing, ultimately resulting in significant performance degradation. Therefore, careful consideration of these trade-offs is critical when designing devices to achieve an optimal balance between row hammer resistance and overall device performance. Moreover, considering the data from our simulation results, if the scaling node of DRAM goes below 14 nm, the physical distance between the gate and the neighboring node will become closer, resulting in increased capacitive coupling. This trend is consistent with the D1 failure and D0 failure caused by the RHE as the DRAM scales down.

4. Conclusions

As the DRAM cell dimensions decrease, these systems become increasingly susceptible to adverse effects such as D1 failure and D0 failure. To address these challenges, the impact of manipulating four parameters such as θ_angle, H_{fin_overlap}, H_fin, and P_{dop_bot} is analyzed. In particular, electrical analysis and an investigation of D1 and D0 failures were conducted with a focus on the θ_angle, which should be considered in the BCAT fabrication. Additionally, we analyze three parameters (H_{fin_overlap}, H_fin, P_{dop_bot}) directly related to the RHE mechanism. Although reducing the fin height can mitigate D1 and D0 failures, it decreases the on-current and causes device degradation. Similarly, increasing the substrate bottom doping concentration can also mitigate D1 and D0 failures, but excessively high doping concentrations near the bottom of the substrate can lead to leakage current. These analysis results show that a larger θ_angle actually increases the row hammer tolerance. The smaller the height of the gate covering the fin, the more effective it is in reducing the RHE, but the lower the on-current. Therefore, it is recommended to minimize the height of the gate covering the fin to the maximum, ensuring it meets the desired on-current requirements. In addition, D0 and D1 failure tolerance can be improved if the bottom substrate doping concentration is appropriately increased to a level that is not affected by GIJL. Thus, designing the BCAT structure with consideration of these trade-offs can enhance the reliability and performance of DRAM components, thereby contributing to the advancement of DRAM technology. This comprehensive analysis examines the correlation between structural changes and their impact on the reliability and robustness of DRAM architectures. It also provides insights into optimizing DRAM cell structures to improve resilience against reliability challenges.