Missing/Extra Via Check Algorithm for Advanced VLSI Analog Designs

Abstract

This paper presents an original algorithm and the application of a Via Check script implemented in the PVS/Pegasus Verification System Tool (Cadence). The algorithm was written in the physical verification language. Via Check is mainly looking for places in the layout where connections (vias) between metals within the same net are missing or could be reinforced. The designed tool was equipped with special user interface graphics to filter the obtained results for more convenient use. It was successfully used in many projects involving advanced submicron technologies like cmos65lp, cmos40lp, stios40nm, stios28nm, 16ff, and 12ff for almost two years. Its application supported by examples of the results from ongoing projects is also included in this publication.

1. Introduction

In analog layout design, the majority of work is usually carried out by hand with no auto routing. The reason behind this is the significant complexity and diversity of circuits. Each analog design has special requirements that need to be met with routing and very often it is not possible to add all these constraints to the autorouter. Even power mesh frequently needs to be individually adapted. For VLSI designs where the same types of circuits are gathered in big matrixes, power mesh cannot be duplicated due to the unevenly distributed signals that go between the power mesh and these circuits. Creating default repeatable mesh for all will leave many empty areas that could be used to make the connection stronger. In design for manufacturability and yield, this is unacceptable [1]. From the point of view of electromigration, each additional connection might be crucial in fulfilling the current limit requirements. Moreover, a greater number of vias meaningfully decreases paths or mesh resistance, which results in fewer signal losses. Unfortunately, while creating big mesh by hand, it is very easy to miss points where metals can be connected, especially with VLSI layouts.

The issue of spot defects in very large scale integration (VLSI) IC manufacturing [2,3] remains a persistent challenge [4,5,6] and cannot be overlooked. Various studies have proposed methods to detect missing via defects, such as the nanocell strategy [4]. However, this approach requires advanced broadband plasma-patterned wafer defect inspection tools, which are not always accessible to all engineers. Additionally, non-traditional methods were explored [5], though they often identify spot defects only in the later stages of circuit design. The algorithm written in the physical verification language (PVL) [7] developed in this work offers a straightforward verification process to assess whether a design can be improved by increasing the number of vias, using a method as simple as running a Design Rule Check (DRC). While it does not pinpoint the exact locations where spot defects may occur, it strengthens the circuit against such defects on a large scale. It can thus serve as a preliminary tool for circuit enhancement. Furthermore, the proposed algorithm was shown to effectively identify areas where vias are insufficiently distributed, reinforcing circuits against this type of defect [8].

A similar approach was introduced in [3], utilizing a DRC tool (Dracula, now obsolete) for implementation. However, the focus of that work was primarily on tracing single vias within a design. While this was a concern at the time of publication, modern technologies have largely standardized the use of one via, mitigating this issue.

It was observed that none of the projects were free from this issue because of the lack of a proper verification tool. Moreover, in VLSI designs, it is impossible to track all of them by eye due to the size and significant number of metals used. Standard verification procedures such as Design Rule Checking (DRC) or Layout Versus Schematic (LVS) are incapable of identifying these kinds of issues. Moreover, currently, there are no existing tools capable of assessing whether the number of applied contacts can be increased within same physically connected net. This solution was developed precisely to address the lack of available verification methods for detecting missing vias in analog layout power distribution grids and therefore improve IC chips’ manufacturability and manufacturing yield. An additional usage is mitigating the impact of spot defects by identifying and addressing wicked areas within the design.

It should be noted that the designed program searches for places between metals within the same net (which is already physically connected – LVS clean), where vias (the connection between metal paths) are missing, or their number can be increased. It is not like LVS (Layout vs. Schematic) verification that searches for opens or shorts. LVS will recognize two physically unconnected paths that should be shorted (Figure 1b) based on the included schematic. If the situation from Figure 1a will be an input for MVC (Missing Via Check), it will show no errors (Figure 1c).

Unlike LVS, for MVC to work, the physical connection between the paths must be at least in one place, as is depicted in Figure 2a. This case for LVS is always a “match” with the schematic (Figure 2b), but MVC will catch areas where vias are missing within the same physically connected net (Figure 2c).

This paper describes an algorithm for creating a tool that finds places between metals of the same net, where vias are missing, or their number can be increased (Section 2). Then, the graphical interface with all functionalities is presented in Section 3. Additional switches for easier analysis of the script results are shown and explained in detail in Section 4, as well as the operation of the tool, with examples taken from ongoing or past projects. Section 5 presents a discussion of the strengths and weaknesses of the algorithm. The paper ends with the conclusions described in Section 6.

2. Algorithm of Via Check

The script was written in the physical verification language (PVL) [9] format and is executed on the Pegasus/PVS system. The Via Check script has the following two main functions:

• Missing Via Check (MVC).
• Extra Via Check (EVC).

Figure 3a presents a circuit that is used to test MVC and EVC operation. It contains two different nets: A (dots) and B (sloping lines).

The blue regions represent metal 1 (M1), the via connecting M1 and M2 (V1) is purple, M2 is green, the via connecting M2 and M3 (V2) is yellow, and M3 is brown. The Missing Via Check will mark all places where metals within the same net are crossing but there is no via between them. The Extra Via Check will mark only places where vias are placed but the metal area there allows the addition of more vias to increase the connection strength.

The Missing Via Check should mark places like those that are marked in red in Figure 3b and the Extra Via Check in Figure 3c. Both MVC and EVC can be run for neighboring metals, as well as for a stack of metals, assuming that between them there is a space to make a stack via connection. This option is explained in detail in Section 3.

2.1. Algorithm Structure

Figure 4 shows a flowchart of the invented algorithm. Each step is described in detail in the subsections. Mx and My are names of the layers between which the algorithm is looking for missing vias.

2.1.1. Initialization of Metals

First, proper layer initialization must take place and then the rules are implemented. The script starts with the definition of all routing layers used based on the GDS (graphic data system) number and physical connections between them.

connect M1 M2 -by V1;

(1)

Each metal connection (via) requires a separate set of rules. For a simple 4-metal technology, the code will have about 250 lines, for a more advanced one with 13 metals, this number increases to more than 1000 command lines. Fortunately, the core of the algorithm may be reduced to a few simple commands that are repeated accordingly for a chosen set of metals. For a more transparent explanation, only missing via and extra via rules between M1 and M2 will be analyzed in this paper.

2.1.2. Common Part of Layers M1 and M2

First of all, the common part of the metals within the same net is extracted (Figure 5). Net recognition is performed by adding the connect option. It checks the physical connection (vias) between metals to recognize separate nets. The results of this operation are given in a separate output layer. In this case, the layer will be named M1_M2.

and M1 M2 -connected -outputlayer M1_M2;

(2)

2.1.3. Straightening Shape M1_M2 If Needed

It may happen that the obtained layer M1_M2 will have a triangular shape, or some edges will have angles different than 90 degrees. We need to modify such angles to obtain rectangular shapes (see Figure 6) as vias are squares or rectangles.

deangle M1_M2 x -skew -orthogonal_only -all M1_M2_D

(3)

The selection of the x value is a compromise between the accuracy of reproducing the original shape and the time needed by the script to execute. If a very small value like 1 nm or 10 nm is chosen, the script execution time will be very long, even a few hours depending on the number of servers used. On the other hand, if x is too high, the shape could be completely lost, as shown in Figure 7.

Non-rectangular shapes are very rare in layouts (despite bumps and highest layer like AP or LB). However, in order for the script to be complete, it must be protected against such a situation. The x value will be heavily dependent on computing power at one disposal. For the projects the script was running, it was set to 100.

The straightened shape will be saved as a new layer with the following name: M1_M2_D.

2.1.4. Stack Via Option

While looking for missing vias connecting metals that are not adjacent, e.g., M1 and M3, one additional command needs to be added between the deangle and size command. To be able to add vias between, e.g., M1 and M3, it needs to be verified that there is no metal or via layer between them. This is why the or command is added.

(…)                 

        deangle M1_M3 x -skew -orthogonal only -all M1_M3_D;

(4)

  or M2 V2 V1 -outputlayer M1_M3_unsized;

(5)

         size M1_M3_unsized -by y -inside_of M1_M3_D V1_V2_enl

(6)

(…)                 

The or command merges together the V1, M2, and V2 layers (see Figure 8). It is important to note that the command connects all existing vias and metals from all nets. It is crucial to check if there is an empty space between M1 and M3 so that the stack via could be placed.

2.1.5. Via Enlargement

Now the V1—via between M1 and M2 needs to be increased by y. Depending on the check type (MVC or EVC), y is defined differently.

• For the Missing Via Check, y should be reasonably large (e.g., 1 µm) to exclude cases that occur in EVC.
• For the Extra Via Check, y is the minimum possible distance between the vias (see Figure 9).

Figure 9. y—Minimum possible distance between vias in matrix.

Figure 9. y—Minimum possible distance between vias in matrix.

Each technology will have different requirements for via spacing. Moreover, within one technology, y will be different for higher vias. Generally, this size depends on metal thickness. In metal stacks, vias are usually grouped, so y should remain the same for each group of vias. In some technologies, one via could also have different sizes, e.g., V1 can be represented as “square”, “bar”, or “large”. Each size will have different spacing requirements. If each size is assigned a separate GDS number, they need to be included as sperate rules or been copied to common layer.

The y variable can be measured directly from layout after running DRC (Design Rule Check) or can be read from the Design Rule Manual for the appropriate technology (recommended).

size V1 -by y -inside_of M1_M2_D V1_enl

(7)

Via V1 is enlarged by y in every direction, as shown in Figure 10. To prevent overlapping from different nets, the enlargement is limited by the M1_M2_D layer. This means that V1 can only grow inside the common straightened part of M1 and M2. The enlarged V1 vias are saved as a new layer named V1_enl.

2.1.6. Subtraction of V1 from Summed M1 and M2

To find weak spots—places where there is no via between metals within the same net or their number can be increased—we must extract the layer (M1_V1_M2), that is subtract the enlarged V1 (V1_enl) from the straighten sum of M1 and M2 (M1_M2_D)—see Figure 11.

not M1_M2_D V1_enl -outputlayer M1_V1_M2

(8)

2.1.7. Verifying If V1 Fits Remaining Area

To check if the remaining area is enough to instantiate the via, it needs to be reduced and then enlarged, as is depicted in Figure 12.

size M1_V1_M2 -by z -underover V1_error

(9)

The layer M1_V1_M2, i.e., the potential area where V1 can be placed, is decreased by z. Similarly to y, the z value depends on the technology and via group. It can be measured from layout or taken from DRM. This value should represent the minimum distance from via canter to the end of connected metals, allowed by the rules (Figure 13).

If the distances from the via center to the border of M1 and M2 are different, the bigger one should be chosen.

After size reduction, which allows the protruding areas to be reduced, the layer should be enlarged again by z to return to its previous dimension, but with adjusted shape. The necessity of this command could be better understood while examining a more complex layer shown in Figure 13. First, the M1_V1_M2 layer is decreased by z (see Figure 14a) from each edge. New layer creation process is shown on Figure 14b with the final shape results shown in Figure 14c. This step removing areas, which are too small to put vias on them from the M1_V1_M2 layer. It can be seen that some narrow places were fully reduced, making the output shape more rectangular. Then, this smooth layer is increased by z (see Figure 14d). Final layer creation process is shown on Figure 14e. At Figure 14f it can be seen that shape M1_V1_V2 (Figure 14a) return to the original boundaries (see Figure 14f) omitting places where additional vias do not fit with layer name V1_error.

Figure 15 very nicely shows how the “size underover” command works, as well as the differences between the input and output layers. It can be clearly seen which edges/areas were smoothened as they are too small to fit the via.

2.1.8. Preparing Input for PVS/Pegasus

The obtained layer V1_error is copied as an input for the DRC Results Viewer tool. This layer corresponds to the area where an additional via can be placed.

   rule missing_V1 {

(10)

copy V1_error;

(11)

            caption Place where V1 via is missing;}

(12)

3. Graphical Interface

The script can be opened within any version of the Pegasus/PVS Design Rule Check tool. To make the script more user-friendly, a graphical interface was created. It includes a few amenities that facilitate result analysis. Figure 16 presents the layout of the Via Check configurator.

The graphical interface is divided into three parts. In Section I, the user can choose the check type to be run: Missing Via Check, Extra Via Check, or both. Then, in section II, the search depth is defined. Figure 17 explains in more detail how deep search works. Section III allows users to specify the metal layers to be analyzed.

For example, the set up presented in Figure 14 will run both MVC and EVC checks (defined in section I on Figure 16), but only for metals M2, M3, M4, and M5 (defined in section III in Figure 16). Via depth: 1 indicates that the tool will be searching for places where a via can be instantiated only between neighbor metals: M1 and M2, M2 and M3, and M3 and M4. Then, via depth: 2 will be looking for areas between M2 and M4 and then M3 and M5 where vias can be added (defined in section II in Figure 16).

4. Application

The tool can be used as well for sub-blocks and whole chip. Because the proposed algorithm is written in the physical verification language, it works satisfactorily fast and does not burden processors significantly.

As is commonly known, the primary differences between standard CMOS, FDSOI, FinFET, and GAA technologies lie in the transistor and base layer structures. Thanks to this, the script can be applied in any technology, requiring only the adjustment of parameters x, y, and z which are described above. Their values are determined based on each technology DRM file. Due to the data confidentiality, it is not possible to disclose the specific project and technologies to which the results presented below pertain.

The algorithm in a simplified form (without filtering options presented in Figure 16) was implemented in the middle of 2022 for the first time. The results obtained after the first run could not be analyzed due to an enormous number of reported errors (like the one shown in Figure 18). The functionalities or rather filtering options described above were implemented after first usage of the script on VLSI design based on user feedback. By using switches from a graphical interface, it is possible to reject unimportant places, which makes result analysis much easier. In addition, with a smaller number of errors, it is less likely that important areas will not be spotted. Currently, the tool is favorably used by several design teams with a more advanced version.

Figure 18a presents the results of running the MVC script in the Pegasus Results Viewer on design with size 1010 µm × 550 µm without selecting depth or metals—it checks all layers. The time of running the script is less than 3 min.

The results can also be displayed in the layout window (see Figure 18b), which allows each error to be tracked more easily.

It can be easily seen that the tool tracks thousands of places—they are marked in red. It is very difficult to analyze all of them, especially with VLSI circuits. We found out that the missing vias at lower metal layers are usually of no interest. The number of places pointed by the tool for them is very large due to the complexity of the design, especially when the script is run on the top of the design. It is recommended to use the MV Tool for lower metal at the subcell circuit level to verify its connections. Nevertheless, the best results are obtained for higher metals where the power mesh or other critical signals are routed. In Figure 19a, only the missing via function and high metals were chosen in the configurator to improve error viewing.

Making results more transparent allows for just a few areas that require via instantiation to be tracked. Figure 20 and Figure 21a,b represent zoomed areas from Figure 19c. These are the results of only the Missing Via Check—the connections (via) between metals that are missed.

In Figure 21a (zoomed Figure 19c (A)), if we put vias in the places marked by the tool in red, we can reduce by half the current flowing from horizontal (green) lines to the vertical (white) lines and thus significantly improve its distribution and reduce electromigration. In the case of Figure 21b (zoomed Figure 19c (C)), one sub-block was missed while connecting the mesh. This is a part of the same repeatable circuit matrix. It passes LVS as ground and power are connected on lower metals, but the strength of this connection is much lower compared to other circuits in the matrix.

Figure 22 is an example of running Extra Via Checks. It marks the place where the cross-section of two neighboring metals allows more vias to be used than placed in the layout. The situation presented in Figure 22 often happens while importing the layout from another similar technology. The vias are not mapped correctly; therefore, their number is incorrect. In extreme cases, only a single via may appear. This kind of situation is very hard to track, especially in VLSI circuits. Increasing the number of vias makes path resistance much lower and helps with electromigration limits, so it is necessary to use the maximum allowed number of vias, especially in power mesh distribution.

Theoretical average complexity of the commands used in the algorithm of MVC is O(NlogN) [10], where N is the number of geometries in the design. Since each time all of the circuits are checked, the overall time complexity of the extraction is dependent only on the complexity of the basic commands used. Therefore, the limit for the size of the circuit which this algorithm can handle is strictly dependent on the efficiency of the DRC tool, which is used to realize this algorithm [2].

5. Application Difficulties

Although the tool is very helpful, using Via Check should be carried out wisely. The designed algorithm points to all the areas where vias are missing. In analog design, sometimes vias are omitted on purpose. A circuit where the star routing is implemented is a good example. Designers need to be aware not to add vias between layers that are part of star routing even if a Via Check points this place as an error. A similar situation occurs in current mirrors. For the current mirror to work properly, it is necessary to connect transistor gates in correct places to minimize voltage drop and ensure proper current distribution. Adding vias to this circuit may lead to current flow disturbance and significantly worsen its performance.

An additional logic layer blocking the Via Check tool could be added to stop the algorithm from looking for missing vias inside the area where this blocking layer is placed. Additionally, it should be decided whether the blocking layer should applied to all metals at once or should be dedicated separately to each metal layer. The disadvantages of this concept are losing algorithm accuracy in the case of one blocking layer or a significant amount of additional work for the layout designer in the case of separate blocking layers for each metal. For now, in past and ongoing projects, there is no need to implement this kind of functionality.

6. Conclusions

A Via Check tool was invented in response to imperfections that appeared in analog IC layouts. This is an original script designed from scratch by the authors. In VLSI designs, it is impossible to track all weak places manually. The script automated this task, saving a lot of time, and eliminated unconnected places almost completely. Via Check was introduced as an internal tool for the analog IC design team and became very useful in quality and verification checks in various projects. The presented algorithm has so far been tested in manufacturing technologies such as cmos65lp, cmos40lp, stios40nm, stios28nm, 16ff, and 12ff. Each time, it tracked tens of places that were not connected as well as they could be.

It is also important to highlight that one of the significant advantages of the proposed algorithm is the ability to be implemented at very early stages of the design process. It can be used just after having the designed circuit LVS cleaned. This early integration allows for efficient and timely design validation. Additionally, the algorithm does not require any additional software beyond the tool used for DRC (Design Rule Checking), making it very easily accessible and cost-effective. The simplicity of this requirement ensures that the process remains streamlined, reducing the need for a complex set up or extra resources, which contributes to faster development and implementation.

Thanks to the continuous use of the script, the quality of the design increased significantly with very small effort from the IC layout designer side. The tool has been used for the past two years across numerous projects, consistently delivering highly satisfactory results.